Patent application number | Description | Published |
20110153893 | Source Core Interrupt Steering - An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. | 06-23-2011 |
20130080674 | Source Core Interrupt Steering - An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. | 03-28-2013 |
20130339565 | METHOD, DEVICE AND SYSTEM FOR AGGREGATION OF SHARED ADDRESS DEVICES - Techniques and mechanisms for managing resources of an aggregate device which spans multiple physical devices of a computer platform. In an embodiment, an aggregation device coupled to a host bus of the computer platform receives resource information generated by a pre-boot software process of the computer platform. In another embodiment, the aggregation device, based on the received resource information, represents a resource in a first input/output (I/O) device to a host operating system (OS) as residing in the aggregation device, the first I/O device coupled to the aggregation device via a host bus for exchanging communications referencing a shared address space. | 12-19-2013 |
20140036909 | SINGLE INSTRUCTION PROCESSING OF NETWORK PACKETS - Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet. | 02-06-2014 |
20140198116 | A METHOD AND DEVICE TO AUGMENT VOLATILE MEMORY IN A GRAPHICS SUBSYSTEM WITH NON-VOLATILE MEMORY - Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command. | 07-17-2014 |
20140281124 | SYSTEM AND METHOD FOR CACHING A STORAGE MEDIUM - A standalone storage cache is responsive to a host independent of drivers or caching logic on the host. The standalone storage cache (standalone cache) interfaces between the host and corresponding storage device, and appears to each as the same I/O interface. I/O requests are sent by the host, and received/acknowledges by the standalone cache as if it were the native storage device. Similarly, the native storage device receives the I/O requests and fetches or stores the corresponding data. Caching logic in the standalone cache determines occupancy in the cache, and identifies when a request can be fulfilled by the cache rather than incurring an I/O to the storage device. No driver or other control need be resident on the host, due to independence of the standalone cache. Since the caching logic is inherent in the standalone cache, existing hosts may benefit from caching without host modification or storage volume upgrade. | 09-18-2014 |
20150134875 | MAINTAINING AT LEAST ONE JOURNAL AND/OR AT LEAST ONE DATA STRUCTURE BY CIRCUITRY - An embodiment may include circuitry to perform option (a) and/or option (b). In option (a), the circuitry may maintain a journal to record information that is related to a transaction that may result in writing to at least one logical address and at least one physical address of the storage. The information may be recorded in the journal via an atomic operation that may be executed prior to recording, at least in part, the information in a data structure that correlates the at least one logical address to the at least one physical address. In option (b), the circuitry may maintain another data structure that indicates a correlation between at least one other physical address and the at least one logical address. The correlation may be valid prior to completion of the transaction, but the correlation may no longer be valid after the completion. | 05-14-2015 |
20150163143 | Reducing Network Latency During Low Power Operation - In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed. | 06-11-2015 |