Patent application number | Description | Published |
20120217506 | III-Nitride Heterojunction Devices Having a Multilayer Spacer - In accordance with one implementation of the present disclosure, a III-Nitride heterojunction device includes a III-Nitride channel layer, a III-Nitride multilayer spacer situated over the III-Nitride channel layer, and a III-Nitride barrier layer situated over the III-Nitride multilayer spacer. A two-dimensional electron gas (2DEG) is formed near an interface of said III-Nitride Channel layer and said III-Nitride multilayer spacer. The III-Nitride multilayer spacer includes a III-Nitride interlayer. In one implementation, the III-Nitride multilayer spacer includes a III-Nitride polarization layer that is situated over the III-Nitride interlayer. The III-Nitride polarization layer has a higher total polarization than the III-Nitride interlayer, the III-Nitride channel layer, and the III-Nitride barrier layer. | 08-30-2012 |
20120223365 | III-Nitride Semiconductor Structures with Strain Absorbing Interlayer Transition Modules - There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure. | 09-06-2012 |
20120235209 | High Voltage Rectifier and Switching Circuits - According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor. | 09-20-2012 |
20120241820 | III-Nitride Transistor with Passive Oscillation Prevention - There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor. | 09-27-2012 |
20120256188 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Lateral Transistor - In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device. | 10-11-2012 |
20120256189 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Vertical Transistor - In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device. | 10-11-2012 |
20120256190 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Diode - In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device. | 10-11-2012 |
20120274366 | Integrated Power Stage - In one implementation, an integrated power stage includes a common die situated over a load stage, the common die includes a driver stage and power switches. The power switches include a control transistor and a sync transistor. A drain of the control transistor receives an input voltage of the common die on one side (e.g., on a top surface) of the common die. A source of the control transistor is coupled to a drain of the sync transistor and provides an output voltage of the common die on an opposite side (e.g., on a bottom surface) of the common die. An interposer may be included under the power stage and includes an output inductor and optionally an output capacitor coupled to the output voltage of the common die on the opposite side of the common die. | 11-01-2012 |
20130015498 | Composite Semiconductor Device with Integrated Diode - There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a transition body formed over a diode, the transition body including more than one semiconductor layer. The composite semiconductor device also includes a transistor formed over the transition body. The diode may be connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two. | 01-17-2013 |
20130015499 | Composite Semiconductor Device with a SOI Substrate Having an Integrated Diode - There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a semiconductor on insulator (SOI) substrate including a diode and an insulator layer. The composite semiconductor device also includes a transition body formed over the diode, and a transistor formed over the transition body. The diode is connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two. | 01-17-2013 |
20130015501 | Nested Composite Diode - There are disclosed herein various implementations of nested composite diodes. In one implementation, a nested composite diode includes a primary transistor coupled to a composite diode. The composite diode includes a low voltage (LV) diode cascoded with an intermediate transistor having a breakdown voltage greater than the LV diode and less than the primary transistor. In one implementation, the primary transistor may be a group III-V transistor and the LV diode may be an LV group IV diode. | 01-17-2013 |
20130015905 | Nested Composite Switch - There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor. | 01-17-2013 |
20130069208 | Group III-V Device Structure Having a Selectively Reduced Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 03-21-2013 |
20130105814 | Active Area Shaping for III-Nitride Devices | 05-02-2013 |
20130161803 | Semiconductor Package with Conductive Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 06-27-2013 |
20130175542 | Group III-V and Group IV Composite Diode - In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die. | 07-11-2013 |
20130196490 | Method and Apparatus for Growing a III-Nitride Layer - A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method. | 08-01-2013 |
20130207120 | Power Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. | 08-15-2013 |
20130214283 | Power Transistor Having Segmented Gate - There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off. | 08-22-2013 |
20130214330 | Transistor Having Increased Breakdown Voltage - There are disclosed herein various implementations of a transistor having an increased breakdown voltage. Such a transistor includes a source finger electrode having a source finger electrode beginning and a source finger electrode end. The transistor also includes a drain finger electrode with a curved drain finger electrode end having an increased radius of curvature. The resulting decreased electric field at the curved drain finger electrode end allows for an increased breakdown voltage and a more robust and reliable transistor. In some implementations, the curved drain finger electrode end may be extended beyond the source finger electrode beginning to achieve the increased breakdown voltage. | 08-22-2013 |
20130240898 | Group III-V and Group IV Composite Switch - In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die. | 09-19-2013 |
20130256694 | Programmable Gate III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a charged gate insulation body. | 10-03-2013 |
20130292694 | Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure - According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge. | 11-07-2013 |
20130299877 | Integrated III-Nitride and Silicon Device - A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body. | 11-14-2013 |
20130299878 | Transistor Having Elevated Drain Finger Termination - According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature. | 11-14-2013 |
20130334574 | Monolithic Integrated Composite Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 12-19-2013 |
20130337626 | Monolithic Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in. the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a side-wall of the trench. | 12-19-2013 |
20130342184 | Monolithic Group III-V Power Converter - A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches. | 12-26-2013 |
20140008663 | Integrated Composite Group III-V and Group IV Semiconductor Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 01-09-2014 |
20140027778 | Robust Fused Transistor - According to an exemplary implementation, a transistor includes a plurality of drain fingers interdigitated with a plurality of source fingers. The transistor further includes a gate configured to control current conduction between the plurality of drain fingers and the plurality of source fingers. Additionally, the transistor includes a plurality of drain fuses, each being configured to electrically disconnect a drain finger of the plurality of drain fingers from remaining ones of the plurality of drain fingers. At least one of the plurality of drain fuses can electrically couple the drain finger to a common drain pad. The transistor may further include a plurality of source fuses, each being configured to electrically disconnect a source finger of the plurality of source fingers from remaining ones of the plurality of source fingers. | 01-30-2014 |
20140034959 | III-Nitride Semiconductor Device with Stepped Gate - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 02-06-2014 |
20140035005 | Monolithic Integrated Group III-V and Group IV Device - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 02-06-2014 |
20140070278 | Active Area Shaping of III-Nitride Devices Utilizing Multiple Dielectric Materials - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a dielectric body situated over the III-nitride heterojunction and including a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than the first dielectric material. A gate well of a first width is defined by the first dielectric layer, and is of a second width defined by the second dielectric layer, where the second width is greater than the first width. The III-nitride semiconductor device further includes a gate arrangement situated in the gate well and including a gate electrode integrated with a field plate. | 03-13-2014 |
20140070279 | Active Area Shaping of III-Nitride Devices Utilizing a Source-Side Field Plate and a Wider Drain-Side Field Plate - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include steps, and the drain-side field plate is wider than the source-side field plate. | 03-13-2014 |
20140070280 | Active Area Shaping of III-Nitride Devices Utilizing Steps of Source-Side and Drain-Side Field Plates - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include one or more steps, where the drain-side field plate has a different number of the one or more steps than the source-side field plate. | 03-13-2014 |
20140070627 | Integrated Group III-V Power Stage - In one implementation, an integrated group III-V power stage includes a control switch including a first group III-V transistor coupled to a sync switch including a second group III-V transistor. The integrated group III-V power stage may also include one or more driver stages, which may be fabricated in a group die or dies. The driver stage or driver stages, the control switch, and the sync switch may all be situated in a single semiconductor package. | 03-13-2014 |
20140084431 | Semiconductor Package with Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 03-27-2014 |
20140097471 | Active Area Shaping of III-Nitride Devices Utilizing A Field Plate Defined By A Dielectric Body - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. The III-nitride semiconductor device also includes a gate arrangement situated in the gate well and including a gate electrode and a field plate. The field plate includes at least two steps, the at least two steps being defined in the dielectric body. | 04-10-2014 |
20140106548 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 04-17-2014 |
20140147998 | Ion Implantation at High Temperature Surface Equilibrium Conditions - There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber. | 05-29-2014 |
20140159116 | III-Nitride Device Having an Enhanced Field Plate - In an exemplary implementation, a semiconductor device includes a III-nitride heterojunction including a III-nitride barrier layer situated over a III-nitride channel layer to form a conduction channel including a two-dimensional electron gas. The semiconductor device further includes a gate electrode coupled to a field plate. The field plate includes a plurality of steps insulated from the conduction channel by a dielectric body and the III-nitride barrier layer. The dielectric body under each one of the plurality of steps contributes to a breakdown voltage that is at least twice a breakdown voltage of the semiconductor device at each corresponding step. The breakdown voltage can correspond to a breakdown voltage of the dielectric body and the III-nitride barrier layer. | 06-12-2014 |
20140167112 | Cascode Circuit Integration of Group III-N and Group IV Devices - In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can he situated over the group IV transistor die. | 06-19-2014 |
20140192441 | DC/DC Converter with III-Nitride Switches - Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. | 07-10-2014 |
20140197461 | Semiconductor Structure Including A Spatially Confined Dielectric Region - There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed under the drain in the substrate, the spatially confined dielectric region reducing a capacitive coupling of the drain to the substrate. In another exemplary implementation, a spatially confined dielectric region is formed under each of the source and the drain of the FET, in the substrate, the spatially confined dielectric regions reducing a capacitive coupling of the source and the drain to the substrate. | 07-17-2014 |
20140197462 | III-Nitride Transistor with High Resistivity Substrate - There are disclosed herein various implementations of semiconductor structures including high resistivity substrates. In one exemplary implementation, such a semiconductor structure includes a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm), and a III-N high electron mobility transistor (HEMT) having a drain, a source, and a gate, fabricated over the substrate. The III-N HEMT is configured to produce a two-dimensional electron gas (2 DEG). The resistivity of the substrate reduces the capacitive coupling of the 2 DEG to the substrate. In one implementations, a spatially confined dielectric region is formed in the substrate, under at least one of the drain and the source. | 07-17-2014 |
20140203295 | INTEGRATED POWER DEVICE WITH III-NITRIDE HALF BRIDGES - A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die. | 07-24-2014 |
20140213046 | Fabrication of III-Nitride Layers - A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method. | 07-31-2014 |
20140239349 | Drain Pad Having a Reduced Termination Electric Field - In an exemplary implementation, a semiconductor device includes a drain pad on a semiconductor substrate, the drain pad being coupled to a plurality of drain fingers. The semiconductor device further includes a source pad on the semiconductor substrate, the source pad being coupled to a plurality of source fingers. The plurality of source fingers is interdigitated with the plurality of drain fingers. Furthermore, an outer corner of the drain pad has a gradual transition between adjoining sides of the drain pad. The gradual transition between the adjoining sides of the drain pad reduces a termination electric field at the outer corner of the drain pad. Furthermore, the gradual transition between the adjoining sides of the drain pad increases the breakdown voltage of the semiconductor device. | 08-28-2014 |
20140252375 | Delamination and Crack Prevention in III-Nitride Wafers - In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches. | 09-11-2014 |
20140253217 | RF Switch Gate Control - In one implementation, a switching circuit includes a pass switch including group III-V, for example III-Nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch. | 09-11-2014 |
20140339605 | Group III-V Device with a Selectively Reduced Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 11-20-2014 |
20140339686 | Group III-V Device with a Selectively Modified Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 11-20-2014 |
20140353723 | High Voltage Durability III-Nitride Device - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT. | 12-04-2014 |
20140367744 | Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and IC - There are disclosed herein various implementations of a monolithic vertically integrated composite device. Such a composite device may include one or more group IV device fabricated in a group IV semiconductor body formed over a first side of a double sided substrate, and one or more group III-V device fabricated in a group III-V semiconductor body formed over a second side of the double sided substrate opposite the first side. In one implementation, the one or more group IV device may be a PN junction diode or a Schottky diode. In another implementation, the one or more group IV device may be a field-effect transistor (PET). In yet another implementation, such a composite device monolithically integrates one or more group III-V device and a group IV integrated circuit (IC). The one or more group III-V device and one or more group IV device and/or IC may be electrically coupled using one or more of a substrate via and a through-wafer via. | 12-18-2014 |
20140375242 | Depletion Mode Group III-V Transistor with High Voltage Group IV Enable Switch - There are disclosed herein various implementations of a half-bridge or multiple half-bridge switch configurations used in a voltage converter circuit using at least two normally ON switches. Such a circuit includes a high side switch and a low side switch coupled between a high voltage rail and a low voltage rail of the voltage converter circuit. The high side switch is coupled to the low side switch at a switch node of the voltage converter circuit. At least one group IV enhancement mode switch is used as an enable switch. The group IV enhancement mode enable switch may be an insulated gate bipolar transistor (IGBT), a super junction field-effect transistor (SJFET), a unipolar group IV field-effect transistor (FET), or a bipolar junction transistor (BJT). | 12-25-2014 |
20150014698 | Integrated III-Nitride D-Mode HFET with Cascoded Pair Half Bridge - There are disclosed herein various implementations of a group III-V power conversion circuit including a monolithically integrated half bridge having a depletion mode III-Nitride field-effect transistor (FET), and a normally OFF composite cascoded switch including a depletion mode III-Nitride FET and an enhancement mode group IV FET. In one exemplary implementation, the monolithically integrated half bridge includes a high side depletion mode III-Nitride FET having an enable switch coupled in the conduction path of the high side depletion mode III-Nitride FET. | 01-15-2015 |
20150014701 | III-Nitride Semiconductor Device with Reduced Electric Field - A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N | 01-15-2015 |
20150014703 | III-NITRIDE Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. | 01-15-2015 |
20150014740 | Monolithic Composite III-Nitride Transistor with High Voltage Group IV Enable Switch - There are disclosed herein various implementations of a monolithically integrated component. In one exemplary implementation, such a monolithically integrated component includes an enhancement mode group IV transistor and two or more depletion mode III-Nitride transistors. The enhancement mode group IV transistor may be implemented as a group IV insulated gate bipolar transistor (group IV IGBT). One or more of the III-Nitride transistor(s) may be situated over a body layer of the group IV IGBT, or the III-Nitride transistor(s) may be situated over a collector layer of the IGBT. | 01-15-2015 |
20150021619 | III-Nitride Semiconductor Device with Reduced Electric Field Between Gate and Drain - A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N | 01-22-2015 |
20150037965 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 02-05-2015 |
20150115327 | Group III-V Device Including a Buffer Termination Body - There are disclosed herein various implementations of a III-Nitride device and method for its fabrication. The III-Nitride device includes a III-Nitride buffer layer situated over a substrate, the III-Nitride buffer layer having a first bandgap. In addition, the device includes a III-Nitride heterostructure situated over the III-Nitride buffer layer and configured to produce a two-dimensional electron gas (2DEG); the III-Nitride heterostructure including a channel layer having a second bandgap smaller than the first bandgap. The III-Nitride device also includes a buffer termination body situated between the III-Nitride buffer layer and the channel layer, the buffer termination body including a III-Nitride material having a third bandgap smaller than the first bandgap and larger the second bandgap. | 04-30-2015 |
20150155358 | Group III-V Transistor with Semiconductor Field Plate - There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer. | 06-04-2015 |
20150162321 | Composite Power Device with ESD Protection Clamp - There are disclosed herein various implementations of a normally off (enhancement mode) composite power device with an ESD protection clamp. Such a normally off composite power device includes a normally on (depletion mode) power transistor providing a composite drain of the normally off composite power device, and a normally off low voltage (LV) transistor cascoded with the normally on power transistor. The normally off LV transistor provides a composite source and a composite gate of the normally off composite power device. The normally off composite power device also includes the ESD protection clamp coupled between the composite source and the composite gate. The ESD protection clamp is configured to provide electrostatic discharge (ESD) protection for the normally off composite power device. | 06-11-2015 |
20150162424 | Dual-Gated Group III-V Merged Transistor - There are disclosed herein various implementations of a group III-V merged cascode transistor. Such a group III-V merged cascode transistor includes a group III-V body disposed over a substrate and configured to produce a two-dimensional electron gas (2DEG). The group III-V body includes a group III-V barrier layer situated over a group III-V channel layer, and a source electrode and a drain electrode. The group III-V merged cascode transistor also includes an enable gate disposed in a recess extending substantially through the group III-V barrier layer, and an operational gate disposed over the group III-V barrier layer, the operational gate not being in physical contact with the enable gate. | 06-11-2015 |
20150162832 | Group III-V Voltage Converter with Monolithically Integrated Level Shifter, High Side Driver, and High Side Power Switch - There are disclosed herein various implementations of a monolithically integrated high side block. Such a monolithically integrated high side block includes a level shifter, a high side driver coupled to the level shifter, and a high side power switch coupled to the high side driver. The high side power switch is monolithically integrated with the high side driver and the level shifter on a common die. Each of the level shifter, the high side driver, and the high side power switch includes at least one group III-V device. | 06-11-2015 |