Patent application number | Description | Published |
20080285443 | METHOD FOR MONITORING CHANNEL EYE CHARACTERISTICS IN A HIGH-SPEED SERDES DATA LINK - A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the eye characteristics of the channels used by the local side physical layer to transfer data to the remote side physical layer, transferring eye characteristics acquired in the monitoring to the local side physical layer and processing the eye characteristics by the local side physical layer to generate equalization setting adjustments. | 11-20-2008 |
20080285453 | METHOD FOR MONITORING BER IN AN INFINIBAND ENVIRONMENT - A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the bit error rate (BER) of the channels used by the local side physical layer to transfer data to the remote side physical layer, monitoring the BER in the channels used for data transfer, transferring BER data acquired in the monitoring to the local side physical layer and processing the BER data by the local side physical layer to generate equalization setting adjustments. | 11-20-2008 |
20090245110 | SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT - A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring signal eye characteristics in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the signal eye characteristics at the local side to generate the remote side transmission characteristics for the link channel. | 10-01-2009 |
20090257514 | SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT - A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring the bit error rate (BER) in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the BER data at the local side to generate the remote side transmission characteristics for the link channel. | 10-15-2009 |
20130301207 | 276-PIN BUFFERED MEMORY CARD WITH ENHANCED MEMORY SYSTEM INTERCONNECT - An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the rectangular printed circuit card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. | 11-14-2013 |
20140112063 | IMPLEMENTING SDRAM HAVING NO RAS TO CAS DELAY IN WRITE OPERATION - A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit resides are provided. A first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) is provided to the SDRAM for a read operation. A second delay tRCD is provided for a write operation that is substantially shorter than the first delay tRCD for the read operation. | 04-24-2014 |
20140268973 | 276-PIN BUFFERED MEMORY CARD WITH ENHANCED MEMORY SYSTEM INTERCONNECT - An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals. | 09-18-2014 |
20140289488 | SYSTEM FOR SECURING CONTENTS OF REMOVABLE MEMORY - This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled. | 09-25-2014 |