Patent application number | Description | Published |
20090155552 | IC CHIP PACKAGE SUBSTRATE HAVING OUTERMOST GLASS FIBER REINFORCED EPOXY LAYERS AND RELATED METHOD - An IC chip package having a glass reinforced outermost epoxy layers and related method are disclosed. In one embodiment, the IC chip package includes an IC chip; and a substrate coupled to the IC chip, the substrate including a glass fiber reinforced epoxy core, a plurality copper circuitry containing, particle reinforced epoxy layers symmetrically-oriented to each surface of the glass fiber reinforced epoxy core, and an outermost glass fiber reinforced epoxy layer on each surface of the plurality of layers, wherein the IC chip is coupled to copper circuitry bonded to one of the outermost glass fiber reinforced epoxy layer. | 06-18-2009 |
20120061848 | CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHESIVE LAYER - A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffner. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffner can be tailored so that the thermal coefficient of expansion of the stiffner provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon. | 03-15-2012 |
20130157439 | CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHESIVE LAYER - A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon. | 06-20-2013 |
20130320069 | METHOD FOR SHAPING A LAMINATE SUBSTRATE - A method for shaping a laminate substrate includes characterizing the laminate substrate for warpage characteristics. The laminate substrate is placed into a fixture with a correction to shape the laminate substrate based on the warpage characteristics. The laminate substrate is fluxed. A chip is placed onto the laminate substrate. The fixture is placed into a reflow furnace to join the chip and the laminate substrate. The fixture is removed from the reflow furnace. A warpage measurement is performed on the joined chip and laminate substrate. The correction may be modified if shorts are observed at the chip site. | 12-05-2013 |
20140359995 | CONSTRAINED DIE ADHESION CURE PROCESS - A clamping apparatus applies a force to a workpeice during processing. The clamping apparatus includes a base defining a work area configured to receive a joined structure having multiple elements. The base defines a recess in the work area. An adjustable mechanism is configured to releasably couple to the base and apply a adjustable downward force to the joined structure to bend the joined structure downwardly into the recess during a process. A resilient plunger is part of the adjustable mechanism. The resilient plunger extends downwardly from a top plate of the adjustable mechanism, and the resilient plunger is configured to contact a top of a first element of the joined structure to apply the downward force. | 12-11-2014 |
20150014836 | Electronic Module Assembly With Patterned Adhesive Array - An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress. | 01-15-2015 |
Patent application number | Description | Published |
20090294971 | ELECTROLESS NICKEL LEVELING OF LGA PAD SITES FOR HIGH PERFORMANCE ORGANIC LGA - A structure comprises: a substrate; at least one conductor on the substrate; at least one contact pad on the substrate; a mask over the conductor (wherein the mask comprises an opening over the contact pad and wherein the mask comprises a bottom surface contacting the substrate and a top surface opposite the bottom surface); and a contact pad plating layer on the contact pad and within the opening of the mask. The contact pad plating layer comprises a bottom surface contacting the contact pad and a top surface opposite the bottom surface, and the top surface of the contact pad plating layer is coplanar with the top surface of the mask. | 12-03-2009 |
20100164030 | CHIP CARRIER BEARING LARGE SILICON FOR HIGH PERFORMANCE COMPUTING AND RELATED METHOD - Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers. | 07-01-2010 |
20130320578 | METHOD FOR SHAPING A LAMINATE SUBSTRATE - A method for shaping a laminate substrate includes characterizing the laminate substrate for warpage characteristics over a range of temperatures. The laminate substrate is placed into a shaping fixture with any necessary correction to obtain a flat laminate substrate chip site area at a chip join temperature. The laminate substrate is shaped at a temperature greater than or equal to a maximum laminate substrate fabrication temperature. The shape of the laminate substrate is retained when it is removed from the shaping fixture. | 12-05-2013 |
20130323345 | FIXTURE FOR SHAPING A LAMINATE SUBSTRATE - A fixture for shaping a laminate substrate includes a trap ring, a base plate and a center button. The base plate includes a recess adapted to receive the laminate substrate. The center button is disposed in an opening in the base plate. The center button may be adjusted to shape the laminate substrate. | 12-05-2013 |
Patent application number | Description | Published |
20090093066 | GLYCATED PEPTIDES AND METHODS OF USE - The invention provides glycated peptides and glycated fragments and glycated variants thereof, antibodies and aptamers which bind thereto, compositions and kits comprising the same, related conjugates, and a database comprising data indicating the concentration of glycated peptides present in diabetic and non-diabetic persons. The invention also provides a method of monitoring glycemic control, a method of treating or preventing diabetes, a method of preventing a complication of diabetes, a method of monitoring the status of diabetes, a method of determining the efficacy of a diabetes treatment, as well as methods of detecting diabetes or a predisposition thereto. | 04-09-2009 |
20110092428 | DETECTING AND CONTROLLING ABNORMAL HEMATOPOIESIS - A method of detecting abnormal hematopoiesis in a subject based on abnormal expression of ZFP36L2, a method of controlling hematopoiesis in a subject altering the level or activity of ZFP36L2 protein in the subject, a method of screening for compounds that modulate hematopoiesis based on changes to ZFP36L2 expression, and compounds identified thereby. | 04-21-2011 |