Patent application number | Description | Published |
20100205669 | O-TOUCH AND 1-TOUCH TECHNIQUES FOR IMPROVING THE AVAILABILITY OF COMPUTER PROGRAMS UNDER PROTECTION WITHOUT COMPROMISING SECURITY - Protected software, such as an application and/or DLL, is monitored by protective software to guard against attacks, while distinguishing spurious, benign events from attacks. In a 1-touch approach, the protected software is monitored in a testing environment to detect spurious, benign events caused by, e.g., incompatibility or interoperability problems. The spurious events can be remediated in different ways, such as by applying a relaxed security policy. In a production mode, or 0-touch mode, when the protected software is subject to attacks, the corresponding remediation can be applied when the spurious events are again detected. Security events which occur in production mode can also be treated as benign when they occur within a specified time window. The applications and/or DLLs can further be classified according to whether they are known to have bad properties, known to be well-behaved, or unknown. Appropriate treatment is provided based on the classification. | 08-12-2010 |
20110185433 | CONSTRAINT INJECTION SYSTEM FOR IMMUNIZING SOFTWARE PROGRAMS AGAINST VULNERABILITIES AND ATTACKS - A constraint is inserted into a program to address a vulnerability of the program to attacks. The constraint includes a segment of code that determines when the program has been asked to execute a “corner case” which does not occur in normal operations. The constraint code can access a library of detector and remediator functions to detect various attacks and remediate against them. Optionally, the detector can be employed without the remediator for analysis. The context of the program can be saved and restored if necessary to continue operating after remediation is performed. The constraints can include descriptors, along with machine instructions or byte code, which indicate how the constraints are to be used. | 07-28-2011 |
20110219447 | Identification of Unauthorized Code Running in an Operating System's Kernel - Computer implemented methods, system and apparatus for managing execution of a running-page in a virtual machine include associating an execution trace code with the running page by a security virtual machine. The execution trace code generates a notification upon initiation of the execution of the running page by the virtual machine. The notification is received by the security virtual machine running independent of the virtual machine executing the running-page. The running page associated with the execution trace code is validated by the security virtual machine as authorized for execution. An exception is generated if the running-page is not authorized for execution. The generated exception is to prevent the execution of the running page in the virtual machine. | 09-08-2011 |
Patent application number | Description | Published |
20140244193 | BATTERY STATE OF CHARGE TRACKING, EQUIVALENT CIRCUIT SELECTION AND BENCHMARKING - A method includes calculating a first estimated state of charge (SOC) of a battery at a first time, receiving a voltage value representing a measured voltage across the battery at a second time, calculating a filter gain at the second time, and calculating a second estimated SOC of the battery at the second time based on the first estimated SOC, the voltage value, and the filter gain. Another method includes storing, in a memory, a library of equivalent circuit models representing a battery, determining an operational mode of a battery based on a load associated with the battery, selecting one of the equivalent circuit models based on the determined operational mode, and calculating a state of charge of charge (SOC) of the battery using the selected equivalent circuit model. | 08-28-2014 |
20140244225 | BATTERY STATE OF CHARGE TRACKING, EQUIVALENT CIRCUIT SELECTION AND BENCHMARKING - A method includes calculating a first estimated state of charge (SOC) of a battery at a first time, receiving a voltage value representing a measured voltage across the battery at a second time, calculating a filter gain at the second time, and calculating a second estimated SOC of the battery at the second time based on the first estimated SOC, the voltage value, and the filter gain. Another method includes storing, in a memory, a library of equivalent circuit models representing a battery, determining an operational mode of a battery based on a load associated with the battery, selecting one of the equivalent circuit models based on the determined operational mode, and calculating a state of charge of charge (SOC) of the battery using the selected equivalent circuit model. | 08-28-2014 |
Patent application number | Description | Published |
20090196338 | ENTROPY CODING EFFICIENCY ENHANCEMENT UTILIZING ENERGY DISTRIBUTION REMAPPING - Architecture for enhancing the compression (e.g., luma, chroma) of a video signal and improving the perceptual quality of the video compression schemes. The architecture operates to reshape the normal multimodal energy distribution of the input video signal to a new energy distribution. In the context of luma, the algorithm maps the black and white (or contrast) information of a picture to a new energy distribution. For example, the contrast can be enhanced in the middle range of the luma spectrum, thereby improving the contrast between a light foreground object and a dark background. At the same time, the algorithm reduces the bit-rate requirements at a particular quantization step size. The algorithm can be utilized also in post-processing to improve the quality of decoded video. | 08-06-2009 |
20090213933 | TEXTURE SENSITIVE TEMPORAL FILTER BASED ON MOTION ESTIMATION - Architecture that employs texture sensitive temporal filtering to reuse motion estimation information in a realtime encoder. The temporal filter is applied for classified static areas. The architecture reuses the motion estimation results on motion vectors, cost estimates (e.g., sum of absolute difference (SAD)), and edge awareness texture information to apply the temporal filter on the current picture. Filtering can be applied at the pixel level, block level or macroblock level. | 08-27-2009 |
20140169473 | TEXTURE SENSITIVE TEMPORAL FILTER BASED ON MOTION ESTIMATION - Architecture that employs texture sensitive temporal filtering to reuse motion estimation information in a realtime encoder. The temporal filter is applied for classified static areas. The architecture reuses the motion estimation results on motion vectors, cost estimates (e.g., sum of absolute difference (SAD)), and edge awareness texture information to apply the temporal filter on the current picture. Filtering can be applied at the pixel level, block level or macroblock level. | 06-19-2014 |
Patent application number | Description | Published |
20090279605 | ENCODING STREAMING MEDIA AS A HIGH BIT RATE LAYER, A LOW BIT RATE LAYER, AND ONE OR MORE INTERMEDIATE BIT RATE LAYERS - A method of encoding an input video stream comprising a video component and an audio component is disclosed. The input video stream is split into a plurality of segments, each comprising a plurality of frames. Each of the segments is encoded as a low bit rate layer, a high bit rate layer, and one or more intermediate bit rate layers. The bit rate of the low bit rate layer is selected such that a network streaming the segment will always be able to stream the segment encoded as the low bit rate layer. The bit rate of the high bit rate layer is selected such that the segment is able to be decoded and played back at or above a quality threshold. The bit rates of the intermediate bit rate layers are produced by applying a bit rate factor to another bit rate. | 11-12-2009 |
20090282162 | OPTIMIZED CLIENT SIDE RATE CONTROL AND INDEXED FILE LAYOUT FOR STREAMING MEDIA - An indexed file layout, comprising index information, is defined for segmented streaming of multimedia content. The index information can comprise program description information and streaming segment index information. In addition, the layout can comprise files containing streaming segments of the program, where the streaming segments are each encoded at one or more bitrates independently of other streaming segments of the program. The layout supports client switching between different bitrates at segment boundaries. Optimized client-side rate control of streaming content can be provided by defining a plurality of states, selecting available paths based on constraint conditions, and selecting a best path through the states (e.g., based on a distortion measure). In one client-side rate control solution states correspond to a specific bitrate of a specific streaming segment, and in another client-side rate control solution states correspond to a measure of client buffer fullness. | 11-12-2009 |
20120089986 | PROCESS POOL OF EMPTY APPLICATION HOSTS TO IMPROVE USER PERCEIVED LAUNCH TIME OF APPLICATIONS - Various embodiments enable a device to create a pool of at least one empty application. An empty application can be configured to contain resources that are common across one or more other applications and initialize the resources for the one or more other applications effective to reduce startup time of the other applications. In one or more embodiments, an empty application can further be populated with the one or more other applications effective to cause the one or more other applications to execute. Alternately or additionally, a device can be monitored for an idle state, and, upon determining the device is in the idle state, at least one empty application can be created. | 04-12-2012 |
20120167118 | POWER MANAGEMENT VIA COORDINATION AND SELECTIVE OPERATION OF TIMER-RELATED TASKS - Mobile computing device power consumption can be reduced by using expiration window timers, state-based timers and/or the coordination of keep-alive timers. Upon detecting a trigger event causing a mobile computing device to transition from a low-power state to an active state, the device can determine whether the trigger event occurs within the expiration window of a timer, and execute tasks associated with the trigger event and the timer. Tasks associated with state-based timers can be executed if the mobile computing device or a component thereof is in (or, alternatively, not in) a specified state. A mobile computing device can execute tasks associated with multiple keep-alive timers used for maintaining communication links between the device and cloud-based service providers in a single active state. A cloud-based keep-alive service can maintain mobile computing device-service provider communication links by sending one keep-alive communication to a mobile computing device in place of multiple communications. | 06-28-2012 |
20130124697 | OPTIMIZED CLIENT SIDE RATE CONTROL AND INDEXED FILE LAYOUT FOR STREAMING MEDIA - An indexed file layout, comprising index information, is defined for segmented streaming of multimedia content. The index information can comprise program description information and streaming segment index information. In addition, the layout can comprise files containing streaming segments of the program, where the streaming segments are each encoded at one or more bitrates independently of other streaming segments of the program. The layout supports client switching between different bitrates at segment boundaries. Optimized client-side rate control of streaming content can be provided by defining a plurality of states, selecting available paths based on constraint conditions, and selecting a best path through the states (e.g., based on a distortion measure). In one client-side rate control solution states correspond to a specific bitrate of a specific streaming segment, and in another client-side rate control solution states correspond to a measure of client buffer fullness. | 05-16-2013 |
20150078237 | POWER MANAGEMENT VIA COORDINATION AND SELECTIVE OPERATION OF TIMER-RELATED TASKS - A method of coordinating tasks of a mobile computing device may include initializing a timer associated with one or more tasks and a state condition. The state condition may depend on a device state of the mobile computing device and/or a component state of a mobile computing device component. An expiration of the timer is detected. Upon detecting the expiration, a determination is made whether the state condition is satisfied based on whether the mobile computing device is in the device state and/or the mobile computing device component is in the component state. Based at least in part on the determination that the state condition is satisfied, performance of the one or more tasks associated with the timer can be initiated. | 03-19-2015 |
Patent application number | Description | Published |
20090207675 | WAK Devices in SRAM Cells for Improving VCCMIN - A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line. | 08-20-2009 |
20100214860 | SENSE AMPLIFIER SCHEME FOR LOW VOLTAGE SRAM AND REGISTER FILES - A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output. | 08-26-2010 |
20110041109 | MEMORY BUILDING BLOCKS AND MEMORY DESIGN USING AUTOMATIC DESIGN TOOLS - The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis. | 02-17-2011 |
20110198923 | POWER MANAGEMENT MECHANISM - An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit. | 08-18-2011 |
20120075939 | MEMORY CELLS HAVING A ROW-BASED READ AND/OR WRITE SUPPORT CIRCUITRY - A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path and at least one second current path. A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode. | 03-29-2012 |
20120092072 | OFFSET COMPENSATION FOR SENSE AMPLIFIERS - A sense amplifier having compensation circuitry is described. The compensation circuitry includes at least one pair of compensation transistors. When compensation is desired, one or a combination of the bulk of the at least one pair of compensation transistors is provided with one or a combination of compensation voltages. | 04-19-2012 |
20120213013 | MEMORY BUILDING BLOCKS AND MEMORY DESIGN USING AUTOMATIC DESIGN TOOLS - The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis. | 08-23-2012 |
20120243347 | MEMORY CELLS HAVING A ROW-BASED READ AND/OR WRITE SUPPORT CIRCUITRY - A method of controlling a plurality of memory cells in a row. The method includes controlling a switching element using at least one write word line signal to raise a voltage of a node connected to the plurality of memory cells in the row when the plurality of memory cells in the row operate in a first mode. The method further includes controlling at least one transistor using the at least one write word line signal to connect the plurality of memory cells in the row to a reference voltage when the plurality of memory cells in the row operate in a second mode. | 09-27-2012 |
20120274135 | POWER MANAGEMENT MECHANISM - An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit. | 11-01-2012 |
20130044556 | SENSE AMPLIFIER SCHEME FOR LOW VOLTAGE SRAM AND REGISTER FILES - In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and a corresponding one of the pair of bit lines. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the corresponding bit line and configured to maintain a voltage level of the corresponding bit line. The noise threshold control circuit is connected to the sense amplifier output and the pair of bit lines. The noise threshold control circuit comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit. | 02-21-2013 |
20140185369 | SENSE AMPLIFIER SCHEME FOR LOW VOLTAGE SRAM AND REGISTER FILES - In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter. | 07-03-2014 |
20160118107 | METHODS OF OPERATING SENSE AMPLIFIER CIRCUITS - A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving the power supply voltage from the power supply node with an NMOS transistor, and maintaining a voltage level of the bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line. The method includes receiving the voltage level of the bit line with a noise threshold control circuit, inverting the voltage level with the noise threshold control circuit, and driving a sense amplifier output with the noise threshold control circuit. | 04-28-2016 |
20160118945 | OFFSET COMPENSATION FOR SENSE AMPLIFIERS - A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes. | 04-28-2016 |