Patent application number | Description | Published |
20080215950 | LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing - LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches. | 09-04-2008 |
20080256424 | INFORMATION BIT PUNCTURING FOR TURBO CODING WITH PARAMETER SELECTABLE RATE MATCHING TAILORED TO LOWER EB/NO WITHOUT DEGRADING BLER (BLOCK ERROR RATE) PERFORMANCE - Information bit puncturing for turbo coding with parameter selectable rate matching tailored to lower Eb/No without degrading BLER (Block Error Rate) performance. A means is presented herein by which puncturing is performed to each of three bit sequences from a turbo encoder (i.e., the systematic bits or information bits within an block to be turbo encoded, the parity bits output from a first constituent encoder, and the parity bits output from a second constituent encoder). The number of bit punctured from each of the parity bits output from the first constituent encoder and the parity bits output from the second constituent encoder need not be the same number of bits. The manner in which puncturing may be performed can be adaptive and/or changeable, in that, first puncturing parameters may be employed at a first time and second puncturing parameters may be employed at a second time, etc. | 10-16-2008 |
20080276153 | OPTIMAL PERIOD RATE MATCHING FOR TURBO CODING - Optimal period rate matching for turbo coding. A means is provided herein by which a nearly optimal (e.g., optimal for one block size and sub-optimal for others) periodic puncturing pattern that depends on a mother code. Any desired rate matching can be achieved using the means and approaches presented herein to ensure an appropriate rate of an encoded block output from a turbo encoder so that the subsequently modulated signal generated there from has the appropriate rate. In addition, some embodiments can also employ shifting for another design level available in accordance with puncturing employed to provide for periodic rate matching. Selectivity can also be employed, such that, a first periodic puncturing pattern can be applied at a first time to ensure a first rate, and a second periodic puncturing pattern can be applied at a second time to ensure a second rate. | 11-06-2008 |
20090024909 | TURBO CODING HAVING COMBINED TURBO DE-PADDING AND RATE MATCHING DE-PADDING - Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding. One or more of the 3 outputs from the turbo encoding module (e.g., systematic bits, parity 1 bits, and parity 2 bits) may then undergo dummy bit padding as well. Thereafter, these 3 streams (some or all of which may have undergone dummy bit padding) undergo sub-block interleaving. After all of these operations have taken place, a singular combined de-padding module that can be employed to perform de-padding any zero padded bits and any dummy padded bits from each of the three streams that have undergone the sub-block interleaving. | 01-22-2009 |
20090049360 | OPTIMAL CIRCULAR BUFFER RATE MATCHING FOR TURBO CODE - Optimal circular buffer rate matching for turbo code. An offset index, δ, of 3 and a skipping index, σ, of 3 is employed in accordance with circular buffer rate matching. This allows less puncturing of information bits and more puncturing of redundancy/parity bits (e.g., which can provide for a higher rate). Multiple turbo codes may be generated from a mother code such that each generated turbo code can be employed to encode information bits. For example, a first turbo coded signal can be generated using a first turbo code generated from the mother code, and a second turbo coded signal can be generated using a second turbo code generated from the mother code. Any of these turbo coded signal can be decoded using parallel decoding processing or a single turbo decoder (when each turbo coded signal undergoes processing to transform it back to the mother code format). | 02-19-2009 |
20090063940 | REGISTER EXCHANGE NETWORK FOR RADIX-4 SOVA (SOFT-OUTPUT VITERBI ALGORITHM) - A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput. For example, any or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) can be implemented in accordance with the principles of radix-4 decoding processing. | 03-05-2009 |
20090067527 | Data puncturing ensuring orthogonality within communication systems - Data puncturing ensuring orthogonality within communication systems. A means is presented herein by which puncturing is employed within communication systems to ensure orthogonality (or substantial orthogonality) of various transmissions between communication devices within communication systems. Any of a variety of types of signals can be employed herein including uncoded signals, turbo encoded signals, turbo trellis coded modulation (TTCM) encoded signals, LDPC (Low Density Parity Check) encoded signals, and a RS (Reed-Solomon) encoded signals, among just some types of signals. A first transmission can be made from a first communication device to a second communication device, and the second communication device can sometimes request a subsequent transmission (e.g., a re-transmission) from the first communication device to the second communication device. Oftentimes, different information is sent from the first communication device to the second communication device within the subsequent transmission. Herein, each of these transmissions can be ensured to be orthogonal. | 03-12-2009 |
20090119568 | Single CRC polynomial for both turbo code block CRC and transport block CRC - Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal. | 05-07-2009 |
20090129484 | Low Density Parity Check (LDPC) Encoded Higher Order Modulation - A method and apparatus is disclosed to map a sequence of data to Quadrature Amplitude Modulation (QAM) constellation symbols. The method and apparatus encodes only a portion of the sequence of data and leaves a remaining portion of the sequence of data unencoded. The encoded portion of the sequence of data and the remaining unencoded portion of the sequence of data are then mapped into modulation symbols of the QAM constellation. The encoded portion of the sequence of data selects subsets of the QAM constellation, and the remaining unencoded portion of the sequence of data determines a specific modulation symbol within each subset of the QAM constellation. | 05-21-2009 |
20090135965 | Flexible rate matching - Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission. | 05-28-2009 |
20090187804 | LDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems - LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. A variety of communication device types are also presented that may employ the error correcting coding (ECC) using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for communications using ECC. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11 | 07-23-2009 |
20090193312 | FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS - Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities. | 07-30-2009 |
20090199062 | Virtual limited buffer modification for rate matching - Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding. | 08-06-2009 |
20090217142 | Rate control adaptable communications - Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc. | 08-27-2009 |
20090282315 | LDPC coding systems for 60 GHz millimeter wave based physical layer extension - LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.). | 11-12-2009 |
20090285320 | Parallel concatenated code with soft-in soft-out interactive turbo decoder - A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel. | 11-19-2009 |
20090327847 | LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices - LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”). | 12-31-2009 |
20100023838 | Quasi-cyclic LDPC (Low Density Parity Check) code construction - Quasi-cyclic LDPC (Low Density Parity Check) code construction is presented that ensures no four cycles therein (e.g., in the bipartite graphs corresponding to the LDPC codes). Each LDPC code has a corresponding LDPC matrix that is composed of square sub-matrices, and based on the size of the sub-matrices of a particular LDPC matrix, then sub-matrix-based cyclic shifting is performed as not only a function of sub-matrix size, but also the row and column indices, to generate CSI (Cyclic Shifted Identity) sub-matrices. When the sub-matrix size is prime (e.g., each sub-matrix being size q×q, where q is a prime number), then it is guaranteed that no four cycles will exist in the resulting bipartite graph corresponding to the LDPC code of that LDPC matrix. When q is a non-prime number, an avoidance set can be used and/or one or more sub-matrices can be made to be an all zero-valued sub-matrix. | 01-28-2010 |
20100031125 | Tail-biting turbo coding to accommodate any information and/or interleaver block size - Tail-biting turbo coding to accommodate any information and/or interleaver block size. A means is presented by which the beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder. | 02-04-2010 |
20100077277 | Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes - Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit. | 03-25-2010 |
20100077282 | True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations - True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis. | 03-25-2010 |
20100083071 | LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing - LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing. | 04-01-2010 |
20100111145 | BASEBAND UNIT HAVING BIT REPETITIVE ENCODED/DECODING - A baseband unit includes an input/output interface and a processing module. The input/output interface module receives a data word of outbound data and outputs a plurality of outbound symbols. The processing module converts the data word into a bit repetitive data word; encodes the bit repetitive data word to produce an encoded data block; and converts the encoded data block into the plurality of outbound symbols. | 05-06-2010 |
20100115371 | Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding - Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows. | 05-06-2010 |
20100115372 | Header encoding for single carrier (SC) and/or orthogonal frequency division multiplexing (OFDM) using shortening, puncturing, and/or repetition - Header encoding for SC and/or OFDM signaling using shortening, puncturing, and/or repetition in accordance with encoding header information within a frame to be transmitted via a communication channel employs different respective puncturing patterns as applied to different portions thereof. For example, a first puncturing pattern is applied to a first portion of the frame, and a second puncturing pattern is applied to a second portion of the frame (the second portion may be a repeated version of the first portion). Shortening (e.g., by padding 0-valued bits thereto) may be made to header information bits before they undergo encoding (e.g., in an LDPC encoder). One or both of the information bits and parity/redundancy bits output from the encoder undergo selective puncturing. Moreover, one or both of the information bits and parity/redundancy bits output from the encoder may be repeated/spread before undergoing selective puncturing to generate a header. | 05-06-2010 |
20100115375 | Header encoding/decoding - In a communication device that is operative to perform decoding, a log-likelihood ratio (LLR) circuitry operates to calculate LLRs corresponding to every bit location within a received bit sequence. This received bit sequence may include a header and a data portion (both of which may be included within a frame that also includes a preamble). The header is composed of information bits, a duplicate of those information bits (such as may be generated in accordance with repetition encoding), and redundancy bits. The header includes information corresponding to frame or data including frame length, a code type by which the data are encoded, a code rate by which the data are encoded, and a modulation by which symbols of the data are modulated. Once the header has been decoded, then the data corresponding thereto is decoded by a block decoder circuitry to make estimates of that data. | 05-06-2010 |
20100122140 | Algebraic construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices - Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code. | 05-13-2010 |
20100138721 | Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder - Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved. | 06-03-2010 |
20100220804 | ASYMMETRICAL MIMO WIRELESS COMMUNICATIONS - A method for asymmetrical MIMO wireless communication begins by determining a number of transmission antennas for the asymmetrical MIMO wireless communication. The method continues by determining a number of reception antennas for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas exceeds the number of reception antennas, using spatial time block coding for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas does not exceed the number of reception antennas, using spatial multiplexing for the asymmetrical MIMO wireless communication. | 09-02-2010 |
20100241923 | Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding - Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding. An LDPC code is concatenated with a RS code or a binary product code (e.g., using row and column encoding of matrix formatted bits) thereby generating coded bits for use in generating a signal that is suitable to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. and various implementations of cyclic redundancy check (CRC) may accompany the product coding and/or additional ECC/FEC employed. The redundancy of such coded signals as generated using the principles herein are in the range of approximately 20% thereby providing a significant amount of redundancy and a high coding gain. Soft decision decoding may be performed on such coded signal generated herein. | 09-23-2010 |
20100251064 | LDPC codes robust to non-stationary narrowband ingress noise - LDPC codes robust to non-stationary narrowband ingress noise. Particularly designed LDPC codes are adapted to address deleterious noise-effects incurred within LDPC coded signals that propagate via a communication channel (such as from a transmitting communication device to a receiving communication device). Such LDPC matrices employed for encoding and/or decoding such LDPC coded signals are composed of sub-matrices (e.g., all-zero values sub-matrices and/or CSI (Cyclic Shifted Identity) sub-matrices). The sub-matrices are generally uniform in size and square in shape. Based on certain operational conditions, such as communication channel noise, various operations within a communication device are adaptively modified (e.g., signaling, modulation, demodulation, symbol mapping, metric generation, decoding, etc.). Various types of signaling may be employed for such LDPC coded signals including orthogonal frequency division multiplexing (OFDM) signaling, which may include employing symbols of different size therein (e.g., symbols with x and y bits, respectively, with x and y being integers). | 09-30-2010 |
20100281330 | Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code - Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform decoding of more than one type of LDPC coded signals. A common basis of decoder hardware (e.g., decoder circuitry) is employed when decoding all of the various types of LDPC coded signals that such a communication device can decode. However, all of the decoder hardware is only employed to decode signals corresponding to the lowest code rate LDPC code supported by the communication device. A first subset of the decoder hardware is employed to decode signals corresponding to the second to lowest code rate LDPC code, a second subset (being less than the first subset) is employed to decode signals corresponding to the third to lowest code rate LDPC code, etc. | 11-04-2010 |
20100281335 | Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code - Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system. | 11-04-2010 |
20110022925 | Turbo Coding for Upstream and Downstream Transmission in Cable Systems - A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data. | 01-27-2011 |
20110047436 | Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors - Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories). | 02-24-2011 |
20110055663 | Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves - Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function | 03-03-2011 |
20110072336 | LDPC (Low Density Parity Check) coded modulation symbol decoding - LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics. | 03-24-2011 |
20110078527 | ENCODER/DECODER WITH UNFOLDING ERROR CORRECTION - A decoder includes an interface and a processing module. The interface receives first data, redundant data of the first data, second data, redundant data of the second data, and combined redundant data. The processing module decodes the first data based on the redundant data of the first data, decodes the second data based on the redundant data, of the second data and verifies the decoding of the first and second data. When the first data is decoded successfully and the second data is not, the processing module encodes the first data to produce a second redundant data of the first data, determines a second redundant data of the second data based on the combined redundant data and the second redundant data of the first data, decodes the second data based on the second redundant data of the second data, and verifies the decoding of the second data. | 03-31-2011 |
20110107175 | LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices - LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”). | 05-05-2011 |
20110110353 | Multiple input multiple output wireless local area network communications - A wireless local area network (WLAN) transmitter includes a MAC module, a PLCP module, and a PMD module. The Medium Access Control (MAC) module is operably coupled to convert a MAC Service Data Unit (MSDU) into a MAC Protocol Data Unit (MPDU) in accordance with a WLAN protocol. The Physical Layer Convergence Procedure (PLCP) Module is operably coupled to convert the MPDU into a PLCP Protocol Data Unit (PPDU) in accordance with the WLAN protocol. The Physical Medium Dependent (PMD) module is operably coupled to convert the PPDU into a plurality of radio frequency (RF) signals in accordance with one of a plurality of operating modes of the WLAN protocol, wherein the plurality of operating modes includes multiple input and multiple output combinations. | 05-12-2011 |
20110258518 | Variable modulation with LDPC (Low Density Parity Check) coding - Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis. | 10-20-2011 |
20120014364 | WLAN TRANSMITTER HAVING HIGH DATA THROUGHPUT - A wireless local area network (WLAN) transmitter includes a baseband processing module and a plurality of radio frequency (RF) transmitters. The processing module selects one of a plurality of modes of operation based on a mode selection signal. The processing module determines a number of transmit streams based on the mode selection signal. The processing of the data further continues by converting encoded data into streams of symbols in accordance with the number of transmit streams and the mode selection signal. A number of the plurality of RF transmitters are enabled based on the mode selection signal to convert a corresponding one of the streams of symbols into a corresponding RF signal such that a corresponding number of RF signals is produced. | 01-19-2012 |
20120063537 | Turbo coding having combined turbo de-padding and rate matching de-padding - Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding. One or more of the 3 outputs from the turbo encoding module (e.g., systematic bits, parity 1 bits, and parity 2 bits) may then undergo dummy bit padding as well. Thereafter, these 3 streams (some or all of which may have undergone dummy bit padding) undergo sub-block interleaving. After all of these operations have taken place, a singular combined de-padding module that can be employed to perform de-padding any zero padded bits and any dummy padded bits from each of the three streams that have undergone the sub-block interleaving. | 03-15-2012 |
20120106640 | Decoding side intra-prediction derivation for video coding - Decoding side intra-prediction derivation for video coding. Just decoded pixels within a given picture (image) (e.g., such as a given picture (image) within video data) are employed for decoding other pixels within that very same picture (image) using prediction vectors extending from the just decoded pixels to the pixels currently being decoded. In one instance, this intra-prediction operation in accordance with video or image processing can also operate using relatively limited information provided from the device that provides or transmits the video data to the device in which it undergoes processing. Coarse and/or refined direction information corresponding to these prediction vectors may be provided from the device that provides or transmits the video data to the device in which it undergoes processing. | 05-03-2012 |
20120177100 | DATA PUNCTURING ENSURING ORTHOGONALITY WITHIN COMMUNICATION SYSTEMS - Data puncturing ensuring orthogonality within communication systems. Puncturing is employed within communication systems to ensure orthogonality (or substantial orthogonality) of various transmissions between communication devices within communication systems. Any of a variety of types of signals can be employed herein including uncoded signals, turbo encoded signals, turbo trellis coded modulation (TTCM) encoded signals, LDPC (Low Density Parity Check) encoded signals, and RS (Reed-Solomon) encoded signals, among just some types of signals. A first transmission can be made from a first communication device to a second communication device, and the second communication device can sometimes request a subsequent transmission (e.g., a re-transmission) from the first communication device to the second communication device. Oftentimes, different information is sent from the first communication device to the second communication device within the subsequent transmission. Herein, each of these transmissions can be ensured to be orthogonal. | 07-12-2012 |
20120185745 | MULTI-CSI (Cyclic Shifted Identity) SUB-MATRIX BASED LDPC (Low Density Parity Check) CODES - Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit. | 07-19-2012 |
20120192029 | LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices - LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”). | 07-26-2012 |
20120195398 | Virtual limited buffer modification for rate matching - Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding. | 08-02-2012 |
20120237032 | TWO-STAGE BLOCK SYNCHRONIZATION AND SCRAMBLING - A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronization | 09-20-2012 |
20120266042 | HEADER ENCODING/DECODING - In a communication device that is operative to perform decoding, a log-likelihood ratio (LLR) circuitry operates to calculate LLRs corresponding to every bit location within a received bit sequence. This received bit sequence may include a header and a data portion (both of which may be included within a frame that also includes a preamble). The header is composed of information bits, a duplicate of those information bits (such as may be generated in accordance with repetition encoding), and redundancy bits. The header includes information corresponding to frame or data including frame length, a code type by which the data are encoded, a code rate by which the data are encoded, and a modulation by which symbols of the data are modulated. Once the header has been decoded, then the data corresponding thereto is decoded by a block decoder circuitry to make estimates of that data. | 10-18-2012 |
20120272118 | Variable modulation with LDPC (Low Density Parity Check) coding - Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. Variable modulation encoding of LDPC coded symbols is presented. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis. | 10-25-2012 |
20120284583 | OVERLAPPING SUB-MATRIX BASED LDPC (LOW DENSITY PARITY CHECK) DECODER - Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved. | 11-08-2012 |
20120287973 | Flexible rate matching - Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission. | 11-15-2012 |
20120288024 | ASYMMETRICAL MIMO WIRELESS COMMUNICATIONS - A method for asymmetrical MIMO wireless communication begins by determining a number of transmission antennas for the asymmetrical MIMO wireless communication. The method continues by determining a number of reception antennas for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas exceeds the number of reception antennas, using spatial time block coding for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas does not exceed the number of reception antennas, using spatial multiplexing for the asymmetrical MIMO wireless communication. | 11-15-2012 |
20120300861 | Forward error correction (FEC) m-bit symbol modulation - Forward error correction (FEC) m-bit symbol modulation. Any desired FEC, error correction code (ECC), and/or combination thereof generates coded bits for combination with either uncoded bits, separately generated coded bits, and/or combination thereof to generate a number of symbols that undergo mapping to a constellation whose respective constellation points have a mapping characterized by a maximum minimum intra-Euclidean distance between the respective constellation points thereby generating a sequence of discrete-valued modulation symbols. The sequence of discrete-valued modulation symbols may then undergo modulation of any of a number of different operations (e.g., digital to analog conversion [e.g., digital to analog converter (DAC)], scaling, frequency shifting, filtering, etc.) to generate a continuous time signal for transmission via a communication channel. Such a device operative to perform including such functionality, circuitry, capability, etc., may be implemented to be operative within any desired communication system (e.g., satellite, wireless, wired, fiber-optic, and/or combination thereof, etc.). | 11-29-2012 |
20120311400 | Single CRC polynomial for both turbo code block CRC and transport block CRC - Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal. | 12-06-2012 |
20120314711 | Header encoding for single carrier (SC) and/or orthogonal frequency division multiplexing (OFDM) using shortening, puncturing, and/or repetition - Header encoding for SC and/or OFDM signaling using shortening, puncturing, and/or repetition in accordance with encoding header information within a frame to be transmitted via a communication channel employs different respective puncturing patterns as applied to different portions thereof. For example, a first puncturing pattern is applied to a first portion of the frame, and a second puncturing pattern is applied to a second portion of the frame (the second portion may be a repeated version of the first portion). Shortening (e.g., by padding 0-valued bits thereto) may be made to header information bits before they undergo encoding (e.g., in an LDPC encoder). One or both of the information bits and parity/redundancy bits output from the encoder undergo selective puncturing. Moreover, one or both of the information bits and parity/redundancy bits output from the encoder may be repeated/spread before undergoing selective puncturing to generate a header. | 12-13-2012 |
20130010897 | Low Density Parity Check (LDPC) Encoded Higher Order Modulation - A method and apparatus is disclosed to map a sequence of data to Quadrature Amplitude Modulation (QAM) constellation symbols. The method and apparatus encodes only a portion of the sequence of data and leaves a remaining portion of the sequence of data unencoded. The encoded portion of the sequence of data and the remaining unencoded portion of the sequence of data are then mapped into modulation symbols of the QAM constellation. The encoded portion of the sequence of data selects subsets of the QAM constellation, and the remaining unencoded portion of the sequence of data determines a specific modulation symbol within each subset of the QAM constellation. | 01-10-2013 |
20130034148 | Unified binarization for CABAC/CAVLC entropy coding - Unified binarization for CABAC/CAVLC entropy coding. Scalable entropy coding is implemented in accordance with any desired degree of complexity (e.g., entropy encoding and/or decoding). For example, appropriately implemented context-adaptive variable-length coding (CAVLC) and context-adaptive binary arithmetic coding (CABAC) allow for selective entropy coding in accordance with a number of different degrees of complexity. A given device may operate in accordance with a first level complexity a first time, a second level complexity of the second time, and so on. Appropriate coordination and signaling between an encoder/transmitter device and a decoder/receiver device allows for appropriate coordination along a desired degree of complexity. For example, a variable length binarization module and an arithmetic encoding module may be implemented within an encoder/transmitter device and a corresponding arithmetic decoding module and a variable length bin decoding module may be implemented within a decoder/receiver device allowing for entropy coding along various degrees of complexity. | 02-07-2013 |
20130064323 | Turbo Coding for Upstream and Downstream Transmission in Cable Systems - A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data. | 03-14-2013 |
20130077697 | Adaptive loop filtering in accordance with video coding - Adaptive loop filtering in accordance with video coding. An adaptive loop filter (ALF) and/or other in-loop filters (e.g., sample adaptive offset (SAO) filter, etc.) may be implemented within various video coding architectures (e.g., encoding and/or decoding architectures) to perform both offset and scaling processing, only scaling processing, and/or only offset processing. Operation of such an ALF may be selective in accordance with any of multiple respective operational modes at any given time and may be adaptive based upon various consideration(s) (e.g., desired complexity level, processing type, local and/or remote operational conditions, etc.). For example, an ALF may be applied to a decoded picture before it is stored in a picture buffer (or digital teacher buffer (DPB)). An ALF can provide for coding noise reduction of a decoded picture, and the filtering operations performed thereby may be selective (e.g., on a slice by slice basis, block by block basis, etc.). | 03-28-2013 |
20130083841 | Video coding infrastructure using adaptive prediction complexity reduction - Video coding infrastructure using adaptive prediction complexity reduction. One or more subsets associated with one or more frames or pictures of the video signal may be adaptively selected and used for motion vector calculation (e.g., such as in accordance with inter-prediction). For example, a picture or frame of the video signal may be partitioned into a number of respective regions. Any one or more, but typically fewer than all, of the respective regions may be appropriately selected, and stored, based on any one or more considerations for use in motion vector calculation (e.g., inter-prediction). A sub-sampled or down-sampled picture or frame [or alternatively, a sub-sampled or down-sampled version of one or more respective regions of a picture or frame] (e.g., the sub-sampling or down-sampling ratio which may be adaptively determined based on any one or more considerations) may be stored for use in motion vector calculation (e.g., inter-prediction). | 04-04-2013 |
20130083852 | Two-dimensional motion compensation filter operation and processing - Two-dimensional motion compensation filter operation and processing. A video bitstream or signal corresponding thereto undergoes motion compensation operations simultaneously or in parallel with respect to at least two respective dimensions (e.g., at least horizontal and vertical) in accordance with generating coefficient values employed for generating a decoded and/or output video signal. The simultaneous and in parallel operations made with respect to more than one dimension associated with the video bitstream or signal may employ a two-dimensional discrete cosine transform (2-D DCT) implemented to operate on more than one dimension simultaneously. Same or different respective fractional-pel distances may be employed with respect to multiple respective dimensions (e.g., common/same fractional-pel distance for all of the multiple respective dimensions, or different respective fractional-pel distances with respect to each of the multiple respective dimensions [such as a first fractional-pel distance for a first dimension, a second fractional-pel distance for a second dimension, etc.]). | 04-04-2013 |
20130166987 | LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices - LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”). | 06-27-2013 |
20130179756 | Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding - Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows. | 07-11-2013 |
20130208810 | Frequency domain sample adaptive offset (SAO) - Frequency domain sample adaptive offset (SAO). Video processing of a first signal operates to generate a second video signal such that at least one characteristic of a first portion of video information of the first video signal is replicated in generating a second portion of video information, such that the first portion of video information and the second portion of video information undergo combination to generate the second video signal. Such use of the first video signal may involve replication and scaling of the first video information to generate the second portion of video information. One possible characteristic of the first portion of video information may correspond to an energy profile as a function of frequency. One or more portions of the first video signal may be employed to generate different respective portions of the second signal. Such video processing operations may be performed on a block by block basis. | 08-15-2013 |
20130223561 | LDPC coding systems for 60 GHz millimeter wave based physical layer extension - LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.). | 08-29-2013 |
20130227373 | Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC) - Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC). Adaptive processing is performed on a signal based on one or more effects which may deleteriously modify a signal. For example, based on a modification of a signal to noise ratio (SNR) associated with one or more impulse or burst noise events, which may be estimated, different respective processing may be performed selectively to differently affected bits associated with the signal. For example, two respective SNRs may be employed: a first SNR for one or more first bits, and a second SNR for one or more second bits. For example, as an impulse or burst noise event may affect different respective bits of a codeword differently, and adaptive processing may be made such that different respective bits of the codeword may be handled differently. | 08-29-2013 |
20130238953 | Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code - Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system. | 09-12-2013 |
20130332792 | Symbol mapping for binary coding - The present disclosure presents symbol mapping for any desired error correction code (ECC) and/or uncoded modulation. A cross-shaped constellation is employed to perform symbol mapping. The cross-shaped constellation is generated from a rectangle-shaped constellation. Considering the rectangle-shaped constellation and its left hand side, a first constellation point subset located along that left hand side are moved to be along a top of the cross-shaped constellation while a second constellation point subset located along that left hand side are moved to be along a bottom of the cross-shaped constellation. For example, considering an embodiment having four constellation point subsets along the left hand side of the rectangle-shaped constellation, two of those subsets are moved to be along the top of the cross-shaped constellation while two other subsets of the constellation points along the left hand side are moved to be along the bottom of the cross-shaped constellation. | 12-12-2013 |
20140019830 | Joint application-layer forward error/erasure correction (FEC) and video coding - Layered and scalable coding scheme is applied to one or more communication pathways between a transmitter and one or more receivers. Forward error/erasure correction (FEC) is applied for application layer erasure recovery. Additional FEC may also be employed at the physical layer (PHY) layer or channel coding layer for additional error correction capability and to provide joint application and PHY layer FEC coding. Source information (e.g., data, media such as image, video or audio, etc., or any other type of information) is encoded using two or more layers. These layers may include a base layer and one or more enhancement layers that, when combined with the base layer, modify the quality of the base layer. In a packet-based application, transmission of redundancy packets may be separately time-limited in the two or more layers. Also, adaptation (of signaling, FEC, etc.) may be made based on operating condition changes. | 01-16-2014 |
20140153673 | Adaptive decoding based on signal to noise ratio (SNR) - A communication device is configured adaptively to process a receive signal based on noise that may have adversely affected the signal during transition via communication channel. The device may be configured to identify those portions of the signal of the signal that are noise-affected (e.g., noise-affected sub-carriers of an orthogonal frequency division multiplexing (OFDM) signal), or the device may receive information that identifies those portions of the signal that are noise-affected from one or more other devices. The device may be configured to perform the modulation processing of the received signal to generate log-likelihood ratios (LLRs) for use in decoding the signal. Those LLRs associated with noise-affected portions of the signal are handled differently than LLRs associated with portions of the signal that are not noise-affected. The LLRs may be scaled based on signal to noise ratio(s) (SNR(s)) associated with the signal (e.g., based on background noise, burst noise, etc.). | 06-05-2014 |
20140169424 | Orthogonal frequency division multiplexing (OFDM) interleaving - A communication device is configured to perform interleaving of a modulation symbol sequence to generate an OFDM symbol. Some modulation symbols within the modulation symbol sequence that are separated by an interleaver depth may be transmitted via adjacently located sub-carriers, while other modulation symbols within the modulation sequence that are separated by more than the interleaver depth may also be transmitted via adjacently located sub-carriers. First adjacently located sub-carriers transmit first and second modulation symbols that are separated by the interleaver depth within the modulation sequence while second adjacently located sub-carriers transmit third and fourth modulation symbol that are separated by more than the interleaver depth within the modulation sequence. A communication device may be configured to adapt and switch between different operational parameters used for interleaving and/or deinterleaving at different times based on any desired considerations. | 06-19-2014 |
20140169425 | Orthogonal frequency division multiplexing (OFDM) with variable bit loading and time and/or frequency interleaving - A communication device is configured to perform processing of one or more bits to generate a modulation symbol sequence based on one or more profiles that specify variable bit loading of bits per symbol over at least some of the modulation symbols of the modulation symbol sequence. The communication device is also configured to perform interleaving of the modulation symbol sequence to generate OFDM symbol(s). Some modulation symbols within the modulation symbol sequence that are separated by an interleaver depth may be transmitted via adjacently located sub-carriers, while other modulation symbols within the modulation sequence that are separated by more than the interleaver depth may also be transmitted via adjacently located sub-carriers. A communication device may be configured to adapt and switch between different operational parameters used for bit loading, interleaving and/or deinterleaving at different times based on any desired considerations. | 06-19-2014 |
20140201588 | Low density parity check (LDPC) coding in communication systems - A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above). | 07-17-2014 |
20140201592 | Very short size LDPC coding for physical and/or control channel signaling - A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above). | 07-17-2014 |
20140365844 | Cyclic redundancy check (CRC) and forward error correction (FEC) for ranging within communication systems - A communication device (device) includes a processor configured to generate an initial ranging LDPC coded signal based on a first LDPC code and then transmits the initial ranging LDPC coded signal to another device (e.g., via a communication interface) for use by the other device for coarse power and timing adjustment. Then, the processor processes a received transmit opportunity signal to identify a transmit opportunity time period. The processor then generates a fine ranging LDPC coded signal based on a second LDPC code and transmits the fine ranging LDPC coded signal to the other device during the transit opportunity time period for use by the other device for fine power and timing adjustment. In some instances, the processor may be configured to generate one or more wideband probe signals for transmission to the other device in conjunction with or instead of the fine ranging LDPC coded signals. | 12-11-2014 |
20140365845 | Combining CRC and FEC on a variable number of NCPs - A communication device is configured to communicate coded information to other communication device(s). The communication device uses NCPs to indicate locations of codewords within signal(s) transmitted to the other communication device(s). The communication device is configured to encode NCP(s) using an FEC code to generate coded NCP(s) and also to encode the NCP(s) using a cyclic redundancy check (CRC) code to generate NCP CRC bits. The communication device is also configured to encode the NCP CRC bits using the FEC code to generate coded NCP CRC bits. The communication device is then configured to generate OFDM or OFDMA symbol(s) include the coded NCP(s) and the coded NCP CRC bits to indicate beginnings of codeword(s) within at least one of the OFDM symbol(s) and/or additional OFDM symbol(s). The communication device is also configured to transmit the OFDM or OFDMA symbols to another communication device via a communication interface of the communication device. | 12-11-2014 |
20150046778 | OPTIMAL PERIOD RATE MATCHING FOR TURBO CODING - Optimal period rate matching for turbo coding. A means is provided herein by which a nearly optimal (e.g., optimal for one block size and sub-optimal for others) periodic puncturing pattern that depends on a mother code. Any desired rate matching can be achieved using the means and approaches presented herein to ensure an appropriate rate of an encoded block output from a turbo encoder so that the subsequently modulated signal generated there from has the appropriate rate. In addition, some embodiments can also employ shifting for another design level available in accordance with puncturing employed to provide for periodic rate matching. Selectivity can also be employed, such that, a first periodic puncturing pattern can be applied at a first time to ensure a first rate, and a second periodic puncturing pattern can be applied at a second time to ensure a second rate. | 02-12-2015 |
20150063484 | Frequency interleave within communication systems - A communication device includes a communication interface and a processor. In one example, the processor generates an orthogonal frequency division multiplexing (OFDM) symbol that includes information modulated within sub-carriers and then interleaves the sub-carriers of the OFDM symbol to generate an interleaved OFDM symbol. This interleaving of the sub-carriers operates to write the plurality of sub-carriers to rows of a two dimensional (2D) array and read the plurality of sub-carriers from columns of the 2D array. This interleaving also operates to read a column of the columns using a bit-reversed address of the column when the bit-reversed address is less than a number of the columns and using the address of the column when the bit-reversed address is greater than or equal to the number of the columns. The processor transmits, via the communication interface, the interleaved OFDM symbol to another communication device. | 03-05-2015 |