Patent application number | Description | Published |
20080240170 | Systems and methods for digital delayed array transmitter architecture with beam steering capability for high data rate - Embodiments include systems and methods for fine control of beam steering for wide band wireless applications using a phased array of antenna elements. In one embodiment, a digitally controlled delay line delays the signal output from a modulator in each branch of multiple branches feeding multiple antennas in an array. An output of the digital delay line is input to a digital to analog converter. A second digital delay line also delays the signal within the digital to analog converter. The manner of implementation of the delays enables accurate production of a steered beam at a high data rate. | 10-02-2008 |
20080284530 | PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT - A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs. | 11-20-2008 |
20090002086 | Film bulk acoustic resonator calibration - Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant frequency is determined using a fractional-N synthesizer and comparing phase/frequency of an output signal from the fractional-N synthesizer to a reference. The reference may be derived from a low frequency crystal oscillator, an external signal source, or a communications signal. | 01-01-2009 |
20090034603 | SUBRANGING FOR A PULSE POSITION AND PULSE WIDTH MODULATION BASED TRANSMITTER - Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier. | 02-05-2009 |
20090036064 | DIGITAL INTEGRATED TRANSMITTER BASED ON FOUR-PATH PHASE MODULATION - Briefly, in accordance with one or more embodiments, a transmitter comprises four phase modulators to provide four path phase modulation. The phase modulators modulate local oscillator signals with control signals derived from quadrature baseband data to be transmitted to result in four phase modulated signals. The four phase modulated signals may be combined to provide a pulse position and pulse width modulated signal that may have a constant, or nearly constant, amplitude. The frequency spectrum of the control signals have narrower bandwidths and greater out of band attenuation resulting in higher suppression of out of channel and out of band noise. | 02-05-2009 |
20090041108 | CASCADED PHASE PULSE POSITION AND PULSE WIDTH MODULATION BASED DIGITAL TRANSMITTER - Briefly, in accordance with one or more embodiments, a digital transmitter may comprise two or more phase modulators in a cascaded arrangement. The phase modulators may modulate a local oscillator signal using control signals derived from the quadrature baseband data to be transmitted. A closed loop power control feedback arrangement may be used to compare the output power of the transmitter with a desired output signal, and make corrections to the output signal by modifying at least one of the control signals provided to the cascaded phase modulators. | 02-12-2009 |
20100033257 | PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT - A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs. | 02-11-2010 |
20100164774 | TIME-INTERLEAVED DELTA-SIGMA MODULATOR - Embodiments of the present disclosure provide methods, systems, and apparatuses related to a time-interleaved delta-sigma modulator are described. Other embodiments may be described and claimed. | 07-01-2010 |
20110267120 | DELAY LINE CALIBRATION - In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation. | 11-03-2011 |
20120062331 | SYSTEM, METHOD AND APPARATUS FOR AN OPEN LOOP CALIBRATED PHASE WRAPPING PHASE MODULATOR FOR WIDEBAND RF OUTPHASING/POLAR TRANSMITTERS - A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer. | 03-15-2012 |
20120142304 | Power Amplifiers for Wireless Systems - A wireless transceiver may include a power amplifier that uses an envelope tracker. The envelope tracker may include stacked buck switching supply modulators, each having two different supply voltages. In one embodiment, the two different supply voltages are higher and lower supply voltages, which relaxes the voltage head room on the switching regulator and allows the use of thin gate fast transistors in some embodiments. | 06-07-2012 |
20120161831 | DIGITAL PHASE LOCK LOOP - An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed. | 06-28-2012 |
20130271305 | RESISTOR-BASED SIGMA-DELTA DAC - An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal. | 10-17-2013 |
20140333358 | RE-CIRCULATING TIME-TO-DIGITAL CONVERTER (TDC) - A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal. | 11-13-2014 |
20150036767 | DIGITALLY CONTROLLED EDGE INTERPOLLATOR (DCEI) FOR DIGITAL TO TIME CONVERTERS (DTC) - A Digital-to-Time (DTC) for a Digital Polar Transmitter (DPT) comprises a coarse delay/phase segment and a fine delay/phase segment. The coarse delay/phase segment generates an even delay/phase signal and an odd delay/phase signal. The fine/phase delay segment receives the even coarse phase signal and the odd coarse phase signal, and is responsive to a fine delay/phase control signal to generate a fine delay/phase output signal that is an interpolation of the even delay/phase signal and the odd delay/phase signal. In one exemplary embodiment, the fine delay/phase control signal comprises a binary signal having 2 | 02-05-2015 |
20150049840 | DIGITAL-TO-TIME CONVERTER AND METHODS FOR GENERATING PHASE-MODULATED SIGNALS - Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/−1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals. | 02-19-2015 |
20150074156 | METHODS AND SYSTEMS TO COMPENSATE FOR NON-LINEARITY OF A STOCHASTIC SYSTEM - Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop. | 03-12-2015 |