Patent application number | Description | Published |
20090007031 | METHOD AND SYSTEM FOR IMPLEMENTING CACHED PARAMETERIZED CELLS - Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design. | 01-01-2009 |
20100115207 | METHOD AND SYSTEM FOR IMPLEMENTING MULTIUSER CACHED PARAMETERIZED CELLS - An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data. | 05-06-2010 |
20100306729 | SYSTEM AND METHOD FOR GENERATING FLAT LAYOUT - The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout. | 12-02-2010 |
20110061034 | METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS - Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design. | 03-10-2011 |
20110161899 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED-SIGNAL VERIFICATION AND LOW POWER SIMULATION - Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic. | 06-30-2011 |
20110161900 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-POWER DOMAIN DIGITAL / MIXED SIGNAL VERIFICATION AND LOW POWER SIMULATION - Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic. | 06-30-2011 |
20120047434 | METHOD TO PREVIEW AN UNDO/REDO LIST - A method identifying an element in a document corresponding to an edit selected from a list of available edits to distinguish the selected edit from the other edits in the list. The identifying may reflect the type of edit, or otherwise demonstrate the change to the element effectuated by the edit. Multiple edits may be selected and temporarily highlighted or otherwise identified in chronological order to demonstrate the effect of multiple edits on the elements of the document. | 02-23-2012 |
20130097572 | METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS - Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design. | 04-18-2013 |
20130246900 | SYNCHRONIZED THREE-DIMENSIONAL DISPLAY OF CONNECTED DOCUMENTS - A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. Upon selection of any active element or predefined net list, the elements physically or logically connected to the selected element or net list may be highlighted in the active documents, listed, or otherwise identified. An inter-document net list may identify connections between existing net lists in multiple documents. | 09-19-2013 |
20130290834 | SYNCHRONIZED THREE-DIMENSIONAL DISPLAY OF CONNECTED DOCUMENTS - A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. According to an embodiment, the layouts or documents may be connected via an interposer. | 10-31-2013 |
20140123094 | PRODUCING A NET TOPOLGY PATTERN AS A CONSTRAINT UPON ROUTING OF SIGNAL PATHS IN AN INTEGRATED CIRCUIT DESIGN - A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure. | 05-01-2014 |