Patent application number | Description | Published |
20130339587 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible. | 12-19-2013 |
20140047166 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140281069 | MULTI ROOT SHARED PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) END POINT - A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table. | 09-18-2014 |
20140281142 | Storage System Employing MRAM and Redundant Array of Solid State Disk - A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided. | 09-18-2014 |
20140281825 | Method for Reducing Effective Raw Bit Error Rate in Multi-Level Cell NAND Flash Memory - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 09-18-2014 |
20150067449 | FLASH SUBSYSTEM ORGANIZED INTO PAIRS OF UPPER AND LOWER PAGE LOCATIONS - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 03-05-2015 |
20150220435 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible. | 08-06-2015 |
Patent application number | Description | Published |
20150087641 | HETEROCYCLIC CGRP RECEPTOR ANTAGONISTS - The present invention is directed to heterocyclic compounds which are antagonists of CGRP receptors and useful in the treatment or prevention of diseases in which CGRP is involved, such as migraine. The invention is also directed to pharmaceutical compositions comprising these compounds and the use of these compounds and compositions in the prevention or treatment of such diseases in which CGRP is involved. | 03-26-2015 |
20150099771 | PYRIDINE CGRP RECEPTOR ANTAGONISTS - The present invention is directed to pyridine derivatives which are antagonists of CGRP receptors and useful in the treatment or prevention of diseases in which CGRP is involved, such as migraine. The invention is also directed to pharmaceutical compositions comprising these compounds and the use of these compounds and compositions in the prevention or treatment of such diseases in which CGRP is involved. | 04-09-2015 |
20150111914 | SPIROLACTAM CGRP RECEPTOR ANTAGONISTS - The present invention is directed to spirolactam analogues which are antagonists of CGRP receptors and useful in the treatment or prevention of diseases in which CGRP is involved, such as migraine. The invention is also directed to pharmaceutical compositions comprising these compounds and the use of these compounds and compositions in the prevention or treatment of such diseases in which CGRP is involved. | 04-23-2015 |
20150203496 | ALIPHATIC SPIROLACTAM CGRP RECEPTOR ANTAGONISTS - The present invention is directed to aliphatic spirolactam derivatives which are antagonists of CGRP receptors and useful in the treatment or prevention of diseases in which CGRP is involved, such as migraine. The invention is also directed to pharmaceutical\compositions comprising these compounds and the use of these compounds and compositions in the prevention or treatment of such diseases in which CGRP is involved. | 07-23-2015 |