Patent application number | Description | Published |
20100281344 | SOFT REED-SOLOMON DECODER BASED ON ERROR-AND-ERASURE REED-SOLOMON DECODER - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may (i) generate a decoded codeword by decoding a first codeword a plurality of times based on a respective plurality of erasure location vectors and (ii) assert a fail signal upon each failure of the decoding of the first codeword, the decoding comprising an error-and-erasure Reed-Solomon decoding. The second circuit may (i) generate a count of the assertions of the fail signal and (ii) generate the erasure location vectors based on (a) the count and (b) a plurality of reliability items corresponding to the first codeword. | 11-04-2010 |
20100299580 | BCH OR REED-SOLOMON DECODER WITH SYNDROME MODIFICATION - An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to calculate a plurality of preliminary syndromes from a plurality of received symbols. The second circuit may be configured to calculate a plurality of normal syndromes by modifying the preliminary syndromes using at most two Galois Field multiplications. The third circuit is generally configured to calculate an errata polynomial based on the normal syndromes. | 11-25-2010 |
20110239079 | PROGRAMMABLE CIRCUIT FOR HIGH SPEED COMPUTATION OF THE INTERLEAVER TABLES FOR MULTIPLE WIRELESS STANDARDS - A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables. | 09-29-2011 |
20120117359 | NO-DELAY MICROSEQUENCER - An apparatus generally including a memory and a circuit is disclosed. The memory may be configured to store a plurality of instructions. Each of the instructions generally includes a corresponding command and a corresponding command repeat count. At least one of the instructions may include a subprocedure call. The circuit may be configured to (i) decode the instructions one at a time and (ii) present a sequence of the commands at an interface. The sequence (i) may be based on the decoding and (ii) may have no delays between consecutive the commands at the interface. | 05-10-2012 |
20120128102 | L-VALUE GENERATION IN A DECODER - An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of load values corresponding to a trellis of a decoding process. The second circuit generally includes a plurality of calculation layers. The calculation layers may be configured to generate a plurality of maximum values in response to the load values. The third circuit may be configured to generate a plurality of L-values of the decoding process in response to the maximum values. | 05-24-2012 |
20120134325 | BRANCH METRICS CALCULATION FOR MULTIPLE COMMUNICATIONS STANDARDS - A method for branch metric calculation in a plurality of communications standards is disclosed. The method generally includes steps (A) to (C). Step (A) may calculate a plurality of sum values by adding a plurality of first values related to a plurality of information bits, a plurality of second values related to the information bits and a plurality of third values related to a plurality of parity bits. Step (B) may generate a plurality of permutated values by permutating the sum values based on a configuration signal. The configuration signal generally identifies a current one of the communications standards. Step (C) may generate a plurality of branch metrics values by adding pairs of the permutated values. | 05-31-2012 |
20120137190 | RECONFIGURABLE ENCODING PER MULTIPLE COMMUNICATIONS STANDARDS - An apparatus generally including a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) receive a configuration signal that identifies a current one of a plurality of communications standards and (ii) generate a plurality of matrix elements based on the configuration signal. The second circuit may include a plurality of matrixes. The second circuit may be configured to (i) fill the matrixes with the matrix elements and (ii) generate an encoded signal by forward error correction encoding an input signal using the matrixes. The encoded signal generally complies with the current communications standard. | 05-31-2012 |
20120144274 | RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING - A method for forward error correction decoding is disclosed. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword. | 06-07-2012 |
20120166501 | COMPUTATION OF JACOBIAN LOGARITHM OPERATION - An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of first signals carrying (i) a maximum value among a plurality of input values and (ii) a plurality of difference values based on the input values. The second circuit may be configured to generate a plurality of second signals carrying a plurality of intermediate values based on the difference values. The intermediate values are generally respective powers of two. The third circuit may be configured to generate a third signal carrying an output value by adding the maximum value and the intermediate values. The output value may be a Jacobian logarithm computation of the input values. | 06-28-2012 |
20120278648 | TIMER MANAGER ARCHITECTURE BASED ON BINARY HEAP - An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address. | 11-01-2012 |
20120281790 | PARALLEL DECODER FOR MULTIPLE WIRELESS STANDARDS - A method of parallel decoding for a plurality of communications standards generally including steps (A) to (C) is disclosed. Step (A) may receive a plurality of first words, at least two of the first words generally have a different length than each other. Step (B) may parse the first words into a plurality of memories. Step (C) may generate a plurality of second words by decoding the first words using a plurality of decoders. The decoders generally operate in parallel. The decoding of at least one of the first words may be performed by at least two of the decoders. The decoding is generally based on a signal that identifies a current one of the communications standards used to transfer the first words. | 11-08-2012 |
20120284731 | TWO-PASS LINEAR COMPLEXITY TASK SCHEDULER - A method for two-pass scheduling of a plurality of tasks generally including steps (A) to (C). Step (A) may assign each of the tasks to a corresponding one or more of a plurality of processors in a first pass through the tasks. The first pass may be non-iterative. Step (B) may reassign the tasks among the processors to shorten a respective load on one or more of the processors in a second pass through the tasks. The second pass may be non-iterative and may begin after the first pass has completed. Step (C) may generate a schedule in response to the assigning and the reassigning. The schedule generally maps the tasks to the processors. | 11-08-2012 |
20130019139 | VARIABLE PARITY ENCODERAANM Panteleev; Pavel A.AACI MoscowAACO RUAAGP Panteleev; Pavel A. Moscow RUAANM Gasanov; Elyar E.AACI MoscowAACO RUAAGP Gasanov; Elyar E. Moscow RUAANM Neznanov; Ilya V.AACI MoscowAACO RUAAGP Neznanov; Ilya V. Moscow RUAANM Sokolov; Andrey P.AACI MoscowAACO RUAAGP Sokolov; Andrey P. Moscow RUAANM Shutkin; Yurii S.AACI MoscowAACO RUAAGP Shutkin; Yurii S. Moscow RU - An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits. | 01-17-2013 |
20130235907 | Optimization of Data Processors with Irregular Patterns - In described embodiments, data streams with irregular patterns are processed by transformations defined by recursively changing processor state, or iteration level. The data transformations are applied to an arbitrary long portion of data, instead of small portions, that are defined directly by a current processor state. Embodiments combine small parts of, for example, puncturing/repetition patterns into a pattern of bigger parts and apply these patterns of bigger parts to relatively large portions of input data. | 09-12-2013 |
20140040342 | HIGH SPEED ADD-COMPARE-SELECT CIRCUIT - In described embodiments, a trellis decoder includes a memory including a set of registers; and an add-compare-select (ACS) module including at least two ACS layer modules coupled in series and configured to form a feedback loop with carry components in a single clock cycle, wherein the ACS layer module includes at least two branch metrics represented by a plurality of bits and adders configured to generate a plurality of state metrics using carry-save arithmetic, and a plurality of multiplexers configured to perform a selection of a maximum state metric in carry-save arithmetic stored in memory as the carry components. A method of performing high speed ACS operation is disclosed. | 02-06-2014 |
20140223267 | RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING - A method for forward error correction decoding. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword. | 08-07-2014 |