Patent application number | Description | Published |
20080261831 | Ligands and libraries of ligands - The invention relates to variants of Target Biological Molecules (TBMs), such as proteins, peptides and other amino acid sequences that are modified to include cysteine residues at predetermined positions within the TBM. The position of amino acid residues within the TBM that are modified to be cysteine residues is selected for its proximity to ligand binding sites within the TBM. Once an amino acid residue, or the DNA encoding the residue, is modified to cysteine, the TBM linked to potential binding ligands by forming a covalent bond through the cysteine thiol (—SH) reactive group of the variant. | 10-23-2008 |
20100022399 | METHODS FOR RAPIDLY IDENTIFYING SMALL ORGANIC MOLECULE LIGANDS FOR BINDING TO BIOLOGICAL TARGET MOLECULES - The present invention is directed to novel methods for rapidly and unambiguously identifying small organic molecule ligands for binding to biological target molecules. Small organic molecule ligands identified according to the methods of the present invention may find use, for example, as novel therapeutic drug lead compounds, enzyme inhibitors, labeling compounds, diagnostic reagents, affinity reagents for protein purification, and the like. Also presented are novel methods for identifying high affinity binding ligands for a biological target molecule of interest, wherein those methods comprise linking two or more small organic molecule ligands previously identified as being capable of binding to the biological target molecule of interest. Biological target molecules include, for example, polypeptides, nucleic acids, carbohydrates, nucleoproteins, glycoproteins, glycolipids and lipoproteins. | 01-28-2010 |
20120077711 | Novel Ligands and Libraries of Ligands - The present invention provides compounds and libraries of compounds having formula (I): | 03-29-2012 |
20140179542 | METHODS FOR RAPIDLY IDENTIFYING SMALL ORGANIC MOLECULE LIGANDS FOR BINDING TO BIOLOGICAL TARGET MOLECULES - The present invention is directed to novel methods for rapidly and unambiguously identifying small organic molecule ligands for binding to biological target molecules. Small organic molecule ligands identified according to the methods of the present invention may find use, for example, as novel therapeutic drug lead compounds, enzyme inhibitors, labeling compounds, diagnostic reagents, affinity reagents for protein purification, and the like. Also presented are novel methods for identifying high affinity binding ligands for a biological target molecule of interest, wherein those methods comprise linking two or more small organic molecule ligands previously identified as being capable of binding to the biological target molecule of interest. Biological target molecules include, for example, polypeptides, nucleic acids, carbohydrates, nucleoproteins, glycoproteins, glycolipids and lipoproteins. | 06-26-2014 |
Patent application number | Description | Published |
20080299117 | Treatment Method - The invention provides methods of treating autoimmune diseases using lower doses of anti-CD20 antibodies of 100 mg to 200 mg effective to deplete B cells in the patient. | 12-04-2008 |
20090087428 | ANTI-FC-GAMMA RIIB RECEPTOR ANTIBODY AND USES THEREFOR - The present application describes antibodies that selectively bind human FcγRIIB, with little or no binding to other human FcγRs, e.g., human FcγRIIA. The invention also provides isolated bispecific antibodies comprising an antibody that selectively binds FcγRIIB, and a second antibody that specifically binds an activating receptor. Various uses, including therapeutic uses, for those antibodies are also described, including administration with anti-tumor antibodies and methods of inhibiting immune responses and suppressing histamine release. | 04-02-2009 |
20090155257 | IMMUNOGLOBULIN VARIANTS AND USES THEREOF - The invention provides humanized and chimeric anti-CD20 antibodies for treatment of CD20 positive malignancies and autoimmune diseases. | 06-18-2009 |
20090181024 | NOVEL COMPOSITION AND METHODS FOR THE TREATMENT OF IMMUNE RELATED DISEASES - The present invention relates to compositions containing a novel protein and methods of using those compositions for the diagnosis and treatment of immune related diseases. | 07-16-2009 |
20140154242 | IMMUNOGLOBULIN VARIANTS AND USES THEREOF - The invention provides humanized and chimeric anti-CD20 antibodies for treatment of CD20 positive malignancies and autoimmune diseases. | 06-05-2014 |
Patent application number | Description | Published |
20090245520 | DIGITAL CONTENT PROTECTION METHODS - An digital content protection method and device are disclosed. In the method, digital content to be delivered from a content provider to a consumer terminal is retrieved. The digital content is encoded to prevent unauthorized playback. The encoded digital content and a key for decoding the content are separately transmitted from the content provider to the consumer terminal, playback of the encoded digital content requires decoding with the key. | 10-01-2009 |
20090254717 | STORAGE SYSTEM AND METHOD THEREOF - A storage system and a method thereof. The storage system comprises first and second storage devices, first and second analog front ends, and a controller. The first and second analog front ends, coupled to the first and second storage devices, receive first and second analog data from the first and second drive devices for conversion to first and second digital data. The controller, coupled to the first and second analog front ends, comprises a signal processor and a common memory. The signal processor receives the first and second digital data to perform first and second digital signal processing and access the common memory. The common memory is coupled to the signal processor to be accessed thereby. | 10-08-2009 |
20130168857 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs. | 07-04-2013 |
20140035095 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 02-06-2014 |
20140127865 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed. | 05-08-2014 |
20140151867 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 06-05-2014 |
20140191396 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. | 07-10-2014 |
20140377913 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed. | 12-25-2014 |
Patent application number | Description | Published |
20120311353 | PARALLEL PROCESSING COMPUTER SYSTEMS WITH REDUCED POWER CONSUMPTION AND METHODS FOR PROVIDING THE SAME - A computing system is provided that includes a web page search node including a web page collection, a web server, and a search page returner. | 12-06-2012 |
20130054665 | METHODS AND SYSTEMS FOR PERFORMING EXPONENTIATION IN A PARALLEL PROCESSING ENVIRONMENT - An automated method of performing exponentiation is disclosed. A plurality of tables holding factors for obtaining results of Exponentiations are provided. The plurality of tables are loaded into computer memory. Each factor is the result of a second exponentiation of a constant and an exponent. The exponent is related to a memory address corresponding to the factor. A plurality of memory addresses are identified for performing the first exponentiation by breaking up the first exponentiation into equations, the results of which are factors of the first Exponentiation. The exponents of the equations are related to the memory addresses corresponding to the factors held in the tables. A plurality of lookups into the computer memory are performed to retrieve the factors held in the tables corresponding to the respective memory addresses. The retrieved factors are multiplied together to obtain the result of the first exponentiation. | 02-28-2013 |
20130054939 | INTEGRATED CIRCUIT HAVING A HARD CORE AND A SOFT CORE - An integrated circuit (IC) is disclosed. The integrated circuit includes a non-reconfigurable multi-threaded processor core that implements a pipeline having n ordered stages, wherein n is an integer greater than 1. The multi-threaded processor core implements a default instruction set. The integrated circuit also includes reconfigurable hardware that implements n discrete pipeline stages of a reconfigurable execution unit. The n discrete pipeline stages of the reconfigurable execution unit are pipeline stages of the pipeline that is implemented by the multi-threaded processor core. | 02-28-2013 |
20130061213 | METHODS AND SYSTEMS FOR OPTIMIZING EXECUTION OF A PROGRAM IN A PARALLEL PROCESSING ENVIRONMENT - An automated method of optimizing execution of a program in a parallel processing environment is described. The program is adapted to execute in data memory and instruction memory. An optimizer receives the program to be optimized. The optimizer instructs the program to be compiled and executed. The optimizer observes execution of the program and identifies a subset of instructions that execute most often. The optimizer also identifies groups of instructions associated with the subset of instructions that execute most often. The identified groups of instructions include the identified subset of instructions that execute most often. The optimizer recompiles the program and stores the identified groups of instructions in instruction memory. The remaining instructions portions of the program are stored in the data memory. The instruction memory has a higher access rate and smaller capacity than the data memory. Once recompiled, subsequent execution of the program occurs using the recompiled program. | 03-07-2013 |
20130061292 | METHODS AND SYSTEMS FOR PROVIDING NETWORK SECURITY IN A PARALLEL PROCESSING ENVIRONMENT - A method of providing network security for executing applications is disclosed. One or more servers including a plurality of microprocessors and a plurality of network processors are provided. A first grouping of microprocessors executes a first application. The first application is executed using the microprocessors in the first grouping. The microprocessors in the first grouping of microprocessors are permitted to communicate with each other via one or more of the network processors. A second grouping of microprocessors executes a second application. At least one server has one or more microprocessors for executing the first application and one or more different microprocessors for executing the second application. The second application is executed using the microprocessors in the second grouping of microprocessors. One or more of the network processors prevent the microprocessors in the first grouping from communicating with the microprocessors in the second grouping during periods of simultaneous execution. | 03-07-2013 |
20130086564 | METHODS AND SYSTEMS FOR OPTIMIZING EXECUTION OF A PROGRAM IN AN ENVIRONMENT HAVING SIMULTANEOUSLY PARALLEL AND SERIAL PROCESSING CAPABILITY - An automated method of optimizing execution of a program in a parallel processing environment is disclosed. The program has a plurality of threads and is executable in parallel and serial hardware. The method includes receiving the program at an optimizer and compiling the program to execute in parallel hardware. The execution of the program is observed by the optimizer to identify a subset of memory operations that execute more efficiently on serial hardware than parallel hardware. A subset of memory operations that execute more efficiently on parallel hardware than serial hardware are identified. The program is recompiled so that threads that include memory operations that execute more efficiently on serial hardware than parallel hardware are compiled for serial hardware, and threads that include memory operations that execute more efficiently on parallel hardware than serial hardware are compiled for parallel hardware. Subsequent execution of the program occurs using the recompiled program. | 04-04-2013 |
20130226724 | METHODS AND SYSTEMS FOR PRICING COST OF EXECUTION OF A PROGRAM IN A PARALLEL PROCESSING ENVIRONMENT AND FOR AUCTIONING COMPUTING RESOURCES FOR EXECUTION OF PROGRAMS - An automated auction-based method of determining price to execute one or more candidate programs on a parallel computing system is disclosed. The parallel computing system includes a plurality of computing resources, each having a price per unit of time. For each candidate program, a plurality of executions are performed using different amounts of computing resources. The number of program outputs completed during each execution is measured. A plurality of bids defining a price for completing a desired number of program outputs in a desired amount of time are received. The amount of computing resources required to fulfill each bid is determined. A price per unit of time for the computing resources for each bid is calculated based on the price associated with the bid and the determined amount of computing resources required to fulfill the bids. The bids are fulfilled based on the calculated price per unit of time. | 08-29-2013 |
20130311806 | PARALLEL PROCESSING COMPUTER SYSTEMS WITH REDUCED POWER CONSUMPTION AND METHODS FOR PROVIDING THE SAME - A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function. | 11-21-2013 |
20140237175 | PARALLEL PROCESSING COMPUTER SYSTEMS WITH REDUCED POWER CONSUMPTION AND METHODS FOR PROVIDING THE SAME - A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function. | 08-21-2014 |
20140269765 | Broadcast Network - A system and associated methods are disclosed for routing communications amongst computing units in a distributed computing system. In a preferred embodiment, processors engaged in a distributed computing task transmit results of portions of the computing task via a tree of network switches. Data transmissions comprising computational results from the processors are aggregated and sent to other processors via a broadcast medium. Processors receive information regarding when they should receive data from the broadcast medium and activate receivers accordingly. Results from other processors are then used in computation of further results. | 09-18-2014 |
20140281362 | MEMORY ALLOCATION IN A SYSTEM USING MEMORY STRIPING - A system and associated methods are disclosed for allocating memory in a system providing translation of virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a request for memory allocation, identifying an available virtually-contiguous physically-non-contiguous memory region (VCPNCMR) of at least the requested size, where the VCPNCMR is arranged such that physical memory addresses for the VCPNCMR may be derived from a corresponding virtual memory addresses by shifting a contiguous set of bits of the virtual memory address in accordance with information in a matching row of a virtual memory address matching table, and combining the shifted bits with high-order physical memory address bits also associated with the determined matching row and with low-order bits of the virtual memory address, and providing to the requesting process a starting address of the identified VCPNCMR. | 09-18-2014 |
20140281366 | ADDRESS TRANSLATION IN A SYSTEM USING MEMORY STRIPING - A system and associated methods are disclosed for translating virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a virtual memory address, comparing a portion of the received virtual memory address to each of a plurality of entries of a virtual memory address matching table, determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address, shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information from the matching row, and combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address. | 09-18-2014 |
20140282455 | APPLICATION PROFILING - A system and associated methods are disclosed for profiling the execution of program code by a processor. The processor provides an instruction set with special profiling instructions for efficiently determining the bounds and latency of memory operations for blocks of program code. Information gathered regarding the bounds and latency of memory operations are used to determine code optimizations, such as allocation of memory for data structures in memory more local to the processor. | 09-18-2014 |
20150019530 | QUERY LANGUAGE FOR UNSTRUCTED DATA - A system and methods are provided for interactive construction of data queries. One method comprises: generating a query based upon a plurality of user-identified data items, wherein the user-identified data items are data items representing desired results from a query, and wherein information related to the user-identified data items is included in a “given” clause of the query, assigning received input data to a hierarchical set of categories, presenting to a user a plurality of new query results, wherein the plurality of new query results are determined by scanning the received input data to find data elements in the same hierarchical categories as those in the “given” query clause and not in the same hierarchical categories as those of an “unlike” clause of the query, receiving from the user an indication as to whether each query result of the presented plurality of new query results is a desirable query result, adding query results indicated by the user as desirable to the “given” clause of the query, adding query results indicated by the user as undesirable to the “unlike” clause of the query, evaluating a metric indicative of the accuracy of the query, and responsive to a determination that the query achieves a predetermined threshold level of accuracy, storing the query. | 01-15-2015 |
Patent application number | Description | Published |
20090083263 | PARALLEL PROCESSING COMPUTER SYSTEMS WITH REDUCED POWER CONSUMPTION AND METHODS FOR PROVIDING THE SAME - This invention provides a computer system architecture and method for providing the same which can include a web page search node including a web page collection. The system and method can also include a web server configured to receive, from a given user via a web browser, a search query including keywords. The node is caused to search pages in its own collection that best match the search query. A search page returner may be provided which is configured to return, to the user, high ranked pages. The node may include a power-efficiency-enhanced processing subsystem, which includes M processors. The M processors are configured to emulate N virtual processors, and they are configured to limit a virtual processor memory access rate at which each of the N virtual processors accesses memory. The memory accessed by each of the N virtual processors may be RAM. In select embodiments, the memory accessed by each of the N virtual processors includes DRAM having a high capacity yet lower power consumption then SRAM. | 03-26-2009 |
20100241938 | SYSTEM AND METHOD FOR ACHIEVING IMPROVED ACCURACY FROM EFFICIENT COMPUTER ARCHITECTURES - This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function. Alternatively a plurality of SIMD can be used to alternately conduct low-precision computations for a predetermined number of operations and high-precision operations on a fewer number of operations. In an embodiment, aggregation can include summing values within predetermined ranges of orders of magnitude, via an adding tree arrangement, so that significant digits therebetween are preserved. | 09-23-2010 |
Patent application number | Description | Published |
20100214250 | TOUCH SCREEN WITH USER INTERFACE ENHANCEMENT - The present invention is a graphical user interface in a computing device having a processor running an operating system and a display. The graphical user interface comprises a touch screen and a driver coupling the touch screen to the operating system. The driver can display a plurality of icons on the touch screen, or a plurality of screen images having at least one icon, with each of the icons associated with operations on the display and/or the touch screen. Other embodiments include the touch screen having unactivated and activated states, as well as the presence of an application programming interface that enables an application to display at least one image on the touch screen. | 08-26-2010 |
20100275033 | TOUCH SCREEN WITH USER INTERFACE ENHANCEMENT - The present invention is a graphical user interface in a computing device having a processor running an operating system and a display. The graphical user interface comprises a touch screen and a driver coupling the touch screen to the operating system. The driver can display a plurality of icons on the touch screen, or a plurality of screen images having at least one icon, with each of the icons associated with operations on the display and/or the touch screen. Other embodiments include the touch screen having unactivated and activated states, as well as the presence of an application programming interface that enables an application to display at least one image on the touch screen. | 10-28-2010 |
20100275163 | TOUCH SCREEN WITH USER INTERFACE ENHANCEMENT - The present invention is a graphical user interface in a computing device having a processor running an operating system and a display. The graphical user interface comprises a touch screen and a driver coupling the touch screen to the operating system. The driver can display a plurality of icons on the touch screen, or a plurality of screen images having at least one icon, with each of the icons associated with operations on the display and/or the touch screen. Other embodiments include the touch screen having unactivated and activated states, as well as the presence of an application programming interface that enables an application to display at least one image on the touch screen. | 10-28-2010 |
Patent application number | Description | Published |
20100016868 | Hydrodynamic Suture Passer - A hydrodynamic suturing instrument, comprising an elongated cannulated suturing needle having a distal end configured to carry a suture through tissue and a proximal end adapted to connect to a syringe barrel and a lumen extending form said proximal end to an opening at the distal end for having a size for the passage of a suture, the opening at the distal end configured to receive a suture extending from the lumen along an outer surface of the needle wherein a sharp point extends forward of the suture. A companion instrument includes forceps having a distal end with jaws and a proximal end with a cannula extending from the proximal end to the distal end for passage of the needle, and the jaws having an opening enabling passage of the needle through tissue grasped in the jaws. | 01-21-2010 |
20100042117 | SUTURE PASSER - Disclosed are devices and methods relating to a suture passer that passes suture efficiently via motion of fluid in and out of the suture passer. In certain embodiments, the suture passer includes a syringe-like barrel and a plunger for drawing and expelling fluid from the barrel. A suture can be disposed within the barrel, and one end of the suture can be releasably secured to a portion of the plunger. In certain embodiments, the suture end can be releasably secured to a tip portion of the plunger. Various examples of suture releasing mechanisms and actuations of such mechanisms are disclosed. Also disclosed are examples of how such releasably secured sutures can be assembled and packaged into pre-loaded suture passer devices. Also disclosed are examples of suturing operations that can be achieved easier and quicker by use of such suture passer devices. | 02-18-2010 |
20100305610 | SUTURE ANCHOR - Devices and methods for locking a suture to an anchor are disclosed. In certain embodiments, a suture anchor includes a first body configured to be driven into a bone, and a second body also configured to engage the bone and coupled to the first body. At a selected embedded depth of the anchor, the second body moves towards the trailing end of the first body to facilitate a suture-lock configuration as the anchor is driven in deeper. A suture retainer such as a ring, and a flared portion at or near the trailing end of the first body, facilitate locking of a suture between the ring and either or both of the second body and the flared portion as the second body pushes on the ring that in turn pushes against the flared end. In certain embodiments, such suture-lock can be achieved substantially simultaneously as the suture anchor is driven into its final embedded depth. | 12-02-2010 |
20110238112 | SUTURE ANCHOR - Devices and methods for locking a suture to an anchor are disclosed. In certain embodiments, a suture anchor includes a first body configured to be driven into a bone, and a second body also configured to engage the bone and coupled to the first body. At a selected embedded depth of the anchor, the second body moves towards the trailing end of the first body to facilitate a suture-lock configuration as the anchor is driven in deeper. A suture retainer such as a ring, and a flared portion at or near the trailing end of the first body, facilitate locking of a suture between the ring and either or both of the second body and the flared portion as the second body pushes on the ring that in turn pushes against the flared end. In certain embodiments, such suture-lock can be achieved substantially simultaneously as the suture anchor is driven into its final embedded depth. In certain embodiments, the second body can be dimensioned to engage substantially the entire thickness of a cortical layer of the bone to allow the first body to be driven in deeper into a cancellous region to facilitate an easier separation between the first and second bodies. | 09-29-2011 |
Patent application number | Description | Published |
20100176837 | ULTRA-THIN ORGANIC TFT CHEMICAL SENSOR, MAKING THEREOF, AND SENSING METHOD - An embodiment of the invention is an organic thin film transistor chemical sensor. The sensor includes a substrate. A gate electrode is isolated from drain and source electrodes by gate dielectric. An organic ultra-thin semiconductor thin film is arranged with respect to the gate, source and drain electrodes to act as a conduction channel in response to appropriate gate, source and drain potentials. The organic ultra-thin film is permeable to a chemical analyte of interest and consists of one or a few atomic or molecular monolayers of material. An example sensor array system includes a plurality of sensors of the invention. In a preferred embodiment, a sensor chip having a plurality of sensors is mounted in a socket, for example by wire bonding. The socket provides thermal and electrical interference isolation for the sensor chip from associated sensing circuitry that is mounted on a common substrate, such as a PCB (printed circuit board). A method of operating an organic thin film transistor chemical sensor exposes the sensor to a suspected analyte. A low duty cycle voltage pulse train is applied to the gate electrode to reduce baseline drift while sensing for a conduction channel change. | 07-15-2010 |
20100297776 | PEROXIDE CHEMICAL SENSOR AND SENSING METHOD - Sensors, sensing systems and sensing methods of the invention provide for detection of peroxides, including for example, vapor-phase H | 11-25-2010 |
20110124020 | Methods for Detecting Antibodies - Methods for detection of any antibody utilizing a standardized approach applicable to any antibody which provides highly specific assays specific for individual or multiple antibodies. The methods enable improved pharmacokinetic analysis during development and clinical use of antibody-based therapies as well as determination of diagnostic and/or prognostic factors. | 05-26-2011 |
20140109930 | METHOD FOR IN-SITU DRY CLEANING, PASSIVATION AND FUNCTIONALIZATION OF SI-GE SEMICONDUCTOR SURFACES - A method for in-situ dry cleaning of a SiGe semiconductor surface doses the SiGe surface with ex-situ wet HF in a clean ambient environment or in-situ dosing with gaseous NH | 04-24-2014 |
20140113459 | METHOD FOR IN-SITU DRY CLEANING, PASSIVATION AND FUNCTIONALIZATION OF GE SEMICONDUCTOR SURFACES - A method for in-situ dry cleaning of a Ge containing semiconductor surface, other than SiGe. The method is conducted in a vacuum chamber. An oxygen monolayer(s) is formed and promotes removal of essentially all carbon from the surface, and serves to both clean and functionalize the surface. The Ge semiconductor surface is then annealed at a temperature below that which would induce dopant diffusion. | 04-24-2014 |
Patent application number | Description | Published |
20140365642 | Smart Management of Background Network Connections Based on Historical Data - In some implementations, a network daemon can manage access to a mobile device's network interface. The network daemon (e.g., network connection managing process) can monitor the condition of the mobile device's network connection on one or more interfaces. The network daemon can monitor many conditions on the mobile device. The network daemon can receive background networking requests from network clients (e.g., processes, applications) that specify criteria for initiating a network connection. The network daemon can then smartly manage network connections taking into account network conditions, mobile device conditions and/or client criteria received in the client request. This can help reduce battery life impact, memory usage, likelihood of call drops, data usage cost, and load on network operators. | 12-11-2014 |
20140365673 | Smart Management of Background Network Connections - In some implementations, a network daemon can manage access to a mobile device's network interface. The network daemon (e.g., network connection managing process) can monitor the condition of the mobile device's network connection on one or more interfaces. The network daemon can monitor many conditions on the mobile device. The network daemon can receive background networking requests from network clients (e.g., processes, applications) that specify criteria for initiating a network connection. The network daemon can then smartly manage network connections taking into account network conditions, mobile device conditions and/or client criteria received in the client request. This can help reduce battery life impact, memory usage, likelihood of call drops, data usage cost, and load on network operators. | 12-11-2014 |
Patent application number | Description | Published |
20120190910 | SYSTEM FOR DEFINING ENERGY FIELD CHARACTERISTICS TO ILLUMINATE NANO-PARTICLES USED TO TREAT INVASIVE AGENTS - The Invasive Agent Treatment System incorporates the pairing of energy fields with nano-particles to cause a thermal effect in the nano-particles, which thermal effect is transmitted into the biological cells of the invasive agent. The energy fields are derived from at least one or a combination of the following: an electric field, a magnetic field, an electromagnetic field (EM), an acoustic field, and an optical field. The Invasive Agent Treatment System provides the necessary coordination among the characteristics of the nano-particles, concentration of nano-particles, duration of treatment, and applied fields to enable the generation of precisely crafted fields and their application in a mode and manner to be effective with a high degree of accuracy. | 07-26-2012 |
20120190912 | SYSTEM FOR CORRELATING ENERGY FIELD CHARACTERISTICS WITH TARGET PARTICLE CHARACTERISTICS IN THE APPLICATION OF AN ENERGY FIELD TO A LIVING ORGANISM FOR IMAGING AND TREATMENT OF INVASIVE AGENTS - The Energy Field and Target Correlation System automatically correlates the characteristics of target particles and a living organism to compute the characteristics of an energy field that is applied to a living organism to activate the target particles which are bound to or consumed or taken up by invasive agents in the living organism to produce detectable effects which can be used to image and treat the invasive agents. The energy field must be crafted to properly control the response and localize the extent of the illumination. The System automatically selects a set of energy field characteristics, including: field type, frequency, field strength, duration, field modulation, repetition frequency, beam size, and focal point. The determined energy field characteristics then are used to activate field generators to generate the desired energy field. | 07-26-2012 |
20120191148 | SYSTEM FOR CORRELATING ENERGY FIELD CHARACTERISTICS WITH TARGET PARTICLE CHARACTERISTICS IN THE APPLICATION OF AN ENERGY FIELD TO A LIVING ORGANISM FOR TREATMENT OF INVASIVE AGENTS - The Energy Field and Target Correlation System automatically correlates the characteristics of target particles and a living organism to compute the characteristics of an energy field that is applied to a living organism to activate the target particles which are bound to or consumed by invasive agents in the living organism to produce detectable effects which can be used to treat the invasive agents. The energy field must be crafted to properly control the response and localize the extent of the illumination. The System automatically selects a set of energy field characteristics, including: field type, frequency, field strength, duration, field modulation, repetition frequency, beam size, and focal point. The determined energy field characteristics then are used to activate field generators to generate the desired energy field. | 07-26-2012 |
20140243733 | SYSTEM FOR DEFINING ENERGY FIELD CHARACTERISTICS TO ILLUMINATE NANO-PARTICLES USED TO TREAT INVASIVE AGENTS - The Invasive Agent Treatment System incorporates the pairing of energy fields with nano-particles to cause a thermal effect in the nano-particles, which thermal effect is transmitted into the biological cells of the invasive agent. The energy fields are derived from at least one or a combination of the following: an electric field, a magnetic field, an electromagnetic field (EM), an acoustic field, and an optical field. The Invasive Agent Treatment System provides the necessary coordination among the characteristics of the nano-particles, concentration of nano-particles, duration of treatment, and applied fields to enable the generation of precisely crafted fields and their application in a mode and manner to be effective with a high degree of accuracy. | 08-28-2014 |
Patent application number | Description | Published |
20090113292 | FLEXIBLY EDITING HETEROGENEOUS DOCUMENTS - The present invention extends to methods, systems, and computer program products for flexibly editing heterogeneous documents. Different types of documents can be organized on a universal and dynamically adjustable workspace canvas in a manner that indicates relationships between the documents. The workspace canvas is configured to host various different editors simultaneously for editing the different types of documents. Accordingly, embodiments of the present invention facilitate editing different typed documents within the same context and in a manner that maintains relationships between documents. | 04-30-2009 |
20090204912 | GENEERAL PURPOSE INFINITE DISPLAY CANVAS - Expanding and contracting a display screen container. Data is stored in a computer readable medium. The data represents a screen container such as a graphical desktop user interface displayable to a user on a computer display of a computing device. Data is stored representing artifacts, including one or more application graphical user interface artifacts for applications that are instantiated on the computing device. Information is stored specifying locations where each of the artifacts should be graphically located in the screen container. The graphical size of screen container is determined by the locations of the artifacts. Based on user input, a portion of the screen container is displayed to the user on the computer display of the computing device. The screen container may be expanded or contracted based on opening or closing graphical user interface artifacts, adding or removing artifacts, or repositioning artifacts. | 08-13-2009 |
20100054584 | IMAGE-BASED BACKGROUNDS FOR IMAGES - In accordance with one or more aspects of the image-based backgrounds for images, an image is analyzed in order to identify a color that represents the image. An enhanced background is generated based at least in part on the identified color, and both the image and the enhanced background are output on a screen. In addition, or alternatively, the identified color can be saved as being associated with the image in order to be used to generate an enhanced background for the image when the image is displayed. | 03-04-2010 |
20130002702 | IMAGE-BASED BACKGROUNDS FOR IMAGES - In accordance with one or more aspects of the image-based backgrounds for images, an image is analyzed in order to identify a color that represents the image. An enhanced background is generated based at least in part on the identified color, and both the image and the enhanced background are output on a screen. In addition, or alternatively, the identified color can be saved as being associated with the image in order to be used to generate an enhanced background for the image when the image is displayed. | 01-03-2013 |
Patent application number | Description | Published |
20090268356 | INPUT PROTECTION CIRCUIT - A voltage clamp protection circuit to protect against overvoltage conditions where there is insufficient current to blow a fuse. The voltage clamp protection circuit includes a voltage clamp and a thermal cutoff. The voltage clamp clamps any overvoltage to a clamping voltage. If an overvoltage condition persists for too long the voltage clamp dissipates a sufficient amount of heat to activate the thermal cutoff creating an open circuit that protects the rest of the circuit. The voltage clamp protection circuit may be used in combination with a variety of other protection circuits to provide increased protection. | 10-29-2009 |
20110196544 | INPUT PARASITIC METAL DETECTION - A system and method of controlling inductive power transfer in an inductive power transfer system and a method for designing an inductive power transfer system with power accounting. The method of controlling inductive power transfer including measuring a characteristic of input power, a characteristic of power in the tank circuit, and receiving information from a secondary device. Estimating power consumption based on the measured characteristic of tank circuit power and received information and comparing the measured characteristic of input power, the information from the secondary device, and the estimated power consumption to determine there is an unacceptable power loss. The method for designing an inductive power transfer system with power accounting including changing the distance between a primary side and a secondary side and changing a load of the secondary side. For each distance between the primary side and the secondary side and for each load, measuring a circuit parameter on the primary side in the tank circuit and a circuit parameter on the secondary side during the transfer of contactless energy. The method further including selecting a formula to describe power consumption in the system during the transfer of contactless energy based on coefficients and the circuit parameters, and determining the coefficients using the measured circuit parameters. | 08-11-2011 |
20110204711 | SYSTEMS AND METHODS FOR DETECTING DATA COMMUNICATION OVER A WIRELESS POWER LINK - A wireless power supply system that detects communications in the input power to the switching circuit. In this aspect of the invention, the wireless power supply includes a detector for generating a signal indicative of the current in the input to the switching circuitry, a band-pass filter for filtering the detected signal, an amplifier for amplifying the filtered signal, a filter for filtering the amplified signal and a comparator for converting the final signal into a stream of high and low signals that can be passed to a controller for processing as binary data stream. In a second aspect, the wireless power supply system includes a detector for generating a signal that varies in dependence on changes in the phase relationship between the current and the voltage in the primary-side tank circuit, a band-pass filter for filtering the signal, an amplifier for amplifying the filtered signal, a filter for filtering the amplified signal and a comparator for converting the final signal into a stream of high and low signals that can be passed to a controller for processing as binary data stream. | 08-25-2011 |
20120149303 | SYSTEM AND METHOD FOR PROVIDING COMMUNICATIONS IN A WIRELESS POWER SUPPLY - A wireless power transfer system with a remote device having a communication transmitter configured to initiate communications with a framing pulse to prevent noise from being mistaken for legitimate data. The communication system may employ a bi-phase modulation scheme, and the framing pulse may be generated to present no transitions in the communication signal during a specified period of time. The communication transmitter may produce the framing pulse by applying a load in the remote device. The present invention also provides a method for transmitting communication signals in a wireless power supply system including the general steps of: (a) preceding each communication with a framing pulse configured to present a bit sequence that does not exist in legitimate data communications, (b) maintaining the framing pulse for a period of time sufficient to effectively “reset” the communications receiver and (c) transmitting communications following the framing pulse. | 06-14-2012 |
20140077616 | INPUT PARASITIC METAL DETECTION - A system and method of controlling inductive power transfer in an inductive power transfer system and a method for designing an inductive power transfer system with power accounting. The method of controlling inductive power transfer including measuring a characteristic of input power, a characteristic of power in the tank circuit, and receiving information from a secondary device. Estimating power consumption based on the measured characteristic of tank circuit power and received information and comparing the measured characteristic of input power, the information from the secondary device, and the estimated power consumption to determine there is an unacceptable power loss. The method for designing an inductive power transfer system with power accounting including changing the distance between a primary side and a secondary side and changing a load of the secondary side. For each distance between the primary side and the secondary side and for each load, measuring a circuit parameter on the primary side in the tank circuit and a circuit parameter on the secondary side during the transfer of contactless energy. The method further including selecting a formula to describe power consumption in the system during the transfer of contactless energy based on coefficients and the circuit parameters, and determining the coefficients using the measured circuit parameters. | 03-20-2014 |