Patent application number | Description | Published |
20080212665 | System for monitoring the quality of a communications channel with mirror receivers - A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver. | 09-04-2008 |
20090190649 | Conditioning Circuit that Spectrally Shapes a Serviced Bit Stream - A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, such as copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface. | 07-30-2009 |
20100067567 | Multiple High-Speed Bit Stream Interface Circuit - A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit stream interface includes a plurality of signal conditioning circuits. The signal conditioning circuits service each of an RX path and a TX path and include a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream. | 03-18-2010 |
20100221017 | Method and System for Optimum Channel Equalization From a SERDES to an Optical Module - Certain aspects of a method and system for optimum channel equalization between a host Serializer-Deserializer (SerDes) and an optical module may compensate and reduce dispersion loss along an electrical transmit path of a transmitter and an optical transmit path coupled to the transmitter via pre-emphasis. The data degradation as a result of the dispersion loss along the electrical transmit path of the transmitter and the optical transmit path coupled to the transmitter may be recovered by equalizing signals received via an electrical receive path of a receiver communicatively coupled to the transmitter. | 09-02-2010 |
20110249967 | Method and System for Adaptively Setting a Transmitter Filter for a High Speed Serial Link Transmitter - A communication device may be operable to determine, in an optical module, a signal quality associated with each of one or more host transmitter filters in a host circuit. The signal quality may be communicated from the optical module to the host circuit via a management interface. The communication device may control, in the host circuit, configuration of each of the host transmitter filters based on the signal quality. The communication device may be operable to determine, in the host circuit, a signal quality associated with each of one or more module transmitter filters in the optical module. The signal quality associated with each of the module transmitter filters may be communicated from the host circuit to the optical module via the management interface. The communication device may control, in the optical module, configuration of each of the module transmitter filters based on the signal quality. | 10-13-2011 |
20110283020 | METHOD AND SYSTEM FOR PHYSICAL LAYER AGGREGATION - Aspects of a method and system for physical layer aggregation are provided. A first portion of one or more circuits of a network device may be operable to implement media access control (MAC) functions, a second portion of the one or more circuits may be operable to perform physical layer aggregation, and a third portion of the one or more circuits may be operable to perform physical layer functions for communicating over a plurality of physical links. The first portion of the one or more circuits may be operable to encapsulate data into a packet comprising a preamble and convey the packet to the second portion of the one or more circuits. The second portion of the one or more circuits may be operable to fragment the packet into a plurality of fragment payloads and convey each of the fragment payloads to the third portion of the one or more circuits, wherein at least one of the plurality of fragment payloads comprises at least a portion of the preamble. The third portion of the one or more circuits may be operable to add a header to the fragment payloads to generate a corresponding plurality of fragments, and send the plurality of fragments over one or more of the plurality of physical links. | 11-17-2011 |
20120002713 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 01-05-2012 |
20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source - A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider. | 01-12-2012 |
20120120967 | Universal Serial Interface - A communication device may utilize a serial interface to communicate with a peer device via a serial interface link utilizing a serial interface protocol. The communication device may be operable to generate a first serial signal from a first plurality of signals associated with one or more interface protocols. The generated first serial signal may be communicated to the peer device via the serial interface link. The peer device may then regenerate the first plurality of signals from the communicated first serial signal. The communication device may be operable to receive a second serial signal from the peer device via the serial interface link. The second serial signal was generated by the peer device from a second plurality of signals associated with the one or more interface protocols. The communication device may then regenerate the second plurality of signals from the received second serial signal. | 05-17-2012 |
20120327769 | System and Method for Increasing Input/Output Speeds in a Network Switch - A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox. | 12-27-2012 |
20130058363 | METHOD AND SYSTEM FOR SPEED NEGOTIATION FOR TWISTED PAIR LINKS USING INTELLIGENT E-FIFO IN FIBRE CHANNEL SYSTEMS - Systems, apparatuses and methods are disclosed for using elastic buffers in fibre channel systems over twisted pair links. One such system includes a fibre channel host device and another fibre channel host device communicatively coupled to the fibre channel device over a twisted pair link. The system also includes a slave physical layer (PHY) circuit residing in the fibre channel host device and a master PHY circuit residing in the another fibre channel host device. The master PHY circuit is operable to transmit, using a reference clock, data from a transmit elastic buffer. The slave PHY circuit is operable to receive the data transmitted by the master PHY circuit and to store the received data using a derived clock recovered from the received data. | 03-07-2013 |
20130083810 | System and Method for Bit-Multiplexed Data Streams Over Multirate Gigabit Ethernet - Input/output of network switches and the like are improved by a system including a gearbox, an inverse-gearbox, and a Gigabit Ethernet link coupling them. The gearbox and inverse-gearbox interconnect data streams received through wider lower rate Gigabit Ethernet interfaces through narrower faster rate interfaces. The gearbox is configured to bit-multiplex physical-layer data streams received through input interfaces to generate bit-multiplexed data streams. The inverse-gearbox is configured to demultiplex the multiplexed data streams and to output the recovered data streams through output interfaces. One of the output interfaces is selected for each recovered data stream according to a respective embedded physical-layer data stream identifier. | 04-04-2013 |
20130243072 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 09-19-2013 |
20140056315 | METHOD AND SYSTEM FOR SPEED NEGOTIATION FOR TWISTED PAIR LINKS IN FIBRE CHANNEL SYSTEMS - Certain aspects of a method and system for speed negotiation for twisted pair links in fibre channel systems are disclosed. Aspects of a method may include communicating data between fibre channel host devices communicatively coupled via a twisted pair link based on a common speed negotiated between the fibre channel host devices. At least one available speed may be determined for the communication of data between the fibre channel host devices over the twisted pair link. The determined available speeds for each of the fibre channel host devices may be exchanged via at least one fast link pulse signal. The common speed negotiated may be a highest available speed for the communication of data between the fibre channel host devices. | 02-27-2014 |
20140064088 | System and Method for Increasing Input/Output Speeds in a Network Switch - A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox. | 03-06-2014 |
20140241369 | System and Method for Data Flow Identification and Alignment in a 40/100 Gigabit Ethernet Gearbox - A system and method for data flow identification and alignment in a 40/100 gigabit Ethernet gearbox. Virtual lane (VL) identifiers can be identified to create an effective wiring diagram for data flows. This wiring diagram enables a multiplexer or de-multiplexer to align the VL identifiers to match physical lane identifiers. | 08-28-2014 |
20140241411 | System and Method for Link Training of a Backplane Physical Layer Device Operating in Simplex Mode - A system and method for link training of a backplane physical layer device operating in simplex mode. In one embodiment of the present invention, a backplane training system includes a backplane device coupled to a first end of a backplane and at least one retimer device at a second end of the backplane. During a training process, a receiving device is configured to forward a training frame (e.g., DME frame) to a second device for use by a transmitter in the second device. | 08-28-2014 |
20140286346 | System and Method for 10/40 Gigabit Ethernet Multi-Lane Gearbox - A system and method for system and method for 10/40 gigabit Ethernet multi-lane gearbox. In one embodiment, a gearbox device includes one or more inputs on a line side of the device, the one or more inputs being configured to receive four asynchronous 10 Gbit/s Ethernet channels, a marking module that is configured to insert virtual lane markers into four data flows at defined intervals to produce four marked data flows, and a 4:n physical media attachment (PMA) module that is configured to generate one or more higher-rate data flows based on the four marked data flows. | 09-25-2014 |
20150089319 | INBAND MANAGEMENT OF ETHERNET LINKS - Disclosed are various embodiments for in-band management of Ethernet links utilizing a bit-interleaved parity (BIP) block in a transmission frame. According to various embodiments, a bit-interleaved parity error code may be generated for a monitored portion of network data for transmission in a first bit-interleaved parity block. Subsequently, network management data may be encoded in a plurality of bits for transmission in a second bit-interleaved parity block according to a predefined block code, wherein the predefined block code generates the plurality of bits to maintain a DC balance between the bit-interleaved parity error code and the plurality of bits. | 03-26-2015 |