Patent application number | Description | Published |
20090039924 | Systems and methods for reducing distortion in semiconductor based sampling systems - Circuits and methods that improve the performance of electronic sampling systems are provided. Parasitic capacitance associated with bootstrap circuitry is reduced, thereby decreasing signal distortion caused by capacitive loading at the input of the sampling circuit. The impedance of a sampling semiconductor switch is maintained substantially constant during sample states, at least in part, by accounting for non-linear parasitic capacitances associated with a sampling switch control terminal in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 02-12-2009 |
20090121912 | Circuits and methods to reduce or eliminate signal-dependent modulation of a reference bias - Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant. | 05-14-2009 |
20110148388 | RADIATION TOLERANT CIRCUIT FOR MINIMIZING THE DEPENDENCE OF A PRECISION VOLTAGE REFERENCE FROM GROUND BOUNCE AND SIGNAL GLITCH - A radiation-hardened reference circuit includes a precision voltage reference circuit for generating a current-controlling voltage at first and second terminals, a driver circuit for receiving the current-controlling voltage at first and second terminals and for generating an output reference voltage, and a differential sampling circuit having first and second input terminals coupled to the first and second terminals of the voltage reference circuit, and first and second output terminals coupled to the first and second terminals of the driver circuit. | 06-23-2011 |
20110273222 | ELECTRICALLY TUNABLE CONTINUOUS-TIME CIRCUIT AND METHOD FOR COMPENSATING A POLYNOMIAL VOLTAGE-DEPENDENT CHARACTERISTIC OF CAPACITANCE - A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor. | 11-10-2011 |
20110273229 | CONTINUOUS-TIME CIRCUIT AND METHOD FOR CAPACITANCE EQUALIZATION BASED ON ELECTRICALLY TUNABLE VOLTAGE PRE-DISTORTION OF A C-V CHARACTERISTIC - A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor. | 11-10-2011 |
20110304375 | AMPLITUDE-STABILIZED EVEN ORDER PRE-DISTORTION CIRCUIT - An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal. | 12-15-2011 |
20110304392 | AMPLITUDE-STABILIZED ODD ORDER PRE-DISTORTION CIRCUIT - An amplitude-stabilized third-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a plurality of replica cells having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a plurality of control circuits coupled to the differential outputs of the replica cells, and driving the load control inputs of the replica cells and the weighted inputs of a signal combiner driving the load control input of the main cell. The main cell and the replica cells each include a cross-coupled differential cell having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal. | 12-15-2011 |
20110309808 | BIAS-STARVING CIRCUIT WITH PRECISION MONITORING LOOP FOR VOLTAGE REGULATORS WITH ENHANCED STABILITY - A regulator circuit includes a voltage regulator having a stability control input and an output for providing a regulated output voltage, an amplifier circuit having an input for receiving an error voltage of the voltage regulator, and an output, and a control circuit having an input coupled to the output of the amplifier and an output coupled to the stability control input of the voltage regulator, such that the regulator stability is maximized while the error voltage is minimized. The voltage regulator includes an LDO voltage regulator, the amplifier circuit includes an operational amplifier circuit, and the control circuit includes a load-sensing or load-replicating circuit. | 12-22-2011 |
20120194257 | CONTINUOUS-TIME CIRCUIT AND METHOD FOR CAPACITANCE EQUALIZATION BASED ON ELECTRICALLY TUNABLE VOLTAGE PRE-DISTORTION OF A C-V CHARACTERISTIC - A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor. | 08-02-2012 |
20120200332 | ELECTRICALLY TUNABLE CONTINUOUS-TIME CIRCUIT AND METHOD FOR COMPENSATING A POLYNOMIAL VOLTAGE-DEPENDENT CHARACTERISTIC OF CAPACITANCE - A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor. | 08-09-2012 |
20130120026 | HIGH-STABILITY RESET CIRCUIT FOR MONITORING SUPPLY UNDERVOLTAGE AND OVERVOLTAGE - A method of monitoring supply voltage includes providing a single reference voltage, providing a single ratioed supply voltage, comparing the reference voltage to the ratioed supply voltage to provide an output signal, wherein the output signal comprises a first logic value in first and second operating conditions, and a second logic value in a third operating condition, wherein the first, second, and third operating conditions are determined by two crossing points of the reference voltage and ratioed supply voltage characteristics. The first and second operating conditions can represent undervoltage and overvoltage conditions, and the third operating condition can represent a normal operating condition. The reference voltage can be provided by a bandgap reference circuit. | 05-16-2013 |
20140203875 | HIGH-GAIN LOW-NOISE PREAMPLIFIER AND ASSOCIATED AMPLIFICATION AND COMMON-MODE CONTROL METHOD - A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together. | 07-24-2014 |