Patent application number | Description | Published |
20130346805 | FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM - A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation. | 12-26-2013 |
20140321202 | DEFECTIVE BLOCK MANAGEMENT - In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations. | 10-30-2014 |
20150058530 | SMART DYNAMIC WEAR BALANCING BETWEEN MEMORY POOLS - A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated. | 02-26-2015 |
20150071008 | Systems And Methods For Read Disturb Management In Non-Volatile Memory - Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles. | 03-12-2015 |
20150143026 | TEMPERATURE BASED FLASH MEMORY SYSTEM MAINTENANCE - A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed. | 05-21-2015 |
20150348649 | BIT ERROR RATE MAPPING IN A MEMORY SYSTEM - A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program. | 12-03-2015 |
20160077903 | Selective Sampling of Data Stored in Nonvolatile Memory - Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts. | 03-17-2016 |
20160078960 | METHOD AND APPARATUS FOR WRITING DATA TO NON-VOLATILE MEMORY - Devices and methods implemented therein are disclosed for storing data in memory pages of a non-volatile memory of the storage device. The device comprises a non-volatile memory, a reading circuit, a programming circuit and a read disturb detector. The non-volatile memory has an erased memory page comprising a plurality of multi-layer cells (MLCs). The reading circuit is configured to read a respective electric charge stored in each of the plurality of MLCs. The programming circuit is configured to store data in the plurality of MLCs at either one of a first storage density or a second storage density. The read disturb detector is configured to determine whether the erased memory page is read disturbed and if the erased memory page is read disturbed, cause the programming circuit to store data into the MLCs at the second storage density that is less than the first storage density. | 03-17-2016 |