Patent application number | Description | Published |
20100053129 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC EQUIPMENT - An integrated circuit device includes: a plurality of data line driving circuits that drive a plurality of data voltage supply lines; a comparator that compares a data voltage corresponding to a data line driving circuit to be corrected among the plurality of data line driving circuits with a comparator reference voltage; a correction data calculation section that calculates correction data for correcting a difference in the data voltage based on a comparison result given from the comparator; and a plurality of correction circuits that each correct image data based on the correction data given from the correction data calculation section, and output the image data after correction processing to a corresponding data line driving circuit among the plurality of data line driving circuits. | 03-04-2010 |
20100053145 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC EQUIPMENT - An integrated circuit device includes: a plurality of data line driving circuits that drive a plurality of data voltage supply lines; and a correction data calculation section that calculates correction data for correcting differences in data voltages outputted from the plurality of data line driving circuits, wherein the correction data calculation section executes, in one horizontal scanning period in a non-display period in a vertical scanning period, a first mode to obtain the correction data corresponding to a data line driving circuit to be corrected among the plurality of data line driving circuits. | 03-04-2010 |
20100194718 | INTEGRATED CIRCUIT DEVICE, ELECTRO OPTICAL DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes: a data line driving circuit provided for each of a plurality of data signal supply lines that supplies a multiplexed data signal to a corresponding data signal supply line; an order offset register that stores a first order offset setting value; an order setting circuit that sets the order of driving the first pixel; and an order offset addition circuit corresponding to the data line driving circuit. When the data line driving circuit drives the q-th (q is a natural number less than p) pixel in the r-th (r is a natural number less than p) place in the order, the order offset addition circuit processes addition of an order offset correction value based on the r-th order offset setting value among the first order offset setting value. | 08-05-2010 |
20100194734 | INTEGRATED CIRCUIT DEVICE, ELECTRO OPTICAL DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes: a data line driving circuit that is provided for each of a plurality of data signal supply lines and supplies a multiplexed data signal to a corresponding data signal supply line among the plurality of data signal supply lines; a pattern output circuit; and an order setting circuit, wherein a plurality of data signals after demultiplexing obtained by demultiplexing the multiplexed data signal by a demultiplexer are supplied to a plurality of pixels in one horizontal scanning period, the pattern output circuit outputs, as an output rotation pattern, at each frame or each set of plural frames, one of first rotation pattern—M-th (M is a natural number of 2 or more) rotation pattern, which are rotation patterns each defining an order of driving first pixel—p-th (p is a natural number of 2 or more) pixel among the plurality of pixels. | 08-05-2010 |
20100302266 | INTEGRATED CIRCUIT APPARATUS, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT - An integrated circuit apparatus includes data-line drive circuits, an offset register that stores offset set values corresponding to a plurality of pixels, and correction circuits that perform processing of correcting the offsets on the basis of the offset set values. The offset register stores offset set values for the positive polarity and offset set values for the negative polarity. The data-line drive circuits supply data signals resulting from correction based on the offset set values for the positive polarity in a positive drive period and supply data signals resulting from correction based on the offset set values for the negative polarity in a negative drive period. | 12-02-2010 |
20120229432 | DRIVING INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS - A first receiver receives a clock. A second receiver receives a differential type image signal. An image signal receiving unit performs sampling the differential type image signal by the clock, and generates an image signal driving an electro-optic device. A third receiver receives a time multiplexed control signal. A reception buffer performs sampling of the time multiplexed control signal by the clock and the stores the time multiplexed control signal. A driving control unit performs a driving control of the electro-optic device on the basis of the stored time multiplexed control signal. | 09-13-2012 |
20150049073 | DATA LINE DRIVER, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC APPLIANCE - In a data line driver, successively input image data are sequentially stored in a first data storage unit and a second data storage unit. A subtracter calculates a difference value between the image data stored in the first data storage unit and the image data stored in the second data storage unit. A timing pulse generator generates a timing pulse based on the calculated difference value, and a charge supply circuit supplies a charge to a gradation voltage output terminal in accordance with the timing pulse. The rising and falling characteristics of gradation voltage when the image data is changed are improved in this way. | 02-19-2015 |
20150049848 | RECEIVER CIRCUIT, COMMUNICATION SYSTEM, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING RECEIVER CIRCUIT - A receiver circuit etc. which can receive a high-speed signal is provided without providing a PLL circuit etc. A first receiver circuit for capturing an input signal at a plurality of capture timings determined based on a capture clock signal, includes a delay circuit configured to delay the input signal by a set delay time, and output the delayed input signal, a data latch circuit configured to capture the input signal delayed by the delay circuit at each capture timing, a data test circuit configured to test a latch signal captured by the data latch circuit, and a data test result register configured so that a test result value is set therein. The data test circuit compares the latch signal captured by the latch circuit at each capture timing with an expected value, and outputs the result of the comparison. | 02-19-2015 |