Afghahi
Cyrus Afghahi, Aliso Viejo, CA US
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20090316512 | BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S - The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use. | 12-24-2009 |
Morteza Afghahi, Coto De Caza, CA US
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20080224729 | INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT - In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential. | 09-18-2008 |
Morteza Afghahi, Irvine, CA US
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20120223756 | Method and System for High Speed, Low Power and Small Flip-Flops - A master-slave flip-flop may be operable to sense a signal, received by a slave circuit from a master circuit, at a pair of serially coupled NMOS transistors and/or at a pair of serially coupled PMOS transistors in the slave circuit. The flip-flop may generate a corresponding output signal at an output terminal based on the sensing of the signal received by the slave circuit. The flip-flop may receive, in a feedback path of the slave circuit, a SET signal. An inverted version of the SET signal may be received via a gate terminal of a PMOS transistor in the master circuit. The flip-flop may receive, in a feedback path of the master circuit, a RESET signal. The RESET signal may also be received via a gate of a NMOS transistor in the master circuit. The flip-flop may disable an input terminal utilizing the SET signal and/or the RESET signal. | 09-06-2012 |
Morteza Cyrus Afghahi, Coto De Caza, CA US
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20080225568 | DENSE READ-ONLY MEMORY - In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node. | 09-18-2008 |
20080225613 | MEMORY ROW AND COLUMN REDUNDANCY - In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal. | 09-18-2008 |
20080266935 | DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE - In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors. | 10-30-2008 |
20090010041 | Hybrid DRAM - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors. | 01-08-2009 |
Morteza Cyrus Afghahi, Cota De Caza, CA US
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20080291728 | Single-Poly Non-Volatile Memory Cell - A non-volatile memory cell is provided that includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate. | 11-27-2008 |
Morteza Cyrus Afghahi, Irvine, CA US
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20140047296 | Error Correcting Code Design For A Parity Enabled Memory - A memory system provides Error Correcting Code (ECC) protection for data stored in a parity enabled memory. The memory may include designated parity locations for data stored in the memory. During write operations, the system may obtain data to write into the memory, compute ECC protection bits for the data, and store the ECC protection bits in locations in the memory designated as parity locations for the data. During read operations, the system may read data from the memory. The system may also read protection bits for the data from locations designated as parity locations for the data. Then, the system may interpret the protection bits as ECC protection bits instead of as parity bits. The system may provide ECC protection for data without additional overhead or memory configuration changes to the parity enabled memory. | 02-13-2014 |