Patent application number | Description | Published |
20120079102 | Requester Based Transaction Status Reporting in a System with Multi-Level Memory - A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed. | 03-29-2012 |
20120079204 | Cache with Multiple Access Pipelines - Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags. | 03-29-2012 |
20120191914 | PERFORMANCE AND POWER IMPROVEMENT ON DMA WRITES TO LEVEL TWO COMBINED CACHE/SRAM THAT IS CAUSED IN LEVEL ONE DATA CACHE AND LINE IS VALID AND DIRTY - This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors. | 07-26-2012 |
20120191915 | EFFICIENT LEVEL TWO MEMORY BANKING TO IMPROVE PERFORMANCE FOR MULTIPLE SOURCE TRAFFIC AND ENABLE DEEPER PIPELINING OF ACCESSES BY REDUCING BANK STALLS - The level two memory of this invention supports coherency data transfers with level one cache and DMA data transfers. The width of DMA transfers is 16 bytes. The width of level one instruction cache transfers is 32 bytes. The width of level one data transfers is 64 bytes. The width of level two allocates is 128 bytes. DMA transfers are interspersed with CPU traffic and have similar requirements of efficient throughput and reduced latency. An additional challenge is that these two data streams (CPU and DMA) require access to the level two memory at the same time. This invention is a banking technique for the level two memory to facilitate efficient data transfers. | 07-26-2012 |
20120191916 | OPTIMIZING TAG FORWARDING IN A TWO LEVEL CACHE SYSTEM FROM LEVEL ONE TO LEVER TWO CONTROLLERS FOR CACHE COHERENCE PROTOCOL FOR DIRECT MEMORY ACCESS TRANSFERS - A second level memory controller uses shadow tags | 07-26-2012 |
20120192027 | Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme - The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks. | 07-26-2012 |
20120198160 | Efficient Cache Allocation by Optimizing Size and Order of Allocate Commands Based on Bytes Required by CPU - This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line. | 08-02-2012 |
20120198161 | NON-BLOCKING, PIPELINED WRITE ALLOCATES WITH ALLOCATE DATA MERGING IN A MULTI-LEVEL CACHE SYSTEM - This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache line, merges the write data with data returned from the external memory and stores merged data in the cache. The cache controller includes buffers with plural entries storing the write address, the write data, the position of the write data within a cache line and unique identification number. This stored data enables the cache controller to proceed to servicing other access requests while waiting for response from the external memory. | 08-02-2012 |
20120198162 | Hazard Prevention for Data Conflicts Between Level One Data Cache Line Allocates and Snoop Writes - A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line. | 08-02-2012 |
20120198163 | Level One Data Cache Line Lock and Enhanced Snoop Protocol During Cache Victims and Writebacks to Maintain Level One Data Cache and Level Two Cache Coherence - This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write. | 08-02-2012 |
20120198164 | Programmable Address-Based Write-Through Cache Control - This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write- back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit. | 08-02-2012 |
20120198171 | Cache Pre-Allocation of Ways for Pipelined Allocate Requests - This invention is a data processing system with a data cache. The cache controller responds to a cache miss requiring allocation by pre-allocating a way in the set to an allocation request according to said least recently used indication of said ways and then update the least recently used indication of remaining ways of the set. This permits read allocate requests to the same set to proceed without introducing processing stalls due to way contention. This also allows multiple outstanding allocate requests to the same set and way combination. The cache also compares the address of a newly received allocation request to stall this allocation request if the address matches an address of any pending allocation request. | 08-02-2012 |
20120198272 | Priority Based Exception Mechanism for Multi-Level Cache Controller - This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal. | 08-02-2012 |
20120198310 | CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES - This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source. | 08-02-2012 |
20120260031 | ENHANCED PIPELINING AND MULTI-BUFFER ARCHITECTURE FOR LEVEL TWO CACHE CONTROLLER TO MINIMIZE HAZARD STALLS AND OPTIMIZE PERFORMANCE - This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline. | 10-11-2012 |
20120290755 | Lookahead Priority Collection to Support Priority Elevation - A queuing requester for access to a memory system. Transaction requests received from two or more requestors access to the memory system. Each transaction request includes an associated priority value. A request queue is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system uses the selected priority value. | 11-15-2012 |
20120290756 | Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration - Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource. | 11-15-2012 |
20130021858 | Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System - In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency. | 01-24-2013 |
20130036337 | Clock Control of Pipelined Memory for Improved Delay Fault Testing - In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank. | 02-07-2013 |
20130176060 | Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing - This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence. | 07-11-2013 |
20130326155 | SYSTEM AND METHOD OF OPTIMIZED USER COHERENCE FOR A CACHE BLOCK WITH SPARSE DIRTY LINES - A system and method of optimized user coherence for a cache block with sparse dirty lines is disclosed wherein valid and dirty bits of each set are logically AND'ed together and the result for multiple sets are logically OR'ed together resulting in an indication whether a particular block has any dirty lines. If the result indicates that a block does not have dirty lines, then that entire block can be skipped from being written back without affecting coherency. | 12-05-2013 |
20140108737 | ZERO CYCLE CLOCK INVALIDATE OPERATION - A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be trated as a cache miss to ensure that the requesting CPU will receive valid data. | 04-17-2014 |