Patent application number | Description | Published |
20140045589 | DYNAMIC GAMEPLAY ADVERTISEMENTS - Data characterizing historical skills-based gaming metrics for a first user and historical skills-based gaming metrics for at least one second user is accessed. Using the accessed data and a set of rules, a targeted advertisement to present to the first user is determined. The targeted advertisement specifies at least one skills-based game and a characterization of the at least one second user's historical skills-based gaming metrics. The targeted advertisement is generated. Data characterizing the targeted advertisement is provided. Related apparatus, systems, techniques, and articles are also described. | 02-13-2014 |
20140200062 | Peer-to-Peer Wagering Platform - Data characterizing historical skills-based gaming metrics for a first user and historical skills-based gaming metrics for at least one second user is accessed. Using the accessed data and a set of rules, a targeted advertisement to present to the first user is determined. The targeted advertisement specifies at least one skills-based game and a characterization of the at least one second user's historical skills-based gaming metrics. The targeted advertisement is generated. Data characterizing the targeted advertisement is provided. Related apparatus, systems, techniques, and articles are also described. | 07-17-2014 |
20160110960 | Peer-to-Peer Wagering Platform - Data characterizing historical skills-based gaming metrics for a first user and historical skills-based gaming metrics for at least one second user is accessed. Using the accessed data and a set of rules, a targeted advertisement to present to the first user is determined. The targeted advertisement specifies at least one skills-based game and a characterization of the at least one second user's historical skills-based gaming metrics. The targeted advertisement is generated. Data characterizing the targeted advertisement is provided. Related apparatus, systems, techniques, and articles are also described. | 04-21-2016 |
Patent application number | Description | Published |
20110080404 | Redistribution Of Generated Geometric Primitives - One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for per-vertex by multiple graphics pipelines. Geometric primitives that are generated in a first processing stage are collected and redistributed more evenly and in smaller batches to the multiple graphics pipelines for vertex processing in a second processing stage. The smaller batches do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second stage are balanced. Therefore, the performance of the tessellation and geometry shaders is improved. | 04-07-2011 |
20110169850 | BLOCK LINEAR MEMORY ORDERING OF TEXTURE DATA - A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob. | 07-14-2011 |
20120176377 | BLOCK LINEAR MEMORY ORDERING OF TEXTURE DATA TECHNIQUES - A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob. | 07-12-2012 |
20130038620 | TIME SLICE PROCESSING OF TESSELLATION AND GEOMETRY SHADERS - One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved. | 02-14-2013 |
20130117758 | COMPUTE WORK DISTRIBUTION REFERENCE COUNTERS - One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread. | 05-09-2013 |
20130160021 | SIGNALING, ORDERING, AND EXECUTION OF DYNAMICALLY GENERATED TASKS IN A PROCESSING SYSTEM - One embodiment of the present invention sets forth a technique for enabling the insertion of generated tasks into a scheduling pipeline of a multiple processor system allows a compute task that is being executed to dynamically generate a dynamic task and notify a scheduling unit of the multiple processor system without intervention by a CPU. A reflected notification signal is generated in response to a write request when data for the dynamic task is written to a queue. Additional reflected notification signals are generated for other events that occur during execution of a compute task, e.g., to invalidate cache entries storing data for the compute task and to enable scheduling of another compute task. | 06-20-2013 |
20130185725 | SCHEDULING AND EXECUTION OF COMPUTE TASKS - One embodiment of the present invention sets forth a technique for selecting a first processor included in a plurality of processors to receive work related to a compute task. The technique involves analyzing state data of each processor in the plurality of processors to identify one or more processors that have already been assigned one compute task and are eligible to receive work related to the one compute task, receiving, from each of the one or more processors identified as eligible, an availability value that indicates the capacity of the processor to receive new work, selecting a first processor to receive work related to the one compute task based on the availability values received from the one or more processors, and issuing, to the first processor via a cooperative thread array (CTA), the work related to the one compute task. | 07-18-2013 |
20130185728 | SCHEDULING AND EXECUTION OF COMPUTE TASKS - One embodiment of the present invention sets forth a technique for assigning a compute task to a first processor included in a plurality of processors. The technique involves analyzing each compute task in a plurality of compute tasks to identify one or more compute tasks that are eligible for assignment to the first processor, where each compute task is listed in a first table and is associated with a priority value and an allocation order that indicates relative time at which the compute task was added to the first table. The technique further involves selecting a first task compute from the identified one or more compute tasks based on at least one of the priority value and the allocation order, and assigning the first compute task to the first processor for execution. | 07-18-2013 |
20130198759 | CONTROLLING WORK DISTRIBUTION FOR PROCESSING TASKS - A technique for controlling the distribution of compute task processing in a multi-threaded system encodes each processing task as task metadata (TMD) stored in memory. The TMD includes work distribution parameters specifying how the processing task should be distributed for processing. Scheduling circuitry selects a task for execution when entries of a work queue for the task have been written. The work distribution parameters may define a number of work queue entries needed before a cooperative thread array” (“CTA”) may be launched to process the work queue entries according to the compute task. The work distribution parameters may define a number of CTAS that are launched to process the same work queue entries. Finally, the work distribution parameters may define a step size that is used to update pointers to the work queue entries. | 08-01-2013 |
20130268942 | METHODS AND APPARATUS FOR AUTO-THROTTLING ENCAPSULATED COMPUTE TASKS - Systems and methods for auto-throttling encapsulated compute tasks. A device driver may configure a parallel processor to execute compute tasks in a number of discrete throttled modes. The device driver may also allocate memory to a plurality of different processing units in a non-throttled mode. The device driver may also allocate memory to a subset of the plurality of processing units in each of the throttling modes. Data structures defined for each task include a flag that instructs the processing unit whether the task may be executed in the non-throttled mode or in the throttled mode. A work distribution unit monitors each of the tasks scheduled to run on the plurality of processing units and determines whether the processor should be configured to run in the throttled mode or in the non-throttled mode. | 10-10-2013 |
20140118375 | TECHNIQUES FOR MANAGING GRAPHICS PROCESSING RESOURCES IN A TILE-BASED ARCHITECTURE - One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released. | 05-01-2014 |
20140118376 | HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE BASED ARCHITECTURE - One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing. | 05-01-2014 |
Patent application number | Description | Published |
20090022500 | METHOD AND SYSTEM FOR OPTOELECTRONICS TRANSCEIVERS INTEGRATED ON A CMOS CHIP - Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via grating couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser. | 01-22-2009 |
20100059822 | METHOD AND SYSTEM FOR MONOLITHIC INTEGRATION OF PHOTONICS AND ELECTRONICS IN CMOS PROCESSES - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer. | 03-11-2010 |
20100060972 | METHOD AND CIRCUIT FOR ENCODING MULTI-LEVEL PULSE AMPLITUDE MODULATED SIGNALS USING INTEGRATED OPTOELECTRONIC DEVICES - Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by two or more electrical input signals. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers utilizing flip-flops. Phase addition may be synchronized utilizing one or more electrical delay lines. The optical modulator may be integrated on a single substrate, which may include one of: silicon, gallium arsenide, germanium, indium gallium arsenide, polymers, or indium phosphide. The optical modulator may include a Mach-Zehnder interferometer or one or more ring modulators. | 03-11-2010 |
20110206322 | Method and System for Implementing High-Speed Interfaces Between Semiconductor Dies in Optical Communication Systems - A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration. | 08-25-2011 |
20120132993 | Monolithic Integration Of Photonics And Electronics In CMOS Processes - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. | 05-31-2012 |
20120135566 | Monolithic Integration Of Photonics And Electronics In CMOS Processes - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. | 05-31-2012 |
20120301149 | Method And System For Hybrid Integration Of Optical Communication Systems - Methods and systems for hybrid integration of optical communication systems are disclosed and may include receiving continuous wave (CW) optical signals in a silicon photonics die (SPD) from an optical source external to the SPD. The received CW optical signals may be processed based on electrical signals received from an electronics die bonded to the SPD via metal interconnects. Modulated optical signals may be received in the SPD from optical fibers coupled to the SPD. Electrical signals may be generated in the SPD based on the received modulated optical signals and communicated to the electronics die via the metal interconnects. The CW optical signals may be received from an optical source assembly coupled to the SPD and/or from one or more optical fibers coupled to the SPD. The received CW optical signals may be processed utilizing one or more optical modulators, which may comprise Mach-Zehnder interferometer modulators. | 11-29-2012 |
20120315036 | Method And System For Encoding Multi-Level Pulse Amplitude Modulated Signals Using Integrated Optoelectronic Devices - Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by two or more electrical input signals. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers. Phase addition may be synchronized utilizing one or more electrical delay lines. The optical modulator may be integrated on a single substrate, which may include one of: silicon, gallium arsenide, germanium, indium gallium arsenide, polymers, or indium phosphide. The optical modulator may include a Mach-Zehnder interferometer or one or more ring modulators. | 12-13-2012 |
20130094865 | METHOD AND SYSTEM FOR OPTOELECTRONICS TRANSCEIVERS INTEGRATED ON A CMOS CHIP - Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via grating couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser. | 04-18-2013 |
20140186028 | METHOD AND SYSTEM FOR ENCODING MULTI-LEVEL PULSE AMPLITUDE MODULATED SIGNALS USING INTEGRATED OPTOELECTRONIC DEVICES - Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by two or more of a plurality of electrical input signals. The optical modulator may configure levels in the multi-level amplitude modulated optical signal. Drivers may be coupled to the optical modulator, and the plurality of electrical input signals may be synchronized before being communicated to said drivers. Two or more of said plurality of electrical input signals may be selected utilizing one or more multiplexers. The one or more multiplexers may select an electrical input or a complement of the electrical input. Phase addition may be synchronized in a plurality of optical modulator elements in the optical modulator utilizing one or more electrical delay lines. The optical modulator may be integrated on a single substrate. | 07-03-2014 |
20150270898 | Method And System For Monolithic Integration of Photonics And Electronics In CMOS Processes - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include in an optoelectronic transceiver comprising photonic and electronic devices from two complementary metal-oxide semiconductor (CMOS) die with different silicon layer thicknesses for the photonic and electronic devices, the CMOS die bonded together by metal contacts: communicating optical signals and electronic signals to and from said optoelectronic transceiver utilizing a received continuous wave optical signal as a source signal. A first of the CMOS die includes the photonic devices and a second includes the electronic devices. Electrical signals may be communicated between electrical devices to the optical devices utilizing through-silicon vias coupled to the metal contacts. The metal contacts may include back-end metals from a CMOS process. The electronic and photonic devices may be fabricated on SOI wafers, with the SOI wafers being diced to form the CMOS die. | 09-24-2015 |
Patent application number | Description | Published |
20090250402 | REPLACEABLE FILTER ELEMENTS INCLUDING PLURAL FILTER MEDIA AND RELATED FILTRATION SYSTEMS, TECHNIQUES AND METHODS - One embodiment is a filter element including an outer filter media and an inner filter media. The outer filter media is operable to remove particulates present in a flow of fluid and/or coalesce water contained in the flow of fluid. The inner filter media is operable to remove particulates from the flow of fluid, separate water form the flow of fluid, and remove particulates from the flow of fluid. Other embodiments include unique apparatus, devices, systems, and methods relating to fuel filters and filtration. Further embodiments, forms, objects, features, advantages, aspects, and benefits of the present application shall become apparent from the detailed description and figures included herewith. | 10-08-2009 |
20100101993 | FILTER CARTRIDGE HAVING A FILTER WITHIN A FILTER, AND AN ENDPLATE SEALING STRUCTURE ON AN OUTER FILTER ELEMENT - A filter within a filter cartridge design is described that includes a sealing structure on an endplate of an outer filter element. Generally, the sealing structure includes an annular flange on the endplate that can directly seal against an interior surface of a housing when the filter cartridge is assembled for use. During filtration, the annular flange prevents a working fluid from bypassing the outer filter element. The sealing flange can seal with the housing in a press fit engagement. | 04-29-2010 |
20100294707 | MULTI-STAGE FILTER CARTRIDGE WITH SNAP FIT FILTERS - A filter cartridge is described that is designed to accommodate multi-stage filtration, for example dual stage filtration. A filter cartridge includes an outer filter with an endplate and an inner filter arranged within the central axis of the outer filter and that includes an endplate. The endplate of the outer filter includes an outer portion and an inner portion substantially surrounded by the outer portion. The inner portion is axially positioned relative to the outer portion and distal to the inner and outer filters relative to the outer portion. The inner portion includes an upwardly extending flange. The endplate of the inner filter includes a downwardly extending flange. The endplates of the outer and inner filters are arranged in a snap fit connection through engagement of the upwardly extending and the downwardly extending flanges. The endplate structure can provide a filter cartridge with filters of generally equal lengths. | 11-25-2010 |
20100294712 | MULTI-STAGE FILTER CARTRIDGE WITH POLYURETHANE ENDCAPS - A filter cartridge is described that is designed to accommodate for example dual stage filtration. The filter cartridge has an endplate structure formed of a heat cured material, such as polyurethane, where at least one of the top end and the bottom end of the outer filter and the inner filter are embedded within the heat cured material. The heat cured material can provide an endplate structure that is convenient for manufacture and that has one or more sealing surfaces to seal with a housing that the filter cartridge is assembled with. For example, the heat cured material of the endplate can seal non-filtered fluid from filtered fluid that has passed through each of the filtration stages available in the cartridge. | 11-25-2010 |
20130087497 | FILTER CARTRIDGE HAVING A FILTER WITHIN A FILTER, AND AN ENDPLATE SEALING STRUCTURE ON AN OUTER FILTER ELEMENT - A filter within a filter cartridge design is described that includes a sealing structure on an endplate of an outer filter element. Generally, the sealing structure includes an annular flange on the endplate that can directly seal against an interior surface of a housing when the filter cartridge is assembled for use. During filtration, the annular flange prevents a working fluid from bypassing the outer filter element. The sealing flange can seal with the housing in a press fit engagement. | 04-11-2013 |