52nd week of 2008 patent applcation highlights part 65 |
Patent application number | Title | Published |
20080320198 | USB DEVICE COMMUNICATION APPARATUS, SYSTEMS, AND METHODS - Methods, systems and apparatus may operate to send and receive universal serial bus (USB) control endpoint standard device requests with embedded functional sub-requests. From the USB device perspective, such operations may comprise receiving a control endpoint standard device request from a host at the USB device, decoding the functional sub-request forming a first portion of the control endpoint standard device request, decoding data forming a second portion of the control endpoint standard device request, and executing the functional sub-request by the USB device. Other methods, systems, and apparatus are disclosed. | 2008-12-25 |
20080320199 | MEMORY AND CONTROL APPARATUS FOR DISPLAY DEVICE, AND MEMORY THEREFOR - A memory and control apparatus and a memory for a display device are provided. The memory and control apparatus includes a memory, a sense-latch circuit, and a timing and memory controlling apparatus. The memory is used for storing data. The memory has a display data bus and a general data bus. The sense-latch circuit is used for sensing and latching the data on the display data bus. The timing and memory controlling apparatus is used for controlling the memory, so as to make the display data represented on the display data bus, and to make the sense-latch circuit outputting the data on the display data bus. When the display device intends to store the data in the memory, the data on the general data bus is stored to the memory. | 2008-12-25 |
20080320200 | LED LIGHT DONGLE COMMUNICATION SYSTEM - A Universal Serial Bus (USB) dongle may include an optical transceiver having a USB inter face for engagement to an electronic device such as a laptop computer or other USB-configured device. The USB dongle may include a converter or buffering, isolation, modulation or amplification circuitry. The USB dongle sends and receives data signals which may be carried upon an optical transmission as generated by an LED light source which in turn is in communication with a host device such as a network processor. The USB dongle may also include operational amplifiers (op-amps) and transistor amplifiers. | 2008-12-25 |
20080320201 | CENTRAL PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND INFORMATION PROCESSING SYSTEM - A plurality of system controllers | 2008-12-25 |
20080320202 | Physical Device (PHY) Support Of The USB2.0 Link Power Management Addendum Using A ULPI PHY Interface Standard - A protocol may enable support of the USB 2.0 LPM (Link Power Management) Addendum by a ULPI PHY (Universal Serial Bus Transceiver Macrocell Low-Pin Interface Physical Layer Device), facilitating transmitting the reserved PID (Physical Interface Device) token, used in the LPM Extended Transaction, through a ULPI bus. Bits [ | 2008-12-25 |
20080320203 | Memory Management in a Computing Device - A computing device incorporating memory such as mobile SDRAM, which is capable of conserving energy by being operated in a low-power self-refresh mode, is enabled to identify those regions of memory which are allocated but inactive. These regions are collected into specific banks of memory so as to create banks of memory containing only inactive data and which can then be placed in self-refresh. This reduces the power consumed by the computing device, and improves the energy efficiency of the device. | 2008-12-25 |
20080320204 | MEMORY SYSTEM AND METHOD WITH FLASH MEMORY DEVICE - A memory system is provided which includes a host, a flash memory device, and a dual port memory which exchanges data with the host and the flash memory device. The flash memory device utilizes a portion of the dual port memory as a working memory. | 2008-12-25 |
20080320205 | LONG-TERM DIGITAL DATA STORAGE - Embodiments are directed to recording digital data on an optically ablatable digital storage media. In one embodiment, a device configured to ablate portions of ablatable material on an optically ablatable digital storage media receives digital data that is to be recorded on a recording layer of an optically ablatable digital storage media. The recording layer is formed on a substrate with zero or more intervening layers between the recording layer and the substrate. The recording layer includes ablatable material capable of storing digital data. The device ablates the ablatable material in the recording layer according to a sequence defined by the received digital data such that the ablated portions correspond to data points of the received digital data. | 2008-12-25 |
20080320206 | Nonvolatile Memory Card and Configuration Conversion Adapter - A nonvolatile memory card, including interface parts for plural kinds of memory cards; interface controllers corresponding to the interface parts for corresponding memory cards; and a switch configured to select a single one of the interface controllers. | 2008-12-25 |
20080320207 | MULTI-LEVEL CELL (MLC) DUAL PERSONALITY EXTENDED FIBER OPTIC FLASH MEMORY DEVICE - A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data. | 2008-12-25 |
20080320208 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF - A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information. | 2008-12-25 |
20080320209 | High Performance and Endurance Non-volatile Memory Based Storage Systems - High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device. | 2008-12-25 |
20080320210 | Data management systems, methods and computer program products using a phase-change random access memory for selective data maintenance - A data management system includes a data processor configured to provide a file system module configured to store first data in a flash memory in block units and a filter layer module configured to receive second data from the file system module and to store the second data in a phase-change random access memory (PRAM) in sub-block units. The filter layer module may be configured to identify difference data in the second data received from the file system module by comparing the received second data and third data stored in the PRAM, and to write the identified difference data to the PRAM. The second data may include file metadata and the first data may include data other than file metadata. The sub-block units may be byte units. | 2008-12-25 |
20080320211 | NONVOLATILE MEMORY CONTROL DEVICE, NONVOLATILE MEMORY CONTROL METHOD, AND STORAGE DEVICE - According to an embodiment of the present invention is to increase the number of arbitrarily available physical blocks in a nonvolatile memory device. The device comprises a file system control section which analyzes a file allocation table (FAT) to identify an unused logical block, a logical/physical block address conversion table management section which uses a table of a logical/physical block address conversion table information section to obtain a first physical block corresponding to the unused logical block and releases the association between the first physical block and the unused logical block, and a physical block address information management section which registers the first physical block in a physical block address information section as an arbitrarily available second physical block. | 2008-12-25 |
20080320212 | CONTROL DEVICE AND CONTROL METHOD OF NONVOLATILE MEMORY AND STORAGE DEVICE - According to one embodiment, the control device according to an embodiment of the present invention, facilitates and speeds up averaging processing of the number of erases of a physical block (exchange processing of a physical block) of a nonvolatile memory. The device includes a file system control section that analyzes a file system of a nonvolatile memory and identifies a logical block of a read-only file, a logical/physical block address conversion table management section that obtains a first physical block corresponded to the logical block, and a physical block information management section that selects a second physical block that can be optionally used. Further, the device includes a physical block information modification section that moves data of the first physical block to the second physical block. | 2008-12-25 |
20080320213 | CONTROL DEVICE OF NONVOLATILE MEMORY AND CONTROL METHOD THEREOF, AND STORAGE DEVICE - According to one embodiment, the overall information processing time can be shortened. There are provided (1) a logical/physical block address conversion table information section that associates a logical block address of a logical address space with a physical block address of a nonvolatile memory device, (2) a physical block use state management section and a physical block erase count management section to read out erase count information from a physical block of which the logical block address and the physical block address are not associated, and a physical block that satisfies a predetermined condition set related to the erase count information is selected as a selected physical block, and (3) a logical/physical block address conversion table management section that registers a physical block address of the selected physical block in the logical/physical block address conversion table. | 2008-12-25 |
20080320214 | Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices - A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device. | 2008-12-25 |
20080320215 | Semiconductor memory device and method for operating semiconductor memory device - A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section, the memory array section and the interface section being sealed in a package. The interface section includes a plurality of interface modules configured to correspond to a plurality of memory types on a one-to-one basis, and a clock generation section configured to generate a plurality of clock signals based on a system clock signal supplied by the external memory controller. The generated clock signals are used by the plurality of interface modules. The interface section further includes a mode interpretation section configured to interpret an input mode designation signal as indicative of one of the memory types in order to output a mode signal denoting the interpreted memory type. | 2008-12-25 |
20080320216 | Translation Lookaside Buffer and Related Method and Program Product Utilized For Virtual Addresses - A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM. | 2008-12-25 |
20080320217 | Executing I/O Requests For A Disk Drive - Executing I/O requests for a disk drive including receiving, by a device driver from a volume manager, a plurality of I/O requests; retrieving, from non-volatile memory by the device driver, information describing access times for storage locations on the disk drive; and executing, by the device driver, the I/O requests in a sequence, including identifying, in dependence upon the information describing access times for storage locations on the disk drive, the sequence for executing the I/O requests. | 2008-12-25 |
20080320218 | Disk array apparatus and control method for disk array apparatus - Resources of a storage apparatus are utilized effectively by increasing and reducing a capacity of a differential LU used in a snapshot. In a disk array apparatus including a control processor which controls reading and writing of data with respect to a first logical volume which is generated using storage areas of a plural disk drives, performs control such that data in the past stored in the first logical volume is written in a second logical volume as differential data for each generation, and manages the differential data, the control processor manages a pool management table, in which a logical volume usable as the second logical volume is registered, and a pool addition object management table, in which a logical volume which can be added to the second logical volume is registered, and moves the logical volume from the pool addition object management table to the pool management table to thereby increase a capacity of the second logical volume. | 2008-12-25 |
20080320219 | COMPUTER AND METHOD FOR CONFIGURING DATA BACKUP ENVIRONMENT USED BY PLURALITY OF ASSOCIATIVELY OPERATED APPLICATIONS - The present invention stores application management information indicating respective applications constituting a federated application environment, which is a group constituted by a plurality of associatively operated applications. By referencing this application management information, a plurality of applications constituting this federated application environment are specified. A plurality of first logical volumes allocated to the specified plurality of applications, and a plurality of second logical volumes constituting the backup targets for data stored in the plurality of first logical volumes, are assigned to the same volume group. | 2008-12-25 |
20080320220 | Storage system, data transfer method, and program - The present invention suggests a storage system capable of realizing highly reliable data back-up. | 2008-12-25 |
20080320221 | Storage system and storage control method comprising router and switch communication with RAID modules - A storage system comprises a router, which receives and transfers commands; a plurality of RAID modules; and a switch, which receives commands from the router and transmits the commands to any of the plurality of RAID modules. Each RAID module comprises a plurality of media drives, a RAID group is provided by the plurality of media drives. Each RAID module comprises an independent RAID group which does not extend into other RAID groups. In the storage system, the router performs transfer of commands without performing analysis of commands, and a processor within the RAID module performs command analysis. | 2008-12-25 |
20080320222 | Adaptive caching in broadcast networks - Adaptive caching techniques are described. In an implementation, a head end defines a plurality of cache periods having associated criteria. Request data for content is obtained and utilized to associate the content with the defined cache periods based on a comparison of the request data with the associated criteria. Then, the content is cached at the head end for the associated cache period. | 2008-12-25 |
20080320223 | Cache controller and cache control method - A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in from outside to be written to the cache memory, a second buffer unit that retains a data piece to be currently written to the cache memory, among pieces of the data retained in the first buffer unit, and a write controlling unit that controls writing of the data piece retained in the second buffer unit to the cache memory. | 2008-12-25 |
20080320224 | Multiprocessor system, processor, and cache control method - A multiprocessor system includes processors each having a primary cache and a secondary cache shared by the processors. The processors each include a read unit that reads data from the primary cache, a request unit that makes a write request when the data to be read is not stored in the primary cache, a measuring unit that measures an elapsed time since the write request is made, a receiving unit that receives a read command from an external device, a comparing unit that compares specific information for specifying data, for which the read command has been received, with specific information for specifying data, for which the write request has been made, and a controller that suspends reading of the data according to the read command, when pieces of specific information are the same, and the elapsed time measured is less than a predetermined time. | 2008-12-25 |
20080320225 | SYSTEMS AND METHODS FOR CACHING AND SERVING DYNAMIC CONTENT - A web server and a shared caching server are described for serving dynamic content to users of at least two different types, where the different types of users receive different versions of the dynamic content. A version of the dynamic content includes a validation header, such as an ETag, that stores information indicative of the currency of the dynamic content and information indicative of a user type for which the version of the dynamic content is intended. In response to a user request for the dynamic content, the shared caching server sends a validation request to the web server with the validation header information. The web server determines, based on the user type of the requestor and/or on the currency of the cached dynamic content whether to instruct the shared caching server to send the cached content or to send updated content for serving to the user. | 2008-12-25 |
20080320226 | Apparatus and Method for Improved Data Persistence within a Multi-node System - Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache. | 2008-12-25 |
20080320227 | Cache memory device and cache memory control method - A cache memory device that includes a cache which stores data and tag information specifying an address of stored data, includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection by the detection unit, a memory unit that stores an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search by the search unit, and a control unit that requests an external unit to replace data with a use of the address stored by the memory unit. | 2008-12-25 |
20080320228 | METHOD AND APPARATUS FOR EFFICIENT REPLACEMENT ALGORITHM FOR PRE-FETCHER ORIENTED DATA CACHE - Disclosed are a method and apparatus for replacing pre-fetched data in a pre-fetch cache. In one embodiment, each line of the pre-fetch cache will be accessed at most M times. A line accessed M times can be evicted from the cache without any performance loss. In this embodiment, a counter is added to each pre-fetch data line to track how many times it has been accessed. In another embodiment, a displacement bit is added to each pre-fetch data line, and when a defined portion of the data line is accessed, this bit is set to a given value, indicating that the line can be evicted. | 2008-12-25 |
20080320229 | PRE-FETCH CONTROL APPARATUS - A pre-fetch control apparatus is equipped with a next-line pre-fetch control apparatus | 2008-12-25 |
20080320230 | Avoiding Livelock Using A Cache Manager in Multiple Core Processors - Livelocks are prevented in multiple core processors by verifying that a data access request is still valid before sending messages to processor cores that may cause other data access requests to fail. A cache coherency manager receives data access requests from multiple processor cores. Upon receiving a data access request that may cause a livelock, the cache coherency manager first sends an intervention message back to the requesting processor core to confirm that this data access request will succeed. If the requesting processor core determines that the data access request is still valid, it directs the cache coherency manager to proceed with the data access request. The cache coherency manager may then send intervention messages to other processor cores to complete the data access request. If the requesting processor core determines that the data access request is invalid, it directs the cache coherency manager to abandon the data access request. | 2008-12-25 |
20080320231 | Avoiding Livelock Using Intervention Messages in Multiple Core Processors - Livelocks are prevented in multiple core processors by canceling data access requests upon determining that they conflict with other data access requests. A requesting processor core sends a data access request potentially causing livelock to a cache coherency manager. A cache coherency manager receives data access requests from multiple processor. The cache coherency manager sends intervention messages to all of the processor cores in response to all data access requests that may cause livelock. Upon receiving an intervention message from the cache coherency manager, the processor core determines if the intervention message corresponds with any of its own pending data access requests. If the intervention message is associated with a data access request conflicting with one of its own pending data access requests, the processor core responds to the invention message by directing the cache coherency manager to cancel its own conflicting pending data access request. | 2008-12-25 |
20080320232 | Preventing Writeback Race in Multiple Core Processors - A processor prevents writeback race condition errors by maintaining responsibility for data until the writeback request is confirmed by an intervention message from a cache coherency manager. If a request for the same data arrives before the intervention message, the processor core unit provides the requested data and cancels the pending writeback request. The cache coherency data associated with cache lines indicates whether a request for data has been received prior to the intervention message associated with the writeback request. The cache coherency data of a cache line has a value of “modified” when the writeback request is initiated. When the intervention message associated with the writeback request is received, the cache lines's cache coherency data is examined. A change in the cache coherency data from the value of “modified” indicates that the request for data has been received prior to the intervention and the writeback request should be cancelled. | 2008-12-25 |
20080320233 | Reduced Handling of Writeback Data - The complexity of the logic of the cache coherency manager unit is reduced by leveraging the data path for intervention messages and responses to carry data associated with writeback requests. A processor core unit sends a writeback request to the cache coherency manager unit. The request does not include the writeback data. Upon receiving an intervention message associated with the writeback request, the processor core unit provides an intervention message response to the cache coherency manager unit indicating that the writeback operation should not be cancelled. The intervention message response includes the writeback data. Because the cache coherency manager already requires a data path to handle data transfers between processor core units, little or no additional overhead needs to be added to the cache coherency manager to handle data associated with writeback request. | 2008-12-25 |
20080320234 | Information processing apparatus and data transfer method - One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manages the CPU and the main memory as well as controls a data transfer of at least one of the cache memory and the main memory by a memory access request, wherein each system controller including a snoop controller that selects a transfer source CPU from transfer source candidate CPUs each having cache memory including a data requested by the memory access request when the data is available in a plurality of cache memories. | 2008-12-25 |
20080320235 | Processor cache management with software input via an intermediary - Software assists a processor subsystem in making cache replacement decisions by providing an intermediary with information regarding how instructions and/or data of a working set are expected to be used and accessed by the software. The intermediary uses this information along with its knowledge of system requirements, policy and the cache configuration to determine cache usage and management hints for the working sets. The cache usage and management hints are passed by the intermediary to the processor subsystem. | 2008-12-25 |
20080320236 | System having cache snoop interface independent of system bus interface - A system includes processor units, caches, memory shared by the processor units, a system bus interface, and a cache snoop interfaces. Each processor unit has one of the caches. The system bus interface communicatively connects the processor units to the memory via at least the caches, and is a non-cache snoop system bus interface. The cache snoop interface communicatively connects the caches, and is independent of the system bus interface. Upon a given processor unit writing a new value to an address within the memory such that the new value and the address are cached within the cache of the given processor unit a write invalidation event is sent over the cache snoop interface to the caches of the processor units other than the given processor unit. This event invalidates the address as stored within any of the caches other than the cache of the given processor unit. | 2008-12-25 |
20080320237 | SYSTEM CONTROLLER AND CACHE CONTROL METHOD - A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communication time with the other system controllers. The number-of-steps adjustment absorbs the difference of the communication time in the results of the snoop for each scale of the multiprocessor system. When a retrial is determined by an address conflict or the like in the snoop processing, each of the system controllers resubmits the access to be retried to the snoop pipeline after waiting until no other access which may cause an address conflict precedes. The resubmission timing prevents infinite repetition of the retrial of the snoop processing in the system controllers. | 2008-12-25 |
20080320238 | Snoop control method and information processing apparatus - One aspect of the embodiments utilizes a system controller which has a broadcast transmitting and receiving unit that receives a memory access request from each of CPU and notifies to the other system controllers and a snoop control unit that judges when the memory access request from any of the CPUs for each of the cache memories in the CPU is received, whether object data conflicts with object data requested by a prior access request received earlier than the memory access request and whether the object data is present in any of the cache memories, selects the status of the cache memory of the CPU, notifies the other system controller of a snoop processing result in which the status selected and the cache memory are associated, and set a final status as the status of the system controller based on priority of each status of other system controllers. | 2008-12-25 |
20080320239 | Data storage system - A data storage system is provided. The data storage system includes a first storage module for storing a first data, a second storage module for storing a second data, a control module and a processing module. The control module generates a first control signal and a second control signal, and accesses the first data and the second data according to the first control signal and the second control signal. The processing module is coupled to the first storage module, the second storage module and the control module, and controls the first storage module and the second storage module to transmit the first data and the second data to the control module according to the first control signal and the second control signal respectively, wherein the processing module bypasses the second storage module when receiving the first control signal. | 2008-12-25 |
20080320240 | Method and arrangements for memory access - In one embodiment a multi-input, multi output memory system is disclosed. The system can include a plurality of single ported memory modules, an identifier module to provide an identify to each memory access requests of a plurality of memory access requests. The identity can include a port that receives the memory access request. The system can include a memory access controller coupled to the plurality of single ported memory modules that can control movement of the requests. | 2008-12-25 |
20080320241 | Data storage device performance optimization methods and apparatuses - Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests. Various embodiments may process asynchronous requests, including prioritized asynchronous requests, with the isochronous requests. | 2008-12-25 |
20080320242 | PHYSICAL MEMORY CAPPING FOR USE IN VIRTUALIZATION - A method of implementing virtualization involves an improved approach to resource management. A virtualizing subsystem is capable of creating separate environments that logically isolate applications from each other. Some of the separate environments share physical resources including physical memory. When a separate environment is configured, properties for the separate environment are defined. Configuring a separate environment may include specifying a physical memory usage cap for the separate environment. A global resource capping background service enforces physical memory caps on any separate environments that have specified physical memory caps. | 2008-12-25 |
20080320243 | MEMORY-SHARING SYSTEM DEVICE - A memory-sharing system device has a shared memory, divided into forward-direction and backward-direction memory areas; a first processor inputting transfer data in the forward direction, writing the data to the forward-direction memory area, reading transfer data in the backward direction from the backward-direction memory area and outputting the data; and a second processor for transferring data in the back-ward direction. The first or second processor sets memory release criteria for the forward-direction and backward-direction memory areas respectively, and, when the used memory area reaches the memory release criterion, performs memory release processing. The first or second processor monitors the forward-direction and the backward-direction data transfer speed, changes the memory release criterion depending on the data transfer speed. | 2008-12-25 |
20080320244 | Moving records between partitions - In an embodiment, data is partitioned into partitions, which are divided into levels. The levels are ordered by creation times of the levels. A request is received at a current partition, which includes a key that identifies a field in a record and a value for the key. A determination is made whether the value exists in the field in the current partition. If the determination is false, a message is sent from the current partition to a next-older partition, and the message instructs the next-older partition to move the record with the value from the next-older partition to the current partition. If the determination is true, the record with the value in the field is moved from the current partition to a next-newer partition if the next-newer partition sent the request, and the record is deleted from the current partition. | 2008-12-25 |
20080320245 | Method for writing data of an atomic transaction to a memory device - A method for writing data to a memory device is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The data of the atomic transaction is read from the first memory and written to a second memory in the memory device only if it is determined that all of the data of the atomic transaction was written to the first memory. | 2008-12-25 |
20080320246 | Methods and apparatus for compiling instructions for a data processor - Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed. | 2008-12-25 |
20080320247 | Processor and interface - A data processing apparatus comprises a processor constructed to operate under control of a sequence of program instructions selected from a predetermined instruction set; master circuitry to request access to storage locations of the processor; an interface circuit to provide an interface for an external apparatus to signal a request for access to the storage locations and an interface for the master circuitry to signal a request for access to the storage locations; and control to provide access between the storage locations and the interface circuit in response to the request only at predetermined points in execution of the stored program, the control being operable to fix periods of time for providing such access relative to the sequence of program instructions such that execution timing of the stored instructions is independent of whether a request is supplied to the interface. | 2008-12-25 |
20080320248 | Computer system architecture and operating method for the operating system thereof - In order to develop a mobile operating system for a computer, first the mobile operating system must be independent from the computer hardware device. Therefore, the present invention discloses a new computer system architecture which loads a Transient Resident Operating System (TROS) from an external device and provides a predefined hardware device driver to the operating system, and then the TROS can be stored into a portable memory storage device to be a Mobile Operating System (MOS). By applying the technique disclosed in the present invention, the TROS can work beyond the Intrinsic Operating System (IOS) of the computer without the mutual interference from each other, such that a computer environment with a Parasitic Operating System (POS) is created. | 2008-12-25 |
20080320249 | FULLY BUFFERED DIMM READ DATA SUBSTITUTION FOR WRITE ACKNOWLEDGEMENT - A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue. | 2008-12-25 |
20080320250 | WIRELESSLY CONFIGURABLE MEMORY DEVICE - A configurable memory includes an interface section, a plurality of memory modules, and an internal configuration section. The interface section includes a millimeter wave (MMW) transceiver and interfaces with one or more external components. Each the plurality of memory modules includes a memory MMW transceiver and a plurality of memory cells. The internal configuration section includes a memory management unit and a memory management MMW transceiver. The memory management unit is operable to determine configuration of at least some of the plurality of memory modules to form a memory block, identify an interface MMW transceiver to provide a wireless link to the memory block, and generate a configuration signal based on the determined configuration and the identified interface MMW transceiver. The memory management MMW transmits the MMW configuration signal to the identified interface MMW transceiver and the MMW transceivers of the memory modules. | 2008-12-25 |
20080320251 | METHOD AND SYSTEM FOR CENTRALIZED MEMORY MANAGEMENT IN WIRELESS TERMINAL DEVICES - Methods and systems for controlling centralized memory management in wireless terminal devices. Memory management scripts associated with a wireless application are stored in a registry accessible through a data network for on-demand download and execution. A memory management kernel in each terminal device monitors a memory utilization of the terminal device. Based on the memory utilization, the memory management kernel interacts with an application gateway hosting the terminal device to download and execute one or more of the memory management scripts. | 2008-12-25 |
20080320252 | OPTIMIZED AND ROBUST IN-PLACE DATA TRANSFORMATION - In-place data transformations are performed on file data by moving data blocks from a source file into a temporary file and then from the temporary file into a destination file each time in a back to front fashion enabling truncation of the source file while the temporary file is being expanded and written into. Similar read, write, and truncate operations are performed between the temporary and destination files as well resulting in optimized use of available disk and/or memory space. An initial log file with information such as source file name, size, transformation type and direction is generated for recovery from a mid-transaction interruption. Based on a state (truncation, data content) of the temporary and source files, a status of data transfer prior to interruption is determined and remaining data transferred. | 2008-12-25 |
20080320253 | Memory device with circuitry for writing data of an atomic transaction - A memory device with circuitry for writing data of an atomic transaction is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The data of the atomic transaction is read from the first memory and written to a second memory in the memory device only if it is determined that all of the data of the atomic transaction was written to the first memory. | 2008-12-25 |
20080320254 | VARIOUS METHODS AND APPARATUS TO SUPPORT TRANSACTIONS WHOSE DATA ADDRESS SEQUENCE WITHIN THAT TRANSACTION CROSSES AN INTERLEAVED CHANNEL ADDRESS BOUNDARY - A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel. | 2008-12-25 |
20080320255 | VARIOUS METHODS AND APPARATUS FOR CONFIGURABLE MAPPING OF ADDRESS REGIONS ONTO ONE OR MORE AGGREGATE TARGETS - An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable. | 2008-12-25 |
20080320256 | LRU control apparatus, LRU control method, and computer program product - To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data | 2008-12-25 |
20080320257 | Network message logging and archival - A method includes receiving a message to be logged. The message is written to a stream corresponding to an active archive, wherein the active archive comprises compressed messages. The message is also written to an active log without compression. | 2008-12-25 |
20080320258 | SNAPSHOT RESET METHOD AND APPARATUS - A method, device, and system for resetting snapshots are provided. The reset of a snapshot incorporates the traditional snapshot delete and snapshot create operations into a single operation. Additionally, a snapshot created under the reset operation may receive an array partition from a snapshot being deleted under the same snapshot reset operation thereby retaining its identifying characteristics. | 2008-12-25 |
20080320259 | Method for Providing Fault Tolerance to Multiple Servers - A method for providing fault tolerance to multiple computer servers is disclosed. Basically, t backup computer servers are utilized to back up data from multiple active computer servers such that up to t faults can be tolerated. Data from the active computer servers are categorized under their respective data structure accordingly. In response to any access to data within one or more of the active computer servers, backup operations are performed on the accessed data in the t backup computer servers according to their data structures such that data with similar data structures are grouped under their respective fusible data structure within the t backup computer servers. | 2008-12-25 |
20080320260 | Data Synchronization of Multiple Remote Storage After Remote Copy suspension - A method and apparatus are provided for enhancing the performance of storage systems to allow recovery after all types of suspensions in remote copy operations. Data is synchronized after an interruption in transfer between a first storage volume of a primary storage system and a first storage volume of a secondary storage system which also includes a second storage volume. After the interruption is detected, at the primary storage system, a record is provided of the data written onto the first storage volume of the primary storage system, and at the secondary storage volume a record is provided of the data written onto the first storage volume of the secondary storage system. Then, at least a partial copy of the record of the data written onto the first storage volume of the primary storage system is written onto the second storage volume. Using the copy, the first storage volume of the secondary storage system is synchronized with the second storage volume of the secondary storage system. | 2008-12-25 |
20080320261 | Coordinated Storage Management Operations In Replication Environment - A method, system, computer system, and computer-readable medium for maintaining up-to-date, consistent copies of primary data without the need to replicate modified data when the data were modified as a result of an operation that is not an application-driven write operation captured during replication. Selected storage management operations are performed on the primary and secondary data stores at points in time when the data are the same to ensure that the data stored within the data stores remain consistent. These selected storage management operations include operations that produce modified data stored in the primary data store, where a portion of the modified data are not replicated to a secondary node. Other types of storage management operations are selected to be performed on both the primary and secondary data stores, where the operations do not directly change data in the primary data store, but may affect data stored in the primary data store. | 2008-12-25 |
20080320262 | READ/WRITE LOCK WITH REDUCED READER LOCK SAMPLING OVERHEAD IN ABSENCE OF WRITER LOCK ACQUISITION - An improved reader-writer locking for synchronizing access to shared data. When writing the shared data, a writer flag is set and a lock is acquired on the shared data. The shared data may be accessed following the expiration of a grace period and a determination that there are no data readers accessing the shared data. When reading the shared data, the writer flag is tested that indicates whether a data writer is attempting to access the shared data. If the writer flag is not set, the shared data is accessed using a relatively fast read mechanism. If the writer flag is set, the shared data is accessed using a relatively slow read mechanism. | 2008-12-25 |
20080320263 | METHOD, SYSTEM, AND APPARATUS FOR ENCRYPTING, INTEGRITY, AND ANTI-REPLAY PROTECTING DATA IN NON-VOLATILE MEMORY IN A FAULT TOLERANT MANNER - According to some embodiments, a method for providing encryption, integrity, and anti-replay protection of data in a fault tolerant manner is disclosed. A data blob and an anti-replay table blob are copied to a temporary storage region in a non-volatile memory. In an atomic operation, a status indicator is set and a monotonic counter is incremented after the data blob and the anti-replay table blob are copied to the temporary storage region. If a fault occurs while the status indicator is set, the data blob and the anti-replay table blob may be recovered from the temporary storage region. | 2008-12-25 |
20080320264 | CHIP CARD PROTECTED AGAINST COPYING AND METHOD FOR PRODUCTION THEREOF - A chip card is protected against copying by having a data memory for storage of data that are protected, at least in a sub-region of the data memory, against alteration by users or attackers outside of a privileged group. Members of this group can write an individual identifier for this chip card into this protected memory region once, and can write a digital signature of this identifier to an arbitrary memory region of the data memory. The digital signature can be generated with the use of a secret key for which an associated public key exists with which it can be checked whether the digital signature was generated from the individual identifier with the use of a secret key. | 2008-12-25 |
20080320265 | SYSTEM FOR PROVIDING A SLOW COMMAND DECODE OVER AN UNTRAINED HIGH-SPEED INTERFACE - A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates slow commands and transmits the slow commands to the memory interface device via the untrained high-speed interface. The slow commands operate at a first data rate that is slower than a second data rate utilized by the high-speed interface after it has been trained. The memory interface device receives the slow commands via the untrained high-speed interface, decodes the slow commands, and executes the slow commands. | 2008-12-25 |
20080320266 | Allocating Disk Space On A Disk Drive - Allocating disk space on a disk drive, the disk drive controlled by a device driver and a volume manager, including receiving in the volume manager a request to allocate disk space for semi-sequential data access of structured data; retrieving, from non-volatile memory by the volume manager, information describing access times for storage locations on the disk drive; and allocating, by the volume manager in dependence upon the retrieved information, disk space for the structured data. | 2008-12-25 |
20080320267 | Memory Element, Data Processing System, Method for Setting Operating Parameters of a Memory and Computer Program - A memory element includes a memory which is operable according to operating parameters from at least two sets of operating parameter values and an operating parameter control which is implemented to receive operating state information and to select a set of operating parameter values for the operation of the memory based on the operating state information. | 2008-12-25 |
20080320268 | INTERCONNECT IMPLEMENTING INTERNAL CONTROLS - In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target. | 2008-12-25 |
20080320269 | METHOD AND APPARATUS FOR RANKING OF TARGET SERVER PARTITIONS FOR VIRTUAL SERVER MOBILITY OPERATIONS - A computer implemented method, data processing system, and computer program product for automated ranking of target server partitions based on current workload partition performance state. When a violation of a stack tier policy for the virtualized process collection in a source logical partition is detected, the stack tier comprising the virtualized process collection is examined to determine a scalability of the stack tier. A set of logical partitions are examined to identify target logical partitions for the migration event, wherein the target logical partitions are compatible for migrating the virtualized process collection based on the scalability of the stack tier. A performance state of the virtualized process collection is analyzed, and the target logical partitions for selection in the migration event are ranked based on the performance states of the virtualized process collection and the stack tier policy. | 2008-12-25 |
20080320270 | Data read-and-write controlling device - In a data read-and-write controlling device, without waiting for confirmation that data is written in a RAM, data is written in a WER and an ADR, and at the same time, address information of the data is written in the RAM write-information table. That is, the data read-and-write controlling device associates an address retained at a data register of a write controlling unit with the value (a write request is present=“1”) of a write request that makes a request for writing data in the RAM, the value being retained in a write request register, and then causes the result to be stored in the RAM write-information table as the address information. | 2008-12-25 |
20080320271 | Hashing and Serial Decoding Techniques - A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software. | 2008-12-25 |
20080320272 | PARTITION PRIORITY CONTROLLING SYSTEM AND METHOD - A partition priority controlling apparatus includes a partition ID identifying unit, a partition ID match detecting unit for detecting whether or not a partition to which one of a plurality of system board modules belongs matches partitions to which the other system board modules respectively belong for at least one combination of the system board modules, and an inter-crossbar-unit conflict partition detecting unit for detecting a combination of partitions, which make a conflict between two of a plurality of crossbar units, for at least one combination of the two crossbar units on the basis of the determination result of the partition ID identifying unit, and the detection result of the partition ID match detecting unit. | 2008-12-25 |
20080320273 | Interconnections in Simd Processor Architectures - A single instruction multiple data (SIMD) processor ( | 2008-12-25 |
20080320274 | Age matrix for queue dispatch order - An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector. | 2008-12-25 |
20080320275 | Concurrent exception handling - Various technologies and techniques are disclosed for providing concurrent exception handling. Exceptions that occur in concurrent workers are caught. The caught exceptions are then forwarded from the concurrent workers to a coordination worker. The caught exceptions are finally aggregated into an aggregation structure, such as an aggregate exception object. This aggregation structure is rethrown and the individual caught exceptions may then be handled at a proper time. | 2008-12-25 |
20080320276 | Digital Computing Device with Parallel Processing - A digital processing device comprising a plurality of parallel processing units each coupled in parallel with one another. Each of the plurality of parallel processing units comprises at least one data memory storage unit; at least one input register coupled to the at least one data memory storage unit; and an arithmetic unit coupled to the at least one input register and configured to have synchronous command processing. A program execution control unit is coupled to each of the plurality of processing units and configured such that no processing clocks are required for synchronization of data transfer from the plurality of parallel processing units. At least one data bus is coupled to the at least one input register in each of the plurality of parallel processing units. | 2008-12-25 |
20080320277 | Thread Optimized Multiprocessor Architecture - In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein each of the processors comprises local caches dedicated to each of at least three specific registers in the processor. In another aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors, wherein each of the processors is operable to process an instruction set optimized for thread-level parallel processing and wherein each processor accesses the internal data bus of the computer memory on the chip and the internal data bus is the width of one row of the memory. | 2008-12-25 |
20080320278 | SYSTEM AND METHOD FOR EFFICIENT DATA TRANSMISSION IN A MULTI-PROCESSOR ENVIRONMENT - A system and method which provides for efficient data transmission between multiple microprocessors in a computer system is disclosed. A physical data path is divided into one or more data queues which may be virtual connection queues. The virtual connection queues are configured to adaptively split or merge based on traffic conditions therein. | 2008-12-25 |
20080320279 | MANAGEMENT OF A COMMUNICATION LINK EXTENDED TO ONE OR MORE SLAVE DEVICES - A master device for managing a communications link to slave devices (for example in the context of a Wireless USB cluster), wherein the master device is configured to facilitate avoidance of unnecessary waking of the slave devices. | 2008-12-25 |
20080320280 | MICROPROGRAMMED PROCESSOR HAVING MUTIPLE PROCESSOR CORES USING TIME-SHARED ACCESS TO A MICROPROGRAM CONTROL STORE - There is provided a novel microprogrammed processor ( | 2008-12-25 |
20080320281 | PROCESSING MODULE WITH MMW TRANSCEIVER INTERCONNECTION - A processing module includes a fetch and decode module, an instruction register, a data register, an execution module, and a MMW transceiver section. The fetch and decode module is operable to fetch and decode an instruction of a program and to identify data associated with the instruction. The execution module is operable to execute the instruction upon the data associated with the instruction. The MMW transceiver section is operable to wirelessly receive at least one of the instruction and the data associated with the instruction from memory. | 2008-12-25 |
20080320282 | Method And Systems For Providing Transaction Support For Executable Program Components - Methods and systems are described for providing transaction support for executable program components. In one embodiment, transaction information is associated with an instruction included in an executable addressable entity included in an executable program component generated from source code written in a programming language, wherein the transaction information is independent of the source code and the programming language. Further, an access to the instruction is detected for executing by a processor. A transaction operation to perform in association with the executing of the instruction is determined based on the transaction information associated with the instruction. The transaction operation is performed in association with the executing of the instruction, wherein the transaction operation is performed by a program component other than the executable program component including the executable addressable entity. | 2008-12-25 |
20080320283 | Programmable Data Processor for a Variable Length
Encoder/Decoder - A data processing circuit has a programmable processor (12 | 2008-12-25 |
20080320284 | VIRTUAL SERIAL-STREAM PROCESSOR - A virtual serial-stream processor or system consists of one or more data input ports, zero or more data output ports, zero or more virtual control ports, one or more virtual serial and stream processing cores, one or more virtual serial control processors, and memory. Virtual components are spread across multiple physical devices, multiple virtual processing cores implemented in one physical device, or some combination, as dictated by an application-specific design. | 2008-12-25 |
20080320285 | DISTRIBUTED DIGITAL SIGNAL PROCESSOR - A distributed digital signal processor (DSP) includes instruction memory, data memory, a multiply-accumulate module, an instruction MMW transceiver, a data MMW transceiver, and a multiply-accumulate transceiver. The multiply-accumulate module performs a function upon first and second data elements in accordance with a command of an instruction. The instruction MMW transceiver transmits a MMW instruction signal that includes at least a portion of the instruction. The data MMW transceiver transmits a MMW data signal in response to receiving the MMW instruction signal, wherein the MMW data signal includes the first and second data elements. The multiply-accumulate MMW transceiver recovers the first and second data elements from the MMW data signal and recovers a command corresponding to the function from the MMW instruction signal. | 2008-12-25 |
20080320286 | DYNAMIC OBJECT-LEVEL CODE TRANSLATION FOR IMPROVED PERFORMANCE OF A COMPUTER PROCESSOR - A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended. | 2008-12-25 |
20080320287 | Method and Device for Performing Switchover Operations in a Computer System Having at Least Two Processing Units - A method and device for performing switchover operations in a computer system having at least two processing units, a switchover device, and a comparison device, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, information being compared in the comparison mode. In the case of asynchronous operation of the at least two processing units in the comparison mode, a synchronization signal is applied to one interrupt input of at least one of the processing units. | 2008-12-25 |
20080320288 | BRANCH PREDICTION APPARATUS OF COMPUTER - One aspect of the embodiments utilizes a branch instruction predicting unit includes a history memory to store a branch address as history information, a selecting unit to select a storing place with reference to selection information for selecting either one of storing places when the branch address of the branch instruction is stored as the history information, In the case that there are a plurality of branch addresses to be stored at a storing place, when a first branch address is stored at a storing place, a second branch address is stored at a storing place in accordance with selection information updated by the updating unit. | 2008-12-25 |
20080320289 | STORAGE MEDIUM STORING CALCULATION PROCESSING VISUALIZATION PROGRAM, CALCULATION PROCESSING VISUALIZATION APPARATUS, AND CALCULATION PROCESSING VISUALIZATION METHOD - The execution status of pipeline processing is highly visualized by appropriately displaying processes forming loops in a simplified manner. A loop-information storage unit stores loop-defining information specifying the address of an instruction that causes a pipeline process forming a loop. An operation-information storage unit stores operation information that includes the address of an instruction input into a pipeline and information indicating the execution status of a pipeline process caused by the instruction. A loop determination unit determines whether each pipeline process indicated by the operation information forms a loop by referring to the loop-defining information. An output unit outputs visualization information indicating, in a visually comprehensible manner, the execution status of a pipeline process that has been determined to form a loop for a predetermined number of executions of the loop and the execution status of a pipeline process that has been determined to form no loop. | 2008-12-25 |
20080320290 | EXCEPTION-BASED TIMER CONTROL - A processing device includes a timer and an exception controller configured to provide an exception indicator representative of a first exception. The processing device further includes a timer controller configured to selectively enable/disable the timer in response to the exception and based on a characteristic of the exception. A method of utilizing the processing device includes receiving an exception and determining a characteristic of the exception. The method further includes, at a first time, selectively enabling/disabling the timer of the processing device based on the characteristic, and, at a second time subsequent to the first time, accessing a count value stored at the timer. The method further includes providing the count value for output from the processing device. | 2008-12-25 |
20080320291 | Concurrent exception handling - Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled by the one or more exception handler functions. If the respective exception is one of a kind handled by the exception handler functions, then run a particular handler of the exception handler functions and mark the respective exception as handled. Any unhandled exceptions are then processed appropriately. In one implementation, a collection of input data is processed to produce a collection of output results, with the exceptions being interleaved with other output results. In another implementation, a particular exception is selected that represents the multiple exceptions. The selected one particular exception is then thrown. | 2008-12-25 |
20080320292 | Self programming slave device controller - A self programming slave device controller is described which comprises interface circuitry and control circuitry. The interface circuitry is responsive to one or more configuration parameters to communicate data between the slave device controller and a slave device in accordance with the one or more configuration parameters. The control circuitry is responsive to one or more operating parameter signals indicative of one or more operating parameters influencing current performance characteristics of the slave device to set the one or more configuration parameters so as to control an access operation for accessing the slave device to accommodate the current performance characteristics of the slave device. In this way, an access operation can be conducted efficiently and reliably having regard to the current performance characteristics of the slave device. This makes it possible to automatically adjust configuration parameters used to control an access operation in dependence on changes to operating parameters of the slave device which may influence the performance characteristics. | 2008-12-25 |
20080320293 | CONFIGURABLE PROCESSING CORE - A configurable processing core includes a configuration module and a plurality of functional blocks, each including a millimeter wave (MMW) transceiver. The configuration module is operable to determine configuration of at least some of the plurality of functional blocks based on at least one instruction of an algorithm, generate a configuration signal in accordance with the determined configuration, and transmit the configuration signal to the at least some of the plurality of functional blocks via the MMW transceivers. The at least some of the plurality of functional blocks are operable to configure in accordance with the configuration signal to support execution of the at least one instruction. | 2008-12-25 |
20080320294 | USER SELECTABLE CONFIGURATION OPTIONS APPLICATION FOR INACCESSIBLE NONVOLATILE STORAGE AT BOOTSTRAP - Embodiments of the present invention address deficiencies of the art in respect to applying user configurable options during bootstrap and provide a novel and non-obvious method, system and computer program product for user selectable configuration options application for inaccessible nonvolatile storage at bootstrap. In one embodiment of the invention, a method for user selectable configuration options application for inaccessible nonvolatile storage at bootstrap can be provided. The method can include powering up a motherboard for a computer system and reading user selectable configuration options for the computing system from sticky bits prior to bootstrap for the motherboard. The method further can include applying the user selectable configuration options to the computing system. Finally, the method can include performing bootstrap for the motherboard subsequent to applying the user selectable configuration options. | 2008-12-25 |
20080320295 | METHOD AND APPARATUS FOR VIRTUALIZATION OF APPLIANCES - A method and apparatus for the virtualization of appliances provides an embedded operating system (OS) which is included in the system boot ROM of a personal computer. When the system boots, the OS is launched and looks for all available virtual appliances from, for example, the following places: local USB, flash card, e.g. SD, xD, CF, CDROM/DVD, or other storage media; local hard disk storage; and the Internet, e.g. an appliance server. The user selects an appliance to use from the OS, whereupon the appliance is loaded and launched. If the selected appliance is not on a local storage, then it is downloaded, e.g. over the Internet from an appliance server. The downloaded appliance can be cached in local storage media such that, the next time it is needed, it need not be downloaded from the appliance server. The user can also elect to boot an operating system from the hard disk, if an operating system and hard disk are installed, or to power-off the system. | 2008-12-25 |
20080320296 | METHODS AND SYSTEMS FOR SECURE REMOTE MOBILE PRINTING - Systems and methods for for secure, remote printing includes a mobile device (e.g., cell phone or PDA) establishing a secure communication connection with a mobile printer and a server, such a connection using one or more encryption protocols (e.g., SSL, TLS, etc.). The server encrypts the requested data and transmits it to the printer via the secure connection, whereon the printer decrypts and prints the data. The mobile device can, according to other aspects of the invention, logs operational performance characteristic of the printer, the server, and/or the communication connections therebetween. A media cartridge can be provided includes an enclosure having a substantially planar shape, wherein each of its length and width dimensions are greater than its height. An opening is disposed along a width-wise edge (e.g., a “front” of the enclosure), and one or more regions are also disposed on opposing length-wise edges (e.g., a “left side” and a “right side” of the enclosure). The regions permit a user to see and/or exert a force on sheet media (e.g., paper) contained within the enclosure. | 2008-12-25 |
20080320297 | METHOD AND SYSTEM FOR MONITORING ENCRYPTED DATA TRANSMISSIONS - A method for efficiently decrypting asymmetric SSL pre-master keys is divided into a key agent component that runs in user mode, and an SSL driver running in kernel mode. The key agent can take advantage of multiple threads for decoding keys in a multi-processor environment, while the SSL driver handles the task of symmetric decryption of the SSL encrypted data stream. The method is of advantage in applications such as firewalls with deep packet inspection in which all encrypted data traffic passing through the firewall must be decrypted for inspection. | 2008-12-25 |