51st week of 2015 patent applcation highlights part 52 |
Patent application number | Title | Published |
20150364273 | CIRCUIT BREAKER AND METHOD OF CONTROLLING THE SAME - The present invention relates to a circuit breaker and a method of controlling the same. More specifically, the present invention is to provide a circuit breaker capable of performing an interruption operation and an interruption monitoring function through an integrated control contact for transmitting a control signal, in order to solve the conventional problem, i.e., a structural problem due to separation of control contacts, and a malfunction of a monitoring function when an interlock is set, and a method of controlling the circuit breaker. With such a configuration, the circuit breaker can have a simplified structure, and can be designed and controlled more easily and simply. | 2015-12-17 |
20150364274 | A REMOTE CONTROLLABLE SWITCH OPERATING DEVICE - A Remote Controllable Switch Operating device Many household and workplace electrical appliances must be connected to a power supply. They are turned on and off by electrically connecting them to and disconnecting them from a power supply. Typically this is done manually by a user operating a switch. The present invention is directed toward a wirelessly operable electrical light switch ( | 2015-12-17 |
20150364275 | BACKLIGHT MODULE AND LIGHTING KEYBOARD - A backlight module is used in a lighting keyboard. The backlight module includes a light guiding plate and a masking. The masking is disposed on the light guiding plate. The masking includes a support layer, a cover layer and a reflective layer. The support layer includes a first surface and a second surface opposite to the first surface. The cover layer is disposed on the first surface. The cover layer includes a first opening. The reflective layer is disposed on the second surface and faces the light guiding plate for reflecting light emitted from the light guiding plate, so as to enhance lighting efficiency on the first opening. The reflective layer includes a second opening. A shape and a position of the second opening are respectively corresponding to a shape and a position of the first opening. | 2015-12-17 |
20150364276 | OPTICALLY TRANSMISSIVE KEY SWITCH MECHANISM FOR DISPLAY-CAPABLE KEYBOARDS, KEYPADS, OR OTHER USER INPUT DEVICES - Key switch mechanisms are typically used for mediating user input to computing devices. A key switch mechanism provides immediate tactile feedback to a user upon user-actuation thereof. Unlike touchscreen interfaces, existing key switch mechanisms of conventional keyboards do not provide a user with a dynamically changeable interface. Described is a key switch mechanism that comprises a circuit module, a key cap and a linkage mechanism for guiding travel of the key cap substantially along a travel axis. The linkage mechanism comprises a positioning board and a main link pivotably inter-coupling the positioning board and the key cap. The main link substantially impedes tilt of the key cap away from the travel axis during travel of the key cap therealong from a released position, whereat the key cap is biased, to a depressed position whereat a control signal is generated. | 2015-12-17 |
20150364277 | ELECTRICAL ENCLOSURE AND GUARD ASSEMBLY THEREFOR - A guard assembly is for an electrical enclosure. The electrical enclosure includes a housing, an electrical switching apparatus, and a handle. The guard assembly includes: a shaft including a first end and a second end, the first end being structured to be coupled to the handle, the second end being structured to be coupled to the electrical switching apparatus; and a sleeve assembly structured to move between a retracted position and an extended position, the sleeve assembly including a sleeve member, the sleeve member including: a base located proximate the first end of the shaft, and a cover portion extending from the base toward the second end of the shaft, the shaft extending at least partially through the cover portion. Responsive to the sleeve assembly moving from the retracted position toward the extended position, the sleeve member moves away from the second end of the shaft. | 2015-12-17 |
20150364278 | Remote Control Device for Toilet Device - According to one embodiment, a remote control device for a toilet device includes an operation button and a power generator. The operation button is capable of a push operation and is configured to operate an equipment in response to the push operation. The power generator is configured to generate a power by being pressed in response to the push operation. A direction of the pressing is parallel to a wall surface on which the remote control device is placed. | 2015-12-17 |
20150364279 | ELECTRONIC DEVICE CONTROL BUTTON OF VEHICLE - An electronic device control button of a vehicle includes: i) a jog-shuttle configured to control an electronic device including a navigation device for the vehicle; ii) a base part configured to rotatably support the jog-shuttle and slidably move in upward and downward directions from a reference position on a center fascia panel; iii) a return spring provided on the center fascia panel, configured to limit movement of the jog-shuttle, and to recover the jog-shuttle to the reference position; and iv) a terminal part provided at the jog-shuttle and configured to make contact with or be separated from a slot of a circuit board to apply and block different electrical signals to and from the electronic device. | 2015-12-17 |
20150364280 | Switching Method and Switching Device - A switching device has a first contact side with a first nominal current contact piece and a first electric arc contact piece, and a second contact side with a second electric arc contact piece and a second nominal current contact piece. In order to generate a relative movement between the first and second contact sides, the first electric arc contact piece and the first nominal current contact piece as well as the second electric arc contact piece and the second nominal current contact piece are driven. For switching, the first contact piece is moved by a movement profile and the first nominal current contact piece is moved by a movement profile that differs from the movement profile of the first electric arc contact piece. A movement profile of the second electric arc contact piece and the second nominal current contact piece deviate from each other. | 2015-12-17 |
20150364281 | OVERVOLTAGE PROTECTION ELEMENT - An overvoltage protection element with a housing, an overvoltage-limiting component arranged in the housing, and with two connection elements for electrically connecting the overvoltage protection element to the current or signal path to be protected, wherein, normally, the connection elements are each in electrically conductive contact with a pole of the overvoltage-limiting component. Reliable and effective electrical connection in the normal state and reliable isolation of a defective overvoltage-limiting component are ensured by the fact that a thermally expandable material is arranged within the housing in a way that, in the event of thermal overloading of the overvoltage-limiting component, the position of the overvoltage-limiting component is changed by expansion of the thermally expandable material relative to the position of the connection elements in a way that causes at least one pole of the overvoltage-limiting component to be out of electrically conductive contact with the corresponding connection element. | 2015-12-17 |
20150364282 | THERMAL SWITCH, METHOD OF MANUFACTURING THE SAME AND DEVICE FOR ADJUSTING HEIGHT OF MOVABLE CONTACT - A thermal switch includes a thermally responsive plate assembly including a metal support deforming from an initial shape before a header plate assembly is secured to a housing assembly, with a result that a position of a movable contact in the housing assembly is adjusted so as to be within a predetermined height range relative to an open end of a housing. A contact pressure of switching contacts after the assembling is produced by the height adjustment, and subsequently, a neighborhood of a part of the housing to which part the thermally responsive plate assembly is secured is deformed, so that an operating temperature is calibratable. | 2015-12-17 |
20150364283 | OPERATION INDICATING LAMP-EQUIPPED ELECTROMAGNETIC RELAY - An operation indicating lamp-equipped electromagnetic relay has an excitation coil, a contract member that has electromagnetic interaction with the excitation coil to open and close a circuit, a housing in which the excitation coil and the contact member are disposed, and having a display surface arranged in a top surface thereof, a light source having an optical axis that is oriented toward a direction other than the display surface in order to display an operating situation of the electromagnetic relay, and being disposed in the housing so as to emit light according to a situation of power supplied to the excitation coil, a reflecting member disposed in the housing so as to reflect the light emitted from the light source toward the display surface, and a diffusion structure that diffuses the light reflected by the reflecting member formed in the display surface. | 2015-12-17 |
20150364284 | TEMPERATURE-DEPENDENT SWITCH COMPRISING A SPACER RING - A temperature-dependent switch has a temperature-dependent switching mechanism arranged in a housing having an upper part and a lower part. A first contact area is arranged on an inner side of the upper part and a second contact area is arranged internally in the lower part, the switching mechanism producing, in temperature-dependent fashion, an electrically conductive connection between the first and second contact areas. The switching mechanism comprises a current transfer element, a bimetallic snap-action disc and a movable contact area. The moveable contact area is connected to the current transfer element and interacts with the first contact area, the bimetallic snap-action disc lifting off the movable contact area from the first contact area depending on the temperature of the bimetallic snap-action disc. A resistance ring is arranged between the upper part and the lower part and is electrically in series with the current transfer element between the first and second contact areas when the switch is in its closed state. | 2015-12-17 |
20150364285 | Dead Tank Circuit Breaker With Surge Arrester Connected Across The Bushing Tops Of Each Pole - Surge arrester structure is provided for a dead tank circuit breaker. The circuit breaker has a pole assembly with a first electrical terminal in a first bushing, and a second electrical terminal in a second bushing. The first terminal is electrically connected to a stationary contact and the second terminal is electrically connected to a movable contact. The surge arrester structure includes a surge arrester having first and second opposing ends. A first conductor structure electrically and mechanically connects the first end of the surge arrester with an end of the first terminal. A second conductor structure electrically and mechanically connects the second end of the surge arrester with an end of the second terminal. The surge arrester is electrically connected parallel with respect to the stationary and movable contacts so that the surge arrester can limit transient over voltages occurring across the contacts when the contacts are open. | 2015-12-17 |
20150364286 | COMPLEX PROTECTION DEVICE - Provided is a complex protection device which can protect a circuit and circuit elements installed at the circuit against overcurrent and overvoltage. Heat is generated from thin film type printed resistors installed at opposite sides of a fusible element or directly beneath the fusible element and, as such, it is possible to improve thermal characteristics of the product, to design an ultraminiature product, and to simplify manufacture processes. | 2015-12-17 |
20150364287 | METHOD OF MAKING FIELD EMITTER - A method of making a field emitter includes following steps. A carbon nanotube layer is provided, and the carbon nanotube layer includes a first surface and a second surface opposite to each other. A carbon nanotube composite layer is formed via electroplating a first metal layer on the first surface and electroplating a second metal layer on the second surface. A first carbon nanotube layer and a second carbon nanotube layer is formed by separating apart the carbon nanotube composite layer, wherein a fracture surface is formed in the carbon nanotube composite layer, a number of first carbon nanotubes in the first carbon nanotube layer are exposed from the fracture surface, and a number of second carbon nanotubes in the second carbon nanotube layer are exposed from the fracture surface. | 2015-12-17 |
20150364288 | RADIATION GENERATING APPARATUS - A radiation generating apparatus includes a target base, a target, an electronic beam generating device, a tube, a tank, and a porous structure. The target is disposed on the target base. The electronic beam generating device is adapted to generate an electronic beam, and the electronic beam is emitted to the target to generate a radiation. The tube accommodates the target and the electronic beam generating device. The tank is connected to the target base and accommodates the tube. The porous structure is roundly disposed between the tank and the tube and contacts an inner wall of the tank and an outer wall of the tube. A cooling fluid flows through the porous structure to dissipate the heat of the porous structure. | 2015-12-17 |
20150364289 | RADIATION GENERATING APPARATUS - A radiation generating apparatus includes a target base, a target, an electronic beam generating device, a tube, a tank, and a porous structure. The target is disposed on the target base. The electronic beam generating device is adapted to generate an electronic beam, and the electronic beam is emitted to the target to generate a radiation. The tube accommodates the target and the electronic beam generating device. The tank is connected to the target base and is accommodated by the tube. The porous structure is disposed in the tank and contacts the target base. A cooling fluid flows through the porous structure to dissipate the heat of the porous structure. | 2015-12-17 |
20150364290 | CHARGED PARTICLE BEAM APPLICATION DEVICE - The charged particle beam application device is provided with a charged particle source and an objective lens that converges charged particle beam generated by the charged particle source onto a sample. In this case, the charged particle beam application device is further provided with an aberration generating element installed between the charged particle beam source and the objective lens, a tilt-use deflector installed between the aberration generating element and the objective lens, a deflection aberration control unit for controlling the aberration generating element, a first electromagnetic field superposing multipole installed between the aberration generating element and the objective lens, and an electromagnetic field superposing multipole control unit for controlling the first electromagnetic field superposing multipole. The aberration generating element has such a function that when the charged particle beam is tilted relative to the sample by the tilt-use deflector, a plurality of resulting aberrations are cancelled with one another. Moreover, the first electromagnetic field superposing multipole has a function to change the orbit of a charged particle beam having energy different from that of the main charged particle beam in the charged particle beam. | 2015-12-17 |
20150364291 | LITHOGRAPHY APPARATUS, AND METHOD OF MANUFACTURING ARTICLE - The present invention provides a lithography apparatus which forms a pattern by sequentially irradiating a first region and a second region on a substrate with a beam, the apparatus including a beam detector configured to detect the beam, and a processor configured to obtain position information of the second region by giving a weight to first position information of the second region based on an output from the beam detector before irradiation of the first region with the beam, and giving a weight to second position information of the second region based on an output from the beam detector after the irradiation. | 2015-12-17 |
20150364292 | STAGE APPARATUS, LITHOGRAPHY APPARATUS, AND ARTICLES MANUFACTURING METHOD - A stage apparatus including: a magnet; a moving member configured to be supported so as to float by a magnetic force of the magnet and move in a first direction along a horizontal plane together with the magnet; and a fixed member having a magnetic material facing the magnet above the magnet in a movable area of the moving member, wherein side surfaces of the magnet in the first direction are covered by using a first magnetic field blocking surface of the moving member and a second magnetic field blocking surface of the fixed member. | 2015-12-17 |
20150364293 | METHOD OF MAKING TRANSMISSION ELECTRON MICROSCOPE MICRO-GRID - A method of making a transmission electron microscope micro-grid includes following steps. A carbon nanotube layer is provided, and the carbon nanotube layer includes a first surface and a second surface opposite to each other. A first metal layer is electroplated on the first surface and a second metal layer is electroplated on the second surface. A number of first through holes are formed by etching the first metal layer, and a number of second through holes are formed by etching the second metal layer, wherein the carbon nanotube layer is exposed through the number of first through holes and the number of second through holes. | 2015-12-17 |
20150364294 | TRANSMISSION ELECTRON MICROSCOPE MICRO-GRID - A transmission electron microscope micro-grid includes a carbon nanotube layer sandwiched between a first metal layer and a second metal layer. The carbon nanotube layer includes a first surface and a second surface opposite to each other, and the carbon nanotube layer comprises a number of carbon nanotubes. The first metal layer is attached on the first surface. The second metal layer is attached on the second surface. The first metal layer and the second metal layer are bonded with the carbon nanotube layer via a number of dangling bonds on the number of carbon nanotubes, the first metal layer defines a number of first through holes, the second metal layer defines a number of second through holes, and the carbon nanotube layer is exposed through the number of first through holes and the number of second through holes. | 2015-12-17 |
20150364295 | Identification of Trace Constituent Phases in Nuclear Power Plant Deposits Using Electron Backscatter Diffraction (EBSD) - The instant invention provides a method of identifying lead-bearing crystalline phases or compounds in deposits formed on surfaces, such as the heated surfaces of nuclear power plant systems. A deposit sample or specimen is obtained and examined to obtain an image, an area elemental composition spectrum, and an x-ray elemental map to identify a location containing a lead-bearing species of interest. Electron backscatter diffraction is then used to obtain a characteristic diffraction pattern from the location, which is compared to a library of known diffraction patterns to identify any lead-bearing crystalline phases or compounds present in the location. Finally, any potential phase or compound of the lead in the deposit sample is identified by comparing the elemental composition spectrum with the electron backscatter diffraction crystalline compound identification. | 2015-12-17 |
20150364296 | Composite Charged Particle Beam Detector, Charged Particle Beam Device, and Charged Particle Beam Detector - The present invention relates to modulating an irradiation condition of a charged particle beam at high speed and detecting a signal in synchronization with a modulation period for the purpose of extracting a signal arising from a certain charged particle beam when a sample is irradiated with a plurality of charged particle beams simultaneously or, for example, for the purpose of separating a secondary electron signal arising from ion beam irradiation and a secondary electron signal arising from electron beam irradiation in an FIB-SEM system. The present invention further relates to dispersing light emitted from two or more kinds of scintillators having different light emitting properties, detecting each signal strength, and processing a signal on the basis of a ratio of first signal strength when the sample is irradiated with a first charged particle beam alone to second signal strength when the sample is irradiated with a second charged particle beam alone, the ratio being set by a mechanism. The present invention enables extraction of only a signal arising from a desired charged particle beam even when the sample is irradiated with the plurality of charged particle beams simultaneously. The SEM observation can be performed in the middle of the FIB processing using the secondary electron in the FIB-SEM system, for example. | 2015-12-17 |
20150364297 | BEAM IRRADIATION APPARATUS AND BEAM IRRADIATION METHOD - Provided is a beam irradiation apparatus including: a beam scanner that is configured such that a charged particle beam is reciprocatively scanned in a scanning direction; a measurement device that is capable of measuring an angular component of charged particles incident into a region of a measurement target; and a data processor that calculates effective irradiation emittance of the charged particle beam using results measured by the measurement device. The measurement device measures a time dependent value for angular distribution of the charged particle beam. The data processor transforms time information included in the time dependent value for the angular distribution to position information and thus calculates the effective irradiation emittance. The effective irradiation emittance represents emittance of a virtual beam bundle, the virtual beam bundle being formed by summing portions of the charged particle beam which are incident into the region of the measurement target. | 2015-12-17 |
20150364298 | LITHOGRAPHY APPARATUS, AND METHOD OF MANUFACTURING ARTICLE - There is provided a lithography apparatus advantageous in a process on a substrate, on which patterning has been performed thereby, that an external apparatus performs (in a succeeding step). The apparatus includes a controller and a transmitter. The controller extracts log information to be transmitted to the external apparatus that performs a process on the substrate, on which the patterning has been performed, among log information associated with the patterning. The transmitter transmits the extracted log information to the external apparatus. | 2015-12-17 |
20150364299 | ION IMPLANTATION APPARATUS AND CONTROL METHOD FOR ION IMPLANTATION APPARATUS - Provided is an ion implantation apparatus including: a vacuum processing chamber in which an ion implantation process for a wafer is performed; one or more load lock chambers that are used for bringing the wafer into the vacuum processing chamber and taking out the wafer from the vacuum processing chamber; an intermediate conveyance chamber that is disposed to be adjacent to both the vacuum processing chamber and the load lock chamber; a load lock chamber-intermediate conveyance chamber communication mechanism including a gate valve capable of sealing a load lock chamber-intermediate conveyance chamber communication port; and an intermediate conveyance chamber-vacuum processing chamber communication mechanism including a movable shielding plate capable of shielding a part or the whole of the intermediate conveyance chamber-vacuum processing chamber communication port. | 2015-12-17 |
20150364300 | DETERMINING PRESENCE OF CONDUCTIVE FILM ON DIELECTRIC SURFACE OF REACTION CHAMBER - In one aspect, a plasma system includes a dielectric enclosure enclosing a portion of a reaction chamber, a conductive coil extending along a perimeter of the enclosure, and a generator for providing a first electrical signal to the coil to cause a plasma to be generated in the reaction chamber. The system additionally includes a probe located within the reaction chamber, a sensing device for sensing a second electrical signal generated in the probe via the plasma while the first electrical signal is provided to the coil, and a processing unit for determining a metric based on the sensed second electrical signal, the metric indicating a measure of deposition or removal of a conductive material on an inside surface of the enclosure. | 2015-12-17 |
20150364301 | ELECTRONIC DEVICE MANUFACTURING METHOD AND SPUTTERING METHOD - An electronic device manufacturing method includes a first step of moving a substrate holder close to a first shield member and locating a first projecting portion formed on the first shield member and having a ring shape and a second projecting portion having a ring shape and formed on a second shield member installed on the surface of the substrate holder at the outer peripheral portion of a substrate at a position to engage with each other in a noncontact state, a second step of, after the first step, sputtering a target while maintaining the first projecting portion and the second projecting portion at the position to engage with each other in the noncontact state, and a third step of, after the second step, setting the first shield member in an open state and sputtering the target to perform deposition on the substrate. | 2015-12-17 |
20150364302 | Optimizing Drag Field Voltages in a Collision Cell for Multiple Reaction Monitoring (MRM) Tandem Mass Spectrometry - A collision cell has a plurality of rod electrodes arranged in opposed pairs around an axial centerline and a plurality of drag vanes arranged in the interstitial spaces between the rod electrodes. Operating the collision cell includes, applying a rod offset voltage to the rod electrodes, and varying an offset voltage applied to the drag vanes to identify a vane offset voltage with a maximum intensity for the transition. The method further includes varying a drag field by adjusting the voltages applied to drag vane terminals in opposite directions to identify a drag field value with a cross talk below a cross talk threshold, varying the vane offset voltage by adjusting the voltages applied to the drag vane terminals to maximize the intensity of the transition while preserving the drag field, and operating the collision cell at the vane offset voltage and drag field to monitor the transition. | 2015-12-17 |
20150364303 | Methods of operating a fourier transform mass analyzer - A method is disclosed for operating a mass spectrometer having a Fourier Transform (FT) analyzer, such as an orbital electrostatic trap mass analyzer, to avoid peak coalescence and/or other phenomena arising from frequency-shifting caused by ion-ion interactions. Ions of a first group are mass analyzed, for example in a quadrupole ion trap analyzer, to generate a mass spectrum. The estimated frequency shift of the characteristic periodic motion in the FT analyzer is calculated for one or more ion species of interest based on the intensities of adjacent (closely m/z-spaced) ion species. If the estimated frequency shift(s) for the one or more ion species exceeds a threshold, then a target ion population for an FT analyzer scan is adjusted downwardly to a value that produces a shift of acceptable value. An analytical scan of a second ion group is performed at the adjusted target ion population. | 2015-12-17 |
20150364304 | METHODS FOR ACQUIRING AND EVALUATING MASS SPECTRA IN FOURIER TRANSFORM MASS SPECTROMETERS - The invention provides a method for acquiring a mass spectrum with a Fourier transform mass spectrometer, wherein analyte ions and additional reporter ions oscillate at mass specific frequencies in a measuring cell of the frequency mass spectrometer and interact by Coulomb forces; the image current signal induced by the reporter ion is measured; and mass signals of the analyte ions are determined from a sideband signal of the reporter ions in the frequency domain or from the instantaneous frequency of the reporter ions in the time domain. | 2015-12-17 |
20150364305 | DATA PROCESSING FOR MULTIPLEXED SPECTROMETRY - Multiplexed spectrometry, such as multiplexed ion mobility spectrometry (IMS), time-of-flight mass spectrometry (TOFMS), or hybrid IM-TOFMS, is carried out on a sample, and the resulting measurement data are deconvoluted. Noise may be removed from the measurement data prior to deconvolution. Alternatively or additionally, noise may be removed from the deconvoluted data. | 2015-12-17 |
20150364306 | CELLULAR PROBE DEVICE, SYSTEM AND ANALYSIS METHOD - A sampling probe, system and analysis method is disclosed. The sampling probe includes a tube having at least a first bore, a second bore, a first end, and a tapered second end; a first capillary partially disposed within the first bore, at least a portion of the first capillary extending from the first end of the tube; a second capillary partially disposed within the second bore, the second capillary having a portion with a free tapered end which extends from the first end of the tube; and wherein an end of the first capillary and an end of the second capillary converge at a junction in the tapered second end of the tube. | 2015-12-17 |
20150364307 | Systems and Methods for Single Cell Culture and Analysis by Microscopy and Maldi Mass Spectrometry - Systems and methods for single cell culture and analysis by microscopy and matrix assisted laser desorption ionization mass spectrometry are disclosed. The systems and methods isolate a plurality of cells in a plurality of wells such that a predetermined number of the plurality of wells contain one and only one cell. The plurality of wells allow for optical interrogation of the cells and subsequent matrix assisted laser desorption ionizing of molecules within the cells. | 2015-12-17 |
20150364308 | COLLISION CELL - A method of operating a gas-filled collision cell in a mass spectrometer is provided. The collision cell has a longitudinal axis. Ions are caused to enter the collision cell. A trapping field is generated within the collision cell so as to trap the ions within a trapping volume of the collision cell, the trapping volume being defined by the trapping field and extending along the longitudinal axis. Trapped ions are processed in the collision cell and a DC potential gradient is provided, using an electrode arrangement, resulting in a non-zero electric field at all points along the axial length of the trapping volume so as to cause processed ions to exit the collision cell. The electric field along the axial length of the trapping volume has a standard deviation that is no greater than its mean value. | 2015-12-17 |
20150364309 | RF Ion Guide with Axial Fields - RF ion guides are configured as an array of elongate electrodes arranged symmetrically about a central axis, to which RF voltages are applied. The RF electrodes include at least a portion of their length that is semi-transparent to electric fields. Auxiliary electrodes are then provided proximal to the RF electrodes distal to the ion guide axis, such that application of DC voltages to the auxiliary electrodes causes an auxiliary electric field to form between the auxiliary electrodes and the ion guide RF electrodes. A portion of this auxiliary electric field penetrates through the semi-transparent portions of the RF electrodes, such that the potentials within the ion guide are modified. The auxiliary electrode structures and voltages can be configured so that a potential gradient develops along the ion guide axis due to this field penetration, which provides an axial motive force for collision damped ions. | 2015-12-17 |
20150364310 | APPARATUS AND METHOD FOR GENERATING CHEMICAL SIGNATURES USING DIFFERENTIAL DESORPTION - The present invention is directed to a method and device to generate a chemical signature for a mixture of analytes. The present invention involves using a SPME surface to one or both absorb and adsorb the mixture of analytes. In an embodiment of the invention, the surface is then exposed to different temperature ionizing species chosen with appropriate spatial resolution to desorb a chemical signature for the mixture of analytes. | 2015-12-17 |
20150364311 | COMPOSITIONS AND METHODS FOR MASS SPECTOMETRY - The invention provides ionizing matrix compounds. These compounds are useful for mass spectrometry and ion mobility spectrometry as ionizing matrices facilitating transfer of diverse classes of analyte compounds from solid or solution states to gas-phase ions. | 2015-12-17 |
20150364312 | Systems and Methods Of Detecting and Demonstrating Heat Damage to Hair Via Evaluation of Peptides - A method to measure heat damage of keratin fibers comprising eluting a peptide from a hair sample with an aqueous solution; extracting the peptide using a suitable solvent sample; analyzing the peptide samples with MALDI-MS; resulting in peptide results; identifying presence of a marker peptide and identifying the m/z ratio for the peptide. | 2015-12-17 |
20150364313 | ION GENERATION DEVICE AND ION GENERATION METHOD - The invention relates to an ion generation device and an ion generation method, and more particularly to a device and a method which generates ions at the low pressure and then said ions can be transferred into the next stage in an off-axis manner. In the invention, ions from electrospray or other types of ion source are generated in the pressure which is lower than atmosphere pressure. A followed ion guide device can then transfer most of said generated ions into next stage in an off-axis manner, while most of neutral noise can be eliminated in this process. | 2015-12-17 |
20150364314 | OFF-AXIS CHANNEL IN ELECTROSPRAY IONIZATION FOR REMOVAL OF PARTICULATE MATTER - The present invention relates to electrospray ionization (ESI) at atmospheric pressure coupled with a mass spectrometer, in particular to a special kind of micro-electrospray with liquid flows in the range of 0.1 to 100 microliters per minute. The invention describes the use of an off-axis pre-entrance channel in an ESI ion source to prevent particulate matter with higher inertia than the (charged) gas molecules, such as droplets, from entering the mass spectrometer. The elimination of the particulate matter improves the quantitative precision of an LC/MS bioassay, minimizes the contamination of the mass spectrometer and improves the robustness for high throughput assays. | 2015-12-17 |
20150364315 | MASS SPECTROMETRY SYSTEMS WITH CONVECTIVE FLOW OF BUFFER GAS FOR ENHANCED SIGNALS AND RELATED METHODS - Mass spectrometry systems include an ionizer, mass analyzer and the detector, with a high pressure chamber holding the mass analyzer and a separate chamber holding the detector to allow for differential background pressures where P | 2015-12-17 |
20150364316 | Electrostatic Trap - An electrostatic trap such as an orbitrap is disclosed, with an electrode structure. An electrostatic trapping field of the form U′(r, φ, z) is generated to trap ions within the trap so that they undergo isochronous oscillations. The trapping field U′(r, φ, z) is the result of a perturbation W to an ideal field U(r, φ, z) which, for example, is hyperlogarithmic in the case of an orbitrap. The perturbation W may be introduced in various ways, such as by distorting the geometry of the trap so that it no longer follows an equipotential of the ideal field U(r, φ, z), or by adding a distortion field (either electric or magnetic). The magnitude of the perturbation is such that at least some of the trapped ions have an absolute phase spread of more than zero but less than 2 π radians over an ion detection period T | 2015-12-17 |
20150364317 | EXCIMER LAMP - Provided is an excimer lamp having a simple and small structure, which can be used in, for example, a refrigerator, and can emit ultraviolet light at a wavelength effective in disinfection processing without generating ozone in a surrounding atmosphere, without leaving gas impurities and moisture in an electrical discharge vessel, and without causing a steep illuminance decrease. A fluorescent substance is disposed on an inner face of the electrical discharge vessel for converting ultraviolet light emitted upon excimer electrical discharge of a light emitting gas to ultraviolet light having a longer wavelength. An inner electrode has a coil shape. A tight winding portion is formed at a certain area of the interior electrode which extends in the center axial direction of the interior electrode such that the coil is tightly wound in the tight winding portion. A getter is attached to the tight winding portion. | 2015-12-17 |
20150364318 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - A method for manufacturing a semiconductor device includes forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate. | 2015-12-17 |
20150364319 | METHOD OF FABRICATING A NITRIDE SUBSTRATE - A method of fabricating a nitride substrate including preparing a growth substrate and disposing a sacrificial layer on the growth substrate. The sacrificial layer includes a nitride horizontal etching layer including an indium-based nitride and an upper nitride sacrificial layer formed on the nitride horizontal etching layer. The method of fabricating the nitride substrate also includes horizontally etching the nitride horizontal etching layer, forming at least one etching hole at least partially through the upper nitride sacrificial layer such that the at least one etching hole expands in the nitride horizontal etching layer in a horizontal direction during horizontal etching of the nitride horizontal etching layer, forming a nitride epitaxial layer on the upper nitride sacrificial layer by hydride vapor phase epitaxy (HVPE) and separating the nitride epitaxial layer from the growth substrate at the nitride horizontal etching layer. | 2015-12-17 |
20150364320 | LATERAL WAFER OXIDATION SYSTEM WITH IN-SITU VISUAL MONITORING AND METHOD THEREFOR - Wafer oxidation apparatus for selective oxidation of a semiconductor workpiece has an oxidation chamber. The oxidation chamber is heated by external infrared heating lamps. A chuck assembly is disposed within the oxidation chamber and configured to be approximately thermally isolated from the oxidation chamber. Carrier gas pathways deliver heated carrier gasses to the oxidation chamber at variable rates for oxidation uniformity. | 2015-12-17 |
20150364321 | Alkyl-Alkoxysilacyclic Compounds and Methods for Depositing Films Using Same - A method and composition for producing a porous low k dielectric film via chemical vapor deposition is provided. In one aspect, the method comprises the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursor comprising an alkyl-alkoxysilacyclic compound, and a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen, and the preliminary film is deposited; and removing from the preliminary film at least a portion of the porogen contained therein and provide the film with pores and a dielectric constant of 2.7 or less. In certain embodiments, the structure-forming precursor further comprises a hardening additive. | 2015-12-17 |
20150364322 | SILICON CONTAINING CONFINEMENT RING FOR PLASMA PROCESSING APPARATUS AND METHOD OF FORMING THEREOF - A method of forming a silicon containing confinement ring for a plasma processing apparatus useful for processing a semiconductor substrate comprises inserting silicon containing vanes into grooves formed in a grooved surface of an annular carbon template wherein the grooved surface of the annular carbon template includes an upwardly projecting step at an inner perimeter thereof wherein each groove extends from the inner perimeter to an outer perimeter of the grooved surface. The step of the grooved surface and a projection at an end of each silicon containing vane is surrounded with an annular carbon member wherein the annular carbon member covers an upper surface of each silicon containing vane in each respective groove. Silicon containing material is deposited on the annular carbon template, the annular carbon member, and exposed portions of each silicon containing vane thereby forming a silicon containing shell of a predetermined thickness. A portion of the silicon containing shell is removed and the annular carbon template and the annular carbon member are removed from the silicon containing shell leaving a silicon containing confinement ring wherein the silicon containing vanes are supported by the silicon containing shell of the silicon containing confinement ring. | 2015-12-17 |
20150364323 | METHOD FOR DEPOSITING POLYCRYSTALLINE SILICON - The Siemens process for deposition of polycrystalline silicon in the form of rods in a sealed reactor is improved by, after introduction of deposition gas has ceased, introducing a ventilating gas into the partially sealed reactor, withdrawing a gas stream from the reactor, and monitoring the components in the gas stream withdrawn until a desired concentration of one or more components is reached, and opening the reactor to remove the rods. | 2015-12-17 |
20150364324 | NANOCRYSTAL THIN FILM FABRICATION METHODS AND APPARATUS - Nanocrystal thin film devices and methods for fabricating nanocrystal thin film devices are disclosed. The nanocrystal thin films are diffused with a dopant such as Indium, Potassium, Tin, etc. to reduce surface states. The thin film devices may be exposed to air during a portion of the fabrication. This enables fabrication of nanocrystal-based devices using a wider range of techniques such as photolithography and photolithographic patterning in an air environment. | 2015-12-17 |
20150364325 | TECHNIQUES FOR INCREASED DOPANT ACTIVATION IN COMPOUND SEMICONDUCTORS - A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range. | 2015-12-17 |
20150364326 | METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer. | 2015-12-17 |
20150364327 | METHOD FOR PREPARING A FILM AND METHOD FOR PREPARING AN ARRAY SUBSTRATE, AND ARRAY SUBSTRATE - The present invention discloses a method for preparing a film and a method for preparing an array substrate, and an array substrate. The method for preparing a film comprises forming an AB alloy film subjected to oxidation treatment and forming a first metal A film, wherein the first metal A film is provided to contact with the AB alloy film subjected to oxidation treatment, wherein A is a first metal and B is a second metal, the second metal is selected from active metals in period 2 to period 4 of group 2, and the AB alloy film subjected to oxidation treatment is formed by forming an alloy film of a first metal A and a second metal B in the presence of an oxygen-containing gas. | 2015-12-17 |
20150364328 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage. | 2015-12-17 |
20150364329 | Carbon Layer and Method of Manufacture - A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene. | 2015-12-17 |
20150364330 | TA BASED AU-FREE OHMIC CONTACTS IN ADVANCED AIGAN/GAN BASED HFETS AND/OR MOSHFETS FOR POWER SWITCH APPLICATIONS - A method of forming an Ohmic contact including forming a Ta layer in a contact area of a barrier layer by evaporation at an evaporation rate of 1 Å/second, forming a Ti layer on the first Ta layer, and forming an Al layer on the Ti layer, wherein the barrier layer comprises AlGaN having a 25% Al composition and a thickness in a range between 30 Å to 100 Å, and wherein the barrier layer is on a channel layer comprising GaN. | 2015-12-17 |
20150364331 | EXTREMELY THIN PACKAGE - Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate. | 2015-12-17 |
20150364332 | INORGANIC FILM-FORMING COMPOSITION FOR MULTILAYER RESIST PROCESSES, AND PATTERN-FORMING METHOD - An inorganic film-forming composition for multilayer resist processes includes a complex that includes: metal atoms; at least one bridging ligand; and a ligand which is other than the at least one bridging ligand and which is derived from a hydroxy acid ester, a β-diketone, a β-keto ester, a β-dicarboxylic acid ester or a combination thereof. The at least one bridging ligand includes a first bridging ligand derived from a compound represented by formula (1). An amount of the first bridging ligand is no less than 50 mol % with respect to a total of the bridging ligand. In the formula (1), R | 2015-12-17 |
20150364333 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURE - According to an exemplary embodiment, a method of forming vertical structures is provided. The method includes the following operations: providing a substrate; forming a first oxide layer over the substrate; forming a first dummy layer over the first oxide layer; etching the first oxide layer and the first dummy layer to form a recess; forming a second dummy layer in the recess (and further performing CMP on the second dummy layer and stop on the first dummy layer); removing the first dummy layer; removing the first oxide layer; and etching the substrate to form the vertical structure. According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; an STI embedded in the substrate; and a vertical transistor having a source substantially aligned with the STI. | 2015-12-17 |
20150364334 | METHOD OF FORMING PATTERNS AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE - Provided are a method of forming patterns and a method of manufacturing an integrated circuit device. In the method of forming patterns, a photoresist pattern having a first opening exposing a first region of a target layer is formed. A capping layer is formed at sidewalls of the photoresist pattern defining the first opening. An insoluble region is formed around the first opening by diffusing acid from the capping layer to the inside of the photoresist pattern. A second opening exposing a second region of the target layer is formed by removing a soluble region spaced apart from the first opening, with the insoluble region being interposed therebetween. The target layer is etched using the insoluble region as an etch mask. | 2015-12-17 |
20150364335 | METHODS FOR PROVIDING SPACED LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - A method of forming a plurality of regularly spaced lithography features, the method including providing a self-assemblable block copolymer having first and second blocks in a plurality of trenches on a substrate, each trench including opposing side-walls and a base, with the side-walls having a width therebetween, wherein a first trench has a greater width than a second trench; causing the self-assemblable block copolymer to self-assemble into an ordered layer in each trench, the layer having a first domain of the first block alternating with a second domain of the second block, wherein the first and second trenches have the same number of each respective domain; and selectively removing the first domain to form regularly spaced rows of lithography features having the second domain along each trench, wherein the pitch of the features in the first trench is greater than the pitch of the features in the second trench. | 2015-12-17 |
20150364336 | UNIFORM GATE HEIGHT FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing. | 2015-12-17 |
20150364337 | PATTERNING OF A HARD MASK MATERIAL - A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material. | 2015-12-17 |
20150364338 | Method to Improve Etch Selectivity During Silicon Nitride Spacer Etch - Techniques herein include methods to increase etching selectivity among materials. Techniques herein include a cyclical process of etching and oxidation of a silicon nitride (Sin) spacer and silicon (such as polycrystalline silicon). This technique can increase selectivity to the silicon so that silicon is less likely to be etched or damaged while silicon nitride is etched from sidewalls. Techniques and chemistries as disclosed herein can be more selective to silicon oxide and silicon as compared to silicon nitride. An oxidizing step creates an oxide protection film on silicon surfaces that is comparatively thicker to any oxide film formed on nitride surfaces. As such, techniques here enable better removal of silicon nitride and silicon nitride spacer materials. | 2015-12-17 |
20150364339 | DUAL CHAMBER PLASMA ETCHER WITH ION ACCELERATOR - The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber. The etching gas and ions react with the surface of the substrate to etch the substrate as desired. | 2015-12-17 |
20150364340 | CHEMICAL SENSOR ARRAYS FOR ODOR DETECTION - An array of semiconductor chemical sensors and a method for manufacturing the array of semiconductor chemical sensors are disclosed. In some examples, the method may include providing a semiconductor substrate including a plurality of areas, and ejecting onto each area of the semiconductor substrate a solution including at least one modification material for modifying each area of the semiconductor substrate. | 2015-12-17 |
20150364341 | THERMAL INTERFACE MATERIAL ON PACKAGE - A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. | 2015-12-17 |
20150364342 | THERMAL INTERFACE MATERIAL ON PACKAGE - A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. | 2015-12-17 |
20150364343 | THERMAL INTERFACE MATERIAL ON PACKAGE - A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. | 2015-12-17 |
20150364344 | Integrated Circuit Packages and Methods of Forming Same - Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die. | 2015-12-17 |
20150364345 | METHOD AND APPARATUS FOR LIQUID TREATMENT OF WAFER SHAPED ARTICLES - In an apparatus for treating a wafer-shaped article, a spin chuck is provided for holding and rotating a wafer-shaped article. A liquid dispenser comprises a check valve positioned so as to prevent process liquid from dripping out of a discharge nozzle of the liquid dispenser. A valve seat of the check valve is at a distance in a range of 20 mm to 100 mm from an outlet opening of said discharge nozzle. | 2015-12-17 |
20150364346 | EXHAUST SYSTEM OF WAFER TREATMENT DEVICE - Provided is an exhaust system of a wafer treatment device, and the main purpose thereof is to prevent secondary contamination of a wafer by not allowing foreign substances such as process gases and fumes and the like floating in the wafer treatment device to make contact with the wafer in a side storage. The wafer treatment device comprises: a cleaning device for removing foreign substances remaining on a wafer; and an exhaust device comprising first and second main bodies at the lower side of a main body of the wafer treatment device. By not allowing foreign substances such as process gases and fumes and the like floating in the wafer treatment device to make contact with a wafer in a side storage, secondary contamination of the wafer is prevented. | 2015-12-17 |
20150364347 | DIRECT LIFT PROCESS APPARATUS - The present disclosure provides a substrate support assembly includes a substrate pedestal having an upper surface for receiving and supporting a substrate, a cover plate disposed on the substrate support pedestal, and two or more lift pins movably disposed through the substrate support pedestal and the cover plate. The cover plate includes a disk body having a central opening. The two or more lift pins are self supportive. Each of the two or more lift pins comprises one or more contact pads, and the contact pads of the lift pins extend into to the central opening of the cover plate to receive and support a substrate at an edge region of the substrate. | 2015-12-17 |
20150364348 | GAS PHASE ETCHING APPARATUS - Provided is a gas phase etching apparatus. The gas phase etching apparatus includes a process chamber having an inner space that is defined by a chamber body having an opened upper portion and an upper dome having an opened lower portion and detachably coupled to an upper portion of the chamber body, a substrate susceptor disposed in the inner space to ascend and descend by a driving unit, and a ring plate disposed on the substrate susceptor to cover a space between the substrate susceptor and an outer wall of the process chamber so that the inner space is partitioned into a process region defined above the substrate susceptor and an exhaust region defined below the substrate susceptor. The process region partitioned by the ring plate is surrounded by the upper dome, and the exhaust region is surrounded by the chamber body. | 2015-12-17 |
20150364349 | DUAL CHAMBER PLASMA ETCHER WITH ION ACCELERATOR - The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber. The etching gas and ions react with the surface of the substrate to etch the substrate as desired. | 2015-12-17 |
20150364350 | HEATING AND COOLING OF SUBSTRATE SUPPORT - A process chamber and a method for controlling the temperature of a substrate positioned on a substrate support assembly within the process chamber are provided. The substrate support assembly includes a thermally conductive body, a substrate support surface on the surface of the thermally conductive body and adapted to support a large area substrate thereon, one or more heating elements embedded within the thermally conductive body, and two or more cooling channels embedded within the thermally conductive body to be coplanar with the one or more heating elements. The cooling channels may be branched into two or more equal-length cooling passages being extended from a single point inlet and into a single point outlet to provide equal resistance cooling. | 2015-12-17 |
20150364351 | POST-PROCESSING APPARATUS OF SOLAR CELL - A post-processing apparatus of a solar cell is discussed. The post-processing apparatus carries out a post-processing operation including a main period for heat-treating a solar cell including a semiconductor substrate while providing light to the solar cell. The post-processing apparatus includes a main section to carry out the main period. The main section includes a first heat source unit to provide heat to the semiconductor substrate and a light source unit to provide light to the semiconductor substrate. The first heat source unit and the light source unit are positioned in the main section. The light source unit includes a light source constituted by a plasma lighting system (PLS). | 2015-12-17 |
20150364352 | Wafer Loading and Unloading - A robotic handling system loads and unloads wafers (e.g., silicon wafers) and their carriers into and out of an interlock chamber of a loadlock system. The wafer handling system includes an end effector that handles both the wafer and the carrier by their bottom surfaces, avoiding contact with the top surface of the wafer. From the interlock chamber, wafers, seated on the carrier, are moved into a processing chamber under vacuum conditions. Processed wafers, seated on the carrier, are moved from the processing chamber back into the interlock chamber and removed from the interlock chamber by the robotic handling system under atmospheric conditions. | 2015-12-17 |
20150364353 | MANUFACTURING LINE FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing line for a semiconductor device according to the invention is a manufacturing line for manufacturing a semiconductor device by circulating a workpiece along a conveyance route on which a plurality of treatment devices are arranged. The conveyance route includes a first route on which the treatment devices with a large number of times of treatment are arranged, and a second route on which the treatment devices with a small number of times of treatment are arranged. Besides, the conveyance route makes a changeover between the conveyance of the workpiece that has moved along the first route to the first route in a continuous manner, and the conveyance of the workpiece that has moved along the first route to the second route. | 2015-12-17 |
20150364354 | MULTI-ZONE HEATED ESC WITH INDEPENDENT EDGE ZONES - An electrostatic chuck (ESC) with a cooling base for plasma processing chambers, such as a plasma etch chamber. In embodiments, a plasma processing chuck includes a plurality of independent edge zones. In embodiments, the edge zones are segments spanning different azimuth angles of the chuck to permit independent edge temperature tuning, which may be used to compensate for other chamber related non-uniformities or incoming wafer non-uniformities. In embodiments, the chuck includes a center zone having a first heat transfer fluid supply and control loop, and a plurality of edge zones, together covering the remainder of the chuck area, and each having separate heat transfer fluid supply and control loops. In embodiments, the base includes a diffuser, which may have hundreds of small holes over the chuck area to provide a uniform distribution of heat transfer fluid. | 2015-12-17 |
20150364355 | SAMPLE HOLDER AND PLASMA ETCHING APPARATUS USING SAME - A sample holder includes a substrate composed of ceramics, having a sample holding surface on one main surface thereof; and a heat-generating resistor provided on an other main surface of the substrate, containing a glass component. The substrate contains the glass component in a vicinity region of the heat-generating resistor. | 2015-12-17 |
20150364356 | SECTIONAL POROUS CARRIER FORMING A TEMPORARY IMPERVIOUS SUPPORT - Compositions and designs are described for a sectional porous carrier used in processing microelectronics where thin device substrates are affixed by adhesive to the carrier and form an impervious bonded stack that is resistant to thermal and chemical products during processing and is easily handled by a substrate handling vacuum robot, and subsequently allows rapid removal (debonding) in batch operations by directional penetration into sectional porous regions by selective liquids which release the carrier from the device wafer without harm. The invention carrier with porous regions is used for temporary support of thin and fragile device substrates having capabilities of selective penetration of chemical liquids to pass through the porous regions, access and breakdown the bonding adhesive, and allow it to release without damage to the device substrate. The sectional porous nature of the carrier allows passive diffusion of chemical liquids, the manner which in contrast to mechanical, thermal, or radiative methods, is considered to be a higher yield practice and one which enables batch processing in a manufacturing environment utilizing practices of high throughput and low cost. Preferred designs include the use of porous metal forms, including laminates, as well as surface treatment of the porous regions to facilitate exclusion principles and achieve an inert support mechanism during the stages of device manufacture. These benefits allow design flexibility and low-cost batch processing when choosing practices to handle thinned device substrates in the manufacture of semiconductors and other microelectronic devices. | 2015-12-17 |
20150364357 | DICING-TAPE INTEGRATED FILM FOR BACKSIDE OF SEMICONDUCTOR AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the increase of the peel strength between the dicing tape and the film for the backside of a flip-chip semiconductor due to heating. The dicing-tape integrated film for the backside of a semiconductor has a dicing tape having a substrate and a pressure-sensitive adhesive layer formed on the substrate and a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, in which the difference (γ2−γ1) of the surface free energy γ2 and the surface free energy γ1 is 10 mJ/m | 2015-12-17 |
20150364358 | METHOD OF FORMING ISOLATION LAYER - According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure. | 2015-12-17 |
20150364359 | Non-Hierarchical Metal Layers for Integrated Circuits - An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. | 2015-12-17 |
20150364360 | METHOD OF FORMING SHALLOW TRENCH ISOLATION AND SEMICONDUCTOR DEVICE - According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding from the substrate; a second vertical structure protruding from the substrate; an STI between the first vertical structure and the second vertical structure; wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI. | 2015-12-17 |
20150364361 | SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES - A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. | 2015-12-17 |
20150364362 | WAFER STRESS CONTROL WITH BACKSIDE PATTERNING - Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication. | 2015-12-17 |
20150364363 | VHF ETCH BARRIER FOR SEMICONDUCTOR INTEGRATED MICROSYSTEM - The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die. | 2015-12-17 |
20150364364 | METHOD FOR TRASFERRING A LAYER - A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region. | 2015-12-17 |
20150364365 | ENHANCEMENT OF ISO-VIA RELIABILITY - A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line. | 2015-12-17 |
20150364366 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING HIGH ASPECT RATIO - Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings. | 2015-12-17 |
20150364367 | SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER - A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. | 2015-12-17 |
20150364368 | SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER - A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. | 2015-12-17 |
20150364369 | Conductive Line System and Process - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. | 2015-12-17 |
20150364370 | Aluminum Interconnection Apparatus - A method comprises depositing a first alloy layer over a substrate, depositing a metal layer over the first alloy layer, depositing a second alloy layer over the metal layer, patterning the first alloy layer, the metal layer and the second alloy layer to form a metal structure and depositing a dielectric layer over the metal structure through a chemical vapor deposition (CVD) process. | 2015-12-17 |
20150364371 | SELF-ALIGNED INTERCONNECT WITH PROTECTION LAYER - An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug. | 2015-12-17 |
20150364372 | DOUBLE SELF-ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 2015-12-17 |