50th week of 2009 patent applcation highlights part 47 |
Patent application number | Title | Published |
20090305418 | CELL THERAPY METHOD FOR THE TREATMENT OF TUMORS - T cell responses are often diminished in humans with a compromised immune system. We have developed a method to isolate, stimulate and expand naïve cytotoxic T lymphocyte precursors (CTLp) to antigen-specific effectors, capable of lysing tumor cells in vivo. This ex vivo protocol produces fully functional effectors. Artificial antigen presenting cells (AAPCs; | 2009-12-10 |
20090305419 | Compositions for linking DNA-binding domains and cleavage domains - Disclosed herein are compositions for linking DNA binding domains and cleavage domains (or cleavage half-domains) to form non-naturally occurring nucleases. Also described are methods of making and using compositions comprising these linkers. | 2009-12-10 |
20090305420 | SRSV DETECTION KIT - This invention relates to an SRSV detection kit comprising all antibodies against SRSV-related virus constituting peptides selected from the following peptide groups (a) to (k), respectively: (a) a peptide having an amino acid sequence represented by SEQ ID NO: 1, and the like, (b) a peptide having an amino acid sequence represented by SEQ ID NO: 2, and the like, (c) a peptide having an amino acid sequence represented by SEQ ID NO: 3, and the like, (d) a peptide having an amino acid sequence represented by SEQ ID NO: 4, and the like, (e) a peptide having an amino acid sequence represented by SEQ ID NO: 5, and the like, (f) a peptide having an amino acid sequence represented by SEQ ID NO: 6, and the like, (g) a peptide having an amino acid sequence represented by SEQ ID NO: 7, and the like, (h) a peptide having an amino acid sequence represented by SEQ ID NO: 8, and the like, (i) a peptide having an amino acid sequence represented by SEQ ID NO: 9, and the like, (j) a peptide having an amino acid sequence represented by SEQ ID NO: 10, and the like, and (k) a peptide having an amino acid sequence represented by SEQ ID NO: 11, and the like. | 2009-12-10 |
20090305421 | Recombinant vector for deleting specific regions of chromosome and method for deleting specific chromosomal regions of chromosome in the microorganism using the same - Disclosed herein are a recombinant vector for deletion of specific chromosomal regions and a method for deletion of targeted microbial chromosomal regions using the same. Specifically, the recombinant vector comprises an arabinose-inducible promoter; a gene encoding a protein involved in lambda (λ)-red recombination; a rhamnose-inducible promoter; and a gene encoding the I-SceI endonuclease. The present invention enables a convenient, rapid and markerless successive deletion of specific genes of microbes, as compared to a conventional method. | 2009-12-10 |
20090305422 | METHODS AND REAGENTS FOR PRESERVATION OF DNA IN BODILY FLUIDS - Methods, systems and reagents are provided for preserving nucleic acids in a bodily fluid, such as urine, blood, blood serum, and amniotic fluid. The preservative includes an amount of at least one chelator enhancing component selected from the group consisting of lithium chloride, guanidine, sodium salicylate, sodium perchlorate, guanidine thiocyanate, and sodium thiocyanate in the range of from about 0.1M to about 2M and an amount of least one buffer component selected from the group consisting of Tris and HEPES. | 2009-12-10 |
20090305423 | Methods for Monitoring Composition and Flavor Quality of Cheese Using a Rapid Spectroscopic Method - Methods for evaluating cheese comprising using a rapid extraction method and an IR spectra analysis of the cheese are disclosed. | 2009-12-10 |
20090305424 | Microfluidic Flow Devices For Determining Parameters of Physical and/or Chemical Transformations - Microfluidic flow devices for determining parameters of a physical and/or chemical transformation include a body ( | 2009-12-10 |
20090305425 | In-Line Localized Monitoring of Catalyst Activity in Selective Catalytic NOx Reduction Systems - Localized catalyst activity in an SCR unit for controlling emissions from a boiler, power plant, or any facility that generates NO | 2009-12-10 |
20090305426 | AXIAL ILLUMINATION FOR CAPILLARY ELECTROPHORESIS - System and method for fluorescent light excitation and detection from samples to enhance the numerical aperture and/or reduce the cross-talk of the fluorescent light. | 2009-12-10 |
20090305427 | APPARATUS AND PROCESS FOR SENSING FLUORO SPECIES IN SEMICONDUCTOR PROCESSING SYSTEMS - A gas detector and process for detecting a fluorine-containing species in a gas containing same, e.g., an effluent of a semiconductor processing tool undergoing etch cleaning with HF, NF | 2009-12-10 |
20090305428 | Apparatus and method for evaluating a hydrocarbon to determine the propensity for coke formation - An apparatus ( | 2009-12-10 |
20090305429 | Method for Detecting Alkylating Agents - The present invention relates to methods for detecting alkylating agents in a sample using a chemosensor and measuring the change in measurable properties of chemosensor upon binding. Such changes provide indications of the presence and quantity of alkylating agent in the sample. | 2009-12-10 |
20090305430 | DEVICE FOR PREPARING BONE CEMENT - A method of monitoring the extent of cure of a mixed bone cement includes the steps of taking in hand a flexible polymeric film wherein loaded with a thermochromic material configured to change color at a predetermined temperature; wrapping a quantity of the mixed bone cement in the film such that the film is in contact with and tightly conforms to the mixed bone cement; and monitoring the film to identify a change in the color of the film, the change in the color of the film indicating that the mixed bone cement has reached the pre-determined temperature. | 2009-12-10 |
20090305431 | FLUID TRANSFER MECHANISM - A microfluidic device for transferring liquid from a first chamber to a second chamber is provided. The device has a first chamber; a second chamber; and a barrier between the first chamber and the second chamber, the barrier having least one opening fluidly connecting the first chamber to the second chamber, the at least one opening being sized such that a retention force, such as surface tension, keeps the liquid in the first chamber. The fluid is transferred from the first chamber to the second chamber when an initiation input such as fluid pressure is introduced to the liquid that is sufficient to overcome the retention force. The device may be a sensor strip. | 2009-12-10 |
20090305432 | Polypeptide Molecular Switch - A polypeptide can conduct electricity in a closed circuit. Conformational changes in the polypeptide due to posttranslational modifications or ligand binding can effect the conductive properties of the polypeptide which can be measured. In such a closed circuit, a polypeptide having at least one residue capable of reversible modification can be used as a molecular switch. Circuits comprising such molecular switches can be used, for example, in methods for assessing the modification state of a polypeptide, determining the activity of an enzyme of interest, identifying compounds that affect the activity of an enzyme of interest, storing data, detecting the presence of a compound and identifying inhibitors of protein-protein interactions. | 2009-12-10 |
20090305433 | Water-Soluble Rhodamine Dye Conjugates - The present invention provides novel, water-soluble, red-emitting fluorescent rhodamine dyes and red-emitting fluorescent energy-transfer dye pairs, as well as labeled conjugates comprising the same and methods for their use. The dyes, energy-transfer dye pairs and labeled conjugates are useful in a variety of aqueous-based applications, particularly in assays involving staining of cells, protein binding, and/or analysis of nucleic acids, such as hybridization assays and nucleic acid sequencing. | 2009-12-10 |
20090305434 | METHOD OF DIAGNOSING NEUROPHSYCHIATRIC DISEASES, EATING DISORDERS OR METABOLIC DISEASES - The application relates to a method of diagnosing neuropsychiatric diseases, eating disorders and/or metabolic diseases, which comprises: (i) measuring the affinity and/or the avidity of antibodies, derived from a biological sample, directed against a biological molecule involved in homeostatic regulation and/or in motivational behavior and/or in emotion; (ii) comparing the affinity value obtained with a control value. | 2009-12-10 |
20090305435 | METHOD OF CALIBRATING LIGAND SPECIFICITY - A method to determine specificity of ligand binding includes comparing a solid phase carrier first extract obtained by pre-treating a sample with a ligand-immobilized solid phase carrier and a solid phase carrier second extract obtained by treating the pretreated sample again with a ligand-immobilized solid phase carrier in terms of the proteins contained therein, and identifying a protein whose content is remarkably decreased in the second extract compared to the first extract, in order to solve | 2009-12-10 |
20090305436 | DEVICE AND METHOD FOR DETECTION OF A PREGNANCY ASSOCIATED HORMONE - The invention provides a device ( | 2009-12-10 |
20090305437 | FABRICATION OF INORGANIC MATERIALS USING TEMPLATES WITH LABILE LINKAGE - A method of forming an integrated circuit layer material is described, comprising depositing a layer of templates on a substrate, said template including a first binding site having an affinity for the substrate, a second binding site having an affinity for a target integrated circuit material and a protecting material coupled to the second binding site via a labile linkage to prevent the binding site from binding to the target integrated circuit material; exposing the template to an external stimulus to degrade the labile linkage; removing the protecting material; and binding the integrated circuit material to the second binding site. | 2009-12-10 |
20090305438 | Trench isolation method of semiconductor device using chemical mechanical polishing process - A trench isolation method of a semiconductor device includes forming polishing prevention film patterns on a semiconductor substrate, etching the semiconductor device by using the polishing prevention film patterns as masks and forming trenches, and forming conformal insulation films on the semiconductor substrate and the polishing prevention film patterns by burying the trenches. The conformal insulation films are first polished using a first polishing pad by using a slurry including an abrasive having a polishing selection ratio with respect to the polishing prevention film patterns. The first polished conformal insulation films are second polished using a second polishing pad including an abrasive and by using the polishing prevention film patterns as polishing prevention films. | 2009-12-10 |
20090305439 | METHOD FOR CORRECTING MASK PATTERN AND METHOD FOR MANUFACTURING ACCELERATION SENSOR AND ANGULAR VELOCITY SENSOR BY USING THE METHOD FOR CORRECTING THE MASK PATTERN - A method for correcting a mask pattern used for dry-etching an object with higher accuracy, and for manufacturing an acceleration sensor and an angular velocity sensor. The object is first etched by a dry-etching process using an uncorrected reference mask pattern. Then, distribution of the size of expansion of a tapered portion formed in a surface of the object is measured. Thereafter, the measured distribution is approximated by using a quadratic curve (Y=AX | 2009-12-10 |
20090305440 | Method for Treatment of Samples for Auger Electronic Spectrometer (AES) in the Manufacture of Integrated Circuits - A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis. | 2009-12-10 |
20090305441 | NEXT GENERATION SCREEN PRINTING SYSTEM - Embodiments of the present invention provide an apparatus and method for processing substrates using a multiple screen printing chamber processing system that has an increased system throughput, improved system uptime, and improved device yield performance, while maintaining a repeatable and accurate screen printing process on the processed substrates. In one embodiment, the multiple screen printing chamber processing system is adapted to perform a screen printing process within a portion of a crystalline silicon solar cell production line in which a substrate is patterned with a desired material, and then processed in one or more subsequent processing chambers. | 2009-12-10 |
20090305442 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - The light emitting device comprises a substrate | 2009-12-10 |
20090305443 | METHOD OF MAKING LIGHT EMITTING DIODES - A method of making a plurality of light emitting diodes simultaneously includes steps of: a) providing a wafer and a first bonding layer, and adhering the first bonding layer to a bottom side of the wafer; b) cutting the wafer to form a plurality of LED dies on the first bonding layer; c) adhering a second bonding layer on top sides of the plurality of LED dies; d) removing the first bonding layer; e) mounting the second bonding layer with the plurality of LED dies on a base having a plurality of recesses; f) removing the second bonding layer and letting the plurality of LED dies fall into the recesses of the base; g) electrically connecting the LED dies to electric poles in the base; h) encapsulating the LED dies; and i) cutting the base to form the plurality of LEDs. | 2009-12-10 |
20090305444 | Liquid crystal display device and method for fabricating the same - A liquid crystal display device includes a first substrate having a step difference part; a second substrate facing the first substrate; a column spacer between the first substrate and the second substrate, a contact surface of the column spacer with the step difference part of the first substrate including a plurality of protrusions; and a liquid crystal layer between the first substrate and the second substrate. | 2009-12-10 |
20090305445 | Method for Manufacturing Light-Emitting Device - In the present invention, a first substrate which is an evaporation donor substrate is prepared in which a material layer is formed over a patterned reflective layer. A surface of the material layer over the first substrate is irradiated with first light which satisfies one predetermined irradiation condition to pattern the material layer. A surface opposite to the surface of the first substrate is irradiated with second light which satisfies another predetermined irradiation condition to evaporate the patterned material layer onto a second substrate, which is a deposition target substrate. According to the present invention, deterioration of a material included in the material layer can be prevented and a film pattern can be formed on the second substrate with high accuracy. | 2009-12-10 |
20090305446 | HIGH EFFICIENCY LIGHT EMITTING DIODE (LED) WITH OPTIMIZED PHOTONIC CRYSTAL EXTRACTOR - A high efficiency, and possibly highly directional, light emitting diode (LED) with an optimized photonic crystal extractor. The LED is comprised of a substrate, a buffer layer grown on the substrate (if needed), an active layer including emitting species, one or more optical confinement layers that tailor the structure of the guided modes in the LED, and one or more diffraction gratings, wherein the diffraction gratings are two-dimensional photonic crystal extractors. The substrate may be removed and metal layers may be deposited on the buffer layer, photonic crystal and active layer, wherein the metal layers may function as a mirror, an electrical contact, and/or an efficient diffraction grating. | 2009-12-10 |
20090305447 | IMPLANTED VERTICAL CAVITY SURFACE EMITTING LASER - A method of forming a gain guide implant for a vertical cavity surface emitting laser (VCSEL) comprises implanting ions into a wafer to simultaneously form a first non-conducting portion of the gain guide implant spaced apart from an active region and a second non-conducting portion of the gain guide implant occupying the active region, the first non-conducting portion laterally offset relative to the second non-conducting portion. | 2009-12-10 |
20090305448 | Method for Manufacturing a Semiconductor Light Emitting Device - To provide a method for manufacturing a semiconductor light emitting device capable of providing sufficiently low operating voltage. | 2009-12-10 |
20090305449 | Methods and Devices For Processing A Precursor Layer In a Group VIA Environment - Methods and devices for high-throughput printing of a precursor material for forming a film of a group IB-IIIA-chalcogenide compound are disclosed. In one embodiment, the method comprises forming a precursor layer on a substrate, the precursor is subsequently processed in a VIA environment. | 2009-12-10 |
20090305450 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERTING DEVICE - The present invention relates to a manufacturing method of obtaining a photoelectric converting device which can sufficiently maintain airtightness of a housing space for photocathode without degradation of the characteristics of the photocathode. In accordance with the manufacturing method, on the side wall end face of a lower frame and a bonding portion of an upper frame forming an envelope of the photoelectric converting device, a multilayered metal film of chromium and nickel is formed. In a vacuum space decompressed to a predetermined degree of vacuum and having a temperature not more than the melting point of indium, these upper and lower frames introduced therein are brought into close contact with each other with a predetermined pressure while sandwiching indium wire members, and accordingly, an envelope having a housing space whose airtightness is sufficiently maintained is obtained. | 2009-12-10 |
20090305451 | MANUFACTURING METHOD OF WAFER LEVEL CHIP SCALE PACAKGE OF IMAGE-SENSING MODULE - A manufacturing method of a wafer level chip scale package of an image-sensing module is provided. The method includes providing. a wafer having a plurality of die regions, and a plurality of sensing units is formed on a surface of the wafer in each die region. A plurality of lens units is formed on the sensing units, wherein each lens unit includes a lens and an edge wall that are integrally formed. A light-shielding film is also formed on a surface of at least one edge wall of at least one lens units. A dicing process is then performed on the wafer to form a plurality of image sensor chips. | 2009-12-10 |
20090305452 | Methods of Making Quantum Dot Films - Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. | 2009-12-10 |
20090305453 | METHOD OF FABRICATING IMAGE SENSOR DEVICE - A method for fabricating an image sensor device is disclosed. A substrate having a sensing area comprising a pixel array therein is provided. A photoresist layer is coated over the substrate. Exposure is performed on at least two regions of the photoresist layer by at least two binary half-tone masks, respectively, in which a first and second binary half-tone masks of the two binary half-tone masks have different optical transparency distributions. Development is performed on the exposed photoresist layer to form a convex microlens array corresponding to the pixel array of the sensing area and comprising at least two microlenses with different convex profiles. | 2009-12-10 |
20090305454 | FAST P-I-N PHOTODETECTOR WITH HIGH RESPONSITIVITY - A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon. | 2009-12-10 |
20090305455 | Formation of CIGS Absorber Layers on Foil Substrates - An absorber layer of a photovoltaic device may be formed on an aluminum or metallized polymer foil substrate. A nascent absorber layer containing one or more elements of group IB and one or more elements of group IIIA is formed on the substrate. The nascent absorber layer and/or substrate is then rapidly heated from an ambient temperature to an average plateau temperature range of between about 200° C. and about 600° C. and maintained in the average plateau temperature range 2 to 30 minutes after which the temperature is reduced. | 2009-12-10 |
20090305456 | Method of Manufacturing Back Junction Solar Cell - A method of manufacturing a back junction solar cell comprises the steps of forming a first diffusion mask ( | 2009-12-10 |
20090305457 | SOLAR CELL, SOLAR MODULE AND SYSTEM AND FABRICATION METHOD THEREOF - A solar cell having an improved structure of rear surface includes a p-type doped region, a dense metal layer, a loose metal layer, at least one bus bar opening, and solderable material on or within the bus bar opening. The solderable material contacts with the dense aluminum layer. The improved structure in rear surface increases the light converting efficiency, and provides a good adhesion between copper ribbon and solar cell layer thereby providing cost advantages and reducing the complexity in manufacturing. A solar module and solar system composed of such solar cell are also disclosed. | 2009-12-10 |
20090305458 | ANTIMONY AND GERMANIUM COMPLEXES USEFUL FOR CVD/ALD OF METAL THIN FILMS - Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films. | 2009-12-10 |
20090305459 | Methods of Splitting CdZnTe Layers from CdZnTe Substrates for the Growth of HgCdTe - Methods of producing CdZnTe (CZT) layers for the epitaxial growth of HgCdTe thereon include implanting ions into a CZT substrate at a low temperature to form a damaged layer underneath a CZT surface layer, bonding a wafer to the CZT substrate about the CZT surface layer using a bonding material, and, annealing the CZT substrate for a time sufficient to facilitate the splitting of the CZT substrate at the damaged layer from the CZT surface layer. | 2009-12-10 |
20090305460 | Programmable Via Devices with Air Gap Isolation - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap. | 2009-12-10 |
20090305461 | Semiconductor Device And Manufacturing Method Thereof - An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region. | 2009-12-10 |
20090305462 | COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION - A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array. | 2009-12-10 |
20090305463 | System and Method for Thermal Optimized Chip Stacking - A method for thermal optimization comprising the steps of stacking a first chip layer and a second chip layer wherein the second chip layer is rotated in relation to the first chip layer wherein a first hot spot on the first chip layer and a second hot spot on the second chip layer are not spatially aligned; routing a signal input through the first chip layer from a first chip pad on the first chip layer to a first silicon via so as to form a physical input to output twist and a first signal output; and routing the first signal output from the first chip layer through a second chip layer from a second chip pad on the second chip layer to a second silicon via so as to form a second signal output. | 2009-12-10 |
20090305464 | Array-Processed Stacked Semiconductor Packages - One embodiment of the invention is a semiconductor system ( | 2009-12-10 |
20090305465 | MICROBUMP SEAL - A sealable microelectronic device providing mechanical stress endurance which includes a semiconductor substrate. A substantially continuous sealing element is positioned adjacent an outer periphery and between a microelectronic component and the semiconductor substrate, or another microelectronic component. The sealing element seals the microelectronic component to the substrate or another microelectronic component, and provides structural support to the microelectronic device. | 2009-12-10 |
20090305466 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package is provided, which can improve the quality of plating through reduction of plating deviation, and improve molding and soldering efficiencies in forming a molding compound and packaging the semiconductor package onto a printed circuit board. | 2009-12-10 |
20090305467 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a highly reliable semiconductor device that is reduced in thickness and size and has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield. | 2009-12-10 |
20090305468 | Methods of manufacturing oxide semiconductor thin film transistor - Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above. | 2009-12-10 |
20090305469 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer. | 2009-12-10 |
20090305470 | ISOLATING BACK GATES OF FULLY DEPLETED SOI DEVICES - Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well therein of opposite polarity than the first polarity; forming a trench structure in the FDSOI substrate; forming an active region to each side of the trench structure in the SOI layer; and forming a PFET on the active region on one side of the trench structure and an NFET on the active region on the other side of the trench structure. | 2009-12-10 |
20090305471 | THIN SILICON SINGLE DIFFUSION FIELD EFFECT TRANSISTOR FOR ENHANCED DRIVE PERFORMANCE WITH STRESS FILM LINERS - The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance. | 2009-12-10 |
20090305472 | DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle. | 2009-12-10 |
20090305473 | METHOD FOR FABRICATING THIN FILM TRANSISTOR - A method for fabricating a thin film transistor is provided. A gate is formed on a substrate. A gate insulating layer is formed on the substrate to cover the gate. A metal oxide material layer is formed on the gate insulating layer. A photoresist layer is formed on the metal oxide material layer, in which a thickness of the photoresist layer above the gate is larger than that of the photoresist layer above two sides adjacent to the gate. A portion of the metal oxide material layer is removed to form a metal oxide active layer by using the photoresist layer as a mask. The photoresist layer above the two sides adjacent to the gate is removed and the remaining photoresist layer covers a portion of the metal oxide active layer. A source and a drain are formed on the metal oxide active layer covered by the photoresist layer. | 2009-12-10 |
20090305474 | STRAINED-SILICON CMOS DEVICE AND METHOD - The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension. | 2009-12-10 |
20090305475 | Method of Manufacturing Trenched Mosfets with Embedded Schottky in the Same Cell - A method for manufacturing a trenched semiconductor power device includes a step of forming said semiconductor power device with a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The method further includes the steps of covering the MOSFET cell with an insulation layer and applying a contact mask for opening a source-body contact trench extending through the source and body regions into an epitaxial layer underneath for filling a contact metal plug therein. And, the method further includes a step of forming an embedded Schottky diode by forming a Schottky barrier layer near a bottom of the source-body contact trench below the contact metal plug with the Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source. | 2009-12-10 |
20090305476 | Control Element of an Organic Electro-Luminescent Display and Manufacturing Process Thereof - A control element of an organic electro-luminescent display includes a first transistor, a second transistor and a capacitor. The first gate electrode of the first transistor is electrically connected to a scan line, and the first source/drain electrode of the first transistor is electrically connected to a data line. The second gate electrode of the second transistor is electrically connected to the second source/drain electrode of the first transistor. The third source/drain electrode of the second transistor is electrically connected to a working voltage, and the fourth source/drain electrode of the second transistor is electrically connected to a light emitting diode. One end of the capacitor is electrically connected to the second gate electrode. The material of the dielectric layer of the capacitor is different from the material of the gate dielectric of one of the first transistor and the second transistor. | 2009-12-10 |
20090305477 | INTEGRATED CIRCUIT ARRANGEMENT WITH NPN AND PNP BIPOLAR TRANSISTORS AND CORRESPONDING PRODUCTION METHOD - An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout. | 2009-12-10 |
20090305478 | METHOD FOR MANUFACTURING CAPACITOR OF SEMICONDUCTOR DEVICE - A method for manufacturing a capacitor of a semiconductor device includes forming a lower metal layer over a substrate, forming a dielectric layer over the lower metal layer, forming an upper metal layer over the dielectric layer, forming an upper electrode and a dielectric layer pattern by performing a reactive ion etching process with respect to the upper metal layer using the dielectric layer as an etch stop layer, and exposing a top surface of the lower metal layer, and performing a chemical down-stream etch (CDE) process to remove a by-product of a sidewall of the upper electrode. | 2009-12-10 |
20090305479 | CONVENTIONALLY PRINTABLE NON-VOLATILE PASSIVE MEMORY ELEMENT AND METHOD OF MAKING THEREOF - A non-volatile passive memory element comprising on a single surface a first electrode system and a second electrode system together with an insulating system, unless the insulating system is the surface, wherein the first electrode system is insulated from the second electrode system, the first and the second electrode systems are pattern systems and at least one conductive or semiconducting bridge is present between the first and second electrode systems, and wherein the non-volatile passive memory device is exclusive of metallic silicon and the systems and the conductive or semiconducting bridges are printable using conventional printing processes with the optional exception of the insulating system if the insulating system is the surface. A non-volatile passive memory device comprising a support and on at least one side of the support the above-mentioned non-volatile passive memory element. A process for providing the above-mentioned non-volatile passive memory device, comprising the realization on a single surface of the support of the steps of: providing a first electrode system pattern, optionally providing an insulating pattern, providing a second electrode system pattern, and providing at least one conductive or semiconducting bridge between the first electrode system pattern and the second electrode system pattern at predesignated points, wherein at least one of the steps is realized with a conventional printing process and two of said steps are optionally performed simultaneously. | 2009-12-10 |
20090305480 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND STORAGE MEDIUM - A method of manufacturing a semiconductor device, including an interlayer insulating layer having a dielectric constant of about 1, includes at least one of hydrophobically modifying an interlayer insulating film for insulating lines from each other, before forming air gaps in the interlayer insulating film, and hydrophobically modifying the lines, after forming the air gaps in the interlayer insulating film. | 2009-12-10 |
20090305481 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - Disclosed are methods for manufacturing a semiconductor memory device. According to an embodiment, a method includes forming a trench to form an isolation layer performing an annealing process to reduce an amount of a leakage current in an active layer, and performing a gap-fill process with respect to the trench. Another method in accordance with an embodiment includes performing a lithography process to form an active layer, in which a line critical dimension (CD) in the active layer is increased by about 3 nm to about 6 nm as compared with a line CD in a Process of Record (POR). | 2009-12-10 |
20090305482 | SYSTEMS, DEVICES, AND METHODS FOR SEMICONDUCTOR DEVICE TEMPERATURE MANAGEMENT - Devices, systems, and methods for semiconductor die temperature management are described and discussed herein. An IC device is described that includes at least one intra-die cooling structure. In an embodiment, the IC device includes a semiconductor die formed of integral device layers and further includes at least one coolant reservoir and at least one coolant channel. In an embodiment, the at least one coolant reservoir and at least one coolant channel are disposed wholly within the semiconductor die. In various embodiments, at least one coolant reservoir and at least one coolant channel are constructed and arranged to circulate coolant fluid in proximity to at least one IC device structure in order to decrease and or normalize an operating temperature of the IC device. In other embodiments, systems and methods for designing and/or fabricating IC die that include at least one intra-die cooling structure are provided herein. | 2009-12-10 |
20090305483 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - One surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region in the single crystal semiconductor substrate. An insulating layer is formed over the one surface of the single crystal semiconductor substrate. A surface of a substrate having an insulating surface and a surface of the insulating layer are disposed in contact with each other to bond the substrate having the insulating surface and the single crystal semiconductor substrate to each other. Heat treatment is performed to divide the single crystal semiconductor substrate along the damaged region and to form a semiconductor layer over the substrate having the insulating surface. One surface of the semiconductor layer is irradiated with light from a flash lamp under conditions where the semiconductor layer is not melted, to repair a defect. | 2009-12-10 |
20090305484 | METHOD AND REACTOR FOR GROWING CRYSTALS - The reactor for growing crystals on substrates comprises a reaction chamber, support for at least one seed, inlet means for at least one reaction gas, inlet for combustion gasses and means for triggering combustion between said combustion gasses. The growth of a crystal on a seed located inside the reaction chamber comprises the steps of introducing at least one reaction gas into the reaction chamber, introducing combustion gasses into the reaction chamber, triggering combustion between the combustion gasses and depositing the material so generated on the seed. | 2009-12-10 |
20090305485 | Method For Producing Semiconductor Substrate - The present invention is a method for producing a semiconductor substrate, including steps of forming a SiGe gradient composition layer and a SiGe constant composition layer on a Si single crystal substrate, flattening a surface of the SiGe constant composition layer, removing a natural oxide film on the flattened surface of the SiGe constant composition layer, and forming a strained Si layer on the surface of the SiGe constant composition layer from which the natural oxide film has been removed, wherein the formation of the SiGe gradient composition layer and the formation of the SiGe constant composition layer are performed at a temperature T | 2009-12-10 |
20090305486 | METHOD FOR PRODUCING A SEMICONDUCTOR LAYER - A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate. | 2009-12-10 |
20090305487 | NON-VOLATILE RESISTANCE SWITCHING MEMORY - A microelectronic device or non-volatile resistance switching memory comprising the switching material for storing digital information. A process includes a step of depositing the switching material by a CMOS deposition technique at a temperature lower than 400° C. | 2009-12-10 |
20090305488 | METHOD OF PRODUCING AN EPITAXIAL LAYER ON SEMICONDUCTOR SUBSTRATE AND DEVICE PRODUCED WITH SUCH A METHOD - The invention relates to the manufacture of an epitaxial layer, with the following steps: providing a semiconductor substrate; providing a Si—Ge layer on the semiconductor substrate, having a first depth; —providing the semiconductor substrate with a doped layer with an n-type dopant material and having a second depth substantially greater than said first depth; performing an oxidation step to form a silicon dioxide layer such that Ge atoms and n-type atoms are pushed into the semiconductor substrate by the silicon dioxide layer at the silicon dioxide/silicon interface, wherein the n-type atoms are pushed deeper into the semiconductor substrate than the Ge atoms, resulting in a top layer with a reduced concentration of n-type atoms; removing the silicon dioxide layer; growing an epitaxial layer of silicon on the semiconductor substrate with a reduced outdiffusion or autodoping. | 2009-12-10 |
20090305489 | MULTILAYER ELECTROSTATIC CHUCK WAFER PLATEN - This layered assembly utilizes two-piece construction, with an electrically nonconductive layer and a thermally conductive layer. Rather than using metal, the thermally conductive layer is made from a composite material, having both metal and a CTE modifying agent. This composite material may a coefficient of thermal expansion close to or identical to that of the nonconductive layer, thereby eliminating many of the drawbacks of the prior art. In one embodiment, the composite material is a mixture of aluminum and carbon (or graphite) fiber. In a further embodiment, one or more fluid conduits are placed in the mold before the layer is cast. These conduits serve as the fluid passageways in the electrostatic chuck. In another embodiment, the composite material is a mixture of a semiconductor material, such as silicon, and aluminum where the conduits are formed by machining and bonding. | 2009-12-10 |
20090305490 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes forming an electrically conductive pattern so as to overlap in a plan view with part of a semiconductor layer provided on a substrate, on the opposite side of the substrate side of the semiconductor layer; implanting an impurity into the semiconductor layer using the electrically conductive pattern as a mask; reducing a superimposed region that is a region where the electrically conductive pattern and the semiconductor layer overlap with each other in a plan view by removing part of the electrically conductive pattern after the implantation of the impurity; and implanting the impurity into the semiconductor layer using the electrically conductive pattern as a mask after the reduction of the superimposed region. | 2009-12-10 |
20090305491 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film. | 2009-12-10 |
20090305492 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 2009-12-10 |
20090305493 | ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION - An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature. | 2009-12-10 |
20090305494 | Bump structure for a semiconductor device and method of manufacture - A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive. | 2009-12-10 |
20090305495 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug. | 2009-12-10 |
20090305496 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided. | 2009-12-10 |
20090305497 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes: forming a first film pattern above a substrate; forming a plurality of second film patterns like sandwiching the first film pattern from both sides; forming a third film in such a way that an upper surface of the first film pattern and an upper surface and an exposed side surface of each of the plurality of second film patterns are coated with the third film; removing a portion of the third film until the upper surface of the first film pattern is exposed; removing, by a wet process, the first film pattern exposed after the portion of the third film is removed; and removing a remainder of the third film by a dry process after the first film pattern is removed. | 2009-12-10 |
20090305498 | SEMICONDUCTOR DEVICE COMPRISING A COPPER ALLOY AS A BARRIER LAYER IN A COPPER METALLIZATION LAYER - By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction. | 2009-12-10 |
20090305499 | INTRALEVEL CONDUCTIVE LIGHT SHIELD - A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield. | 2009-12-10 |
20090305500 | Contact Clean by Remote Plasma and Repair of Silicide Surface - Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface. | 2009-12-10 |
20090305501 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING A CHEMICAL MECHANICAL POLISHING PROCESS - A method of fabricating a semiconductor device by using a chemical-mechanical polishing (CMP) process includes forming an insulating layer on a semiconductor wafer, etching the insulating layer to form via-holes, and forming a conductive layer on the insulating layer to fill the via-holes. The method further includes performing a first polishing process to etch the conductive layer until an upper surface of the insulating layer is exposed,, performing a second polishing process to etch the insulating layer to a predetermined thickness and performing a third polishing process to remove protrusions of the conductive layer. | 2009-12-10 |
20090305502 | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 2009-12-10 |
20090305503 | Manufacturing Method of Semiconductor Device - A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 μm and equal to or less than 10 μm is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 μm and equal to or less than 10 μm to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed. | 2009-12-10 |
20090305504 | SINGLE PRECURSORS FOR ATOMIC LAYER DEPOSITION - Single precursors for use in flash ALD processes are disclosed. These precursors have the general formula: | 2009-12-10 |
20090305505 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a plurality bar patterns over an underlying layer. A spacer is formed at both sides of the bar patterns and the bar patterns are removed. The spacers are isolated by an exposing process to form a vernier pattern. The underlying layer is etched using the vernier pattern as an etching mask. | 2009-12-10 |
20090305506 | SELF-ALIGNED DUAL PATTERNING INTEGRATION SCHEME - A method of self-aligned dual patterning is described. The method includes first providing a substrate having a stack of films thereon. A template mask is then formed above the stack of films. A liner layer is formed above the stack of films and conformal with the template mask. A spacer-forming material layer is formed over and conformal with the liner layer. The spacer-forming material layer is then etched to form a spacer mask and to exose a portion of the liner layer. The exposed portion of the liner layer and the template mask are then removed. Finally, an image of the spacer mask is transferred to the stack of films. | 2009-12-10 |
20090305507 | Method of processing solid surface with gas cluster ion beam - A solid surface is processed while corner portions of a relief structure are protected from deformation. A method of processing a solid surface with a gas cluster ion beam includes a cluster protection layer formation step of forming, on the solid surface, a relief structure having protrusions with a cluster protection layer formed to cover an upper part thereof and recesses without the cluster protection layer; an irradiation step of emitting a gas cluster ion beam onto the solid surface having the relief structure formed in the cluster protection layer formation step; and a removal step of removing the cluster protection layer. A thickness T of the cluster protection layer satisfies | 2009-12-10 |
20090305508 | INTEGRATED CIRCUIT WITH UPSTANDING STYLUS - A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer. | 2009-12-10 |
20090305509 | Showerhead electrode assemblies for plasma processing apparatuses - Showerhead electrode assemblies are disclosed, which include a showerhead electrode adapted to be mounted in an interior of a vacuum chamber; an optional backing plate attached to the showerhead electrode; a thermal control plate attached to the backing plate or to the showerhead electrode at multiple contact regions across the backing plate; and at least one interface member separating the backing plate and the thermal control plate, or the thermal control plate and showerhead electrode, at the contact regions, the interface member having a thermally and electrically conductive gasket portion and a particle mitigating seal portion. Methods of processing semiconductor substrates using the showerhead electrode assemblies are also disclosed. | 2009-12-10 |
20090305510 | Method of Etching a Material Surface - Disclosed is a method of structuring a material surface by dry etching, so that a passivation layer soluble in a solvent forms by the dry etching on parts of the structured material surface, sealing the passivation layer with a substance soluble in the solvent, and removing the sealed passivation layer and the substance by means of the solvent. | 2009-12-10 |
20090305511 | Methods of Treating Semiconductor Substrates, Methods Of Forming Openings During Semiconductor Fabrication, And Methods Of Removing Particles From Over Semiconductor Substrates - Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath. | 2009-12-10 |
20090305512 | Substrate Processing Apparatus and Substrate Processing Method - The present invention is a substrate processing apparatus including: a holder that holds substrates in a tier-like manner; a processing container that contains the holder and that conducts a predetermined thermal process to the substrates in a process-gas atmosphere under a predetermined temperature and pressure; a gas-introducing part that introduces a process gas into the processing container; a gas-discharging part that discharges a gas from the processing container to create a predetermined vacuum pressure therein; and a heating part that heats the processing container; wherein the holder is provided with baffle plates each of which forms a processing space for each substrate when the holder is contained in the processing container; the gas-introducing part is provided with gas introduction holes disposed at one lateral side of the respective processing spaces; and the gas-discharging part is provided with gas discharge holes disposed at the other lateral side of the respective processing spaces, oppositely to the gas introduction holes. | 2009-12-10 |
20090305513 | Material deposition over template - Embodiments of the invention relate to a method of functional materials deposition using a polymer template fabricated on a substrate. Such template forms an exposed and masked areas of the substrate material, and can be fabricated using polymer resists or Self-assembled monolayers. Deposition is performed using an applicator, which is fabricated in the shape of cylinder or cone made of soft elastomeric materials or laminated with soft elastomeric film. Functional materials, for example, metals, semiconductors, sol-gels, colloids of particles are deposited on the surface of applicator using liquid immersion, soaking, contact with wetted surfaces, vapor deposition or other techniques. Then wetted applicator is contacted the surface of the polymer template and rolled over it's surface. During this dynamic contact functional material is transferred selectively to the areas of the template. Patterning of functional material is achieved by lift-off of polymeric template after deposition. According to another embodiment, where self-assembled monolayers are used as template, selective deposition of functional materials is achieved either due to low surface energy of SAM or reactivity of terminal groups. | 2009-12-10 |
20090305514 | METHOD OF MODIFYING INTERLAYER ADHESION - Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less. | 2009-12-10 |
20090305515 | METHOD AND APPARATUS FOR UV CURING WITH WATER VAPOR - Embodiments of the invention generally relate to a method and apparatus for curing dielectric material deposited in trenches or gaps in the surface of a substrate to produce a feature free of voids and seams. In one embodiment, the dielectric material is steam annealed while being exposed to ultraviolet radiation. In one embodiment, the dielectric material is further thermally annealed in a nitrogen environment. | 2009-12-10 |
20090305516 | METHOD FOR PURIFYING ACETYLENE GAS FOR USE IN SEMICONDUCTOR PROCESSES - Acetylene is treated to remove some residual storage solvent that may be present with the acetylene in a source of acetylene such as a container. Such treatment may be performed prior to supplying the acetylene to a deposition chamber or other reactor where acetylene is a reactant. After treatment, the acetylene gas stream has a relatively constant concentration of storage solvent, regardless of how much acetylene has been released from the acetylene source. The treatment may involve condensing the storage solvent from the gas stream at a certain temperature and separating the storage solvent from the gas stream. | 2009-12-10 |
20090305517 | Method of Manufacturing Semiconductor Device and Substrate Processing Apparatus - A method of manufacturing a semiconductor device has: carrying a substrate into a process chamber; depositing a thin film on the substrate by supplying inside the process chamber a first film deposition gas including at least one element among plural elements forming a thin film to be deposited and capable of accumulating a film solely and a second film deposition gas including at least another element among the plural elements and incapable of accumulating a film solely; carrying the substrate on which is deposited the thin film out from inside the process chamber; and removing a first sediment adhering to an interior of the process chamber and a second sediment adhering to an interior of the supply portion and having a chemical composition different from a chemical composition of the first sediment by supplying cleaning gases inside the process chamber and inside a supply portion that supplies the first film deposition gas while changing at least one of a supply flow rate, a concentration, and a type between a cleaning gas to be supplied inside the process chamber and a cleaning gas to be supplied inside the supply portion. | 2009-12-10 |