49th week of 2015 patent applcation highlights part 66 |
Patent application number | Title | Published |
20150348616 | TRACKING SIGNALS IN MEMORY WRITE OR READ OPERATION - A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit. The delay circuit is coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit, and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal. | 2015-12-03 |
20150348617 | HIGHLY COMPACT NON-VOLATILE MEMORY AND METHOD THEREOF - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness. | 2015-12-03 |
20150348618 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 2015-12-03 |
20150348619 | DETERMINING SOFT DATA - The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell. | 2015-12-03 |
20150348620 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell. | 2015-12-03 |
20150348621 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD THEREOF - This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of NAND cell units arranged therein, each of the NAND cell units being configured having a plurality of memory cells connected in series therein. A bit line is connected to one end of the NAND cell unit, and a source line is connected to the other end of the NAND cell unit. A sense amplifier circuit is connected to the bit line. The sense amplifier circuit comprises: a first switch circuit connected between a power supply voltage terminal and a sense node; a sense amplifier connected to the sense node; and a latch circuit that latches a signal outputted from the sense amplifier. The first switch circuit is configured to switch to a non-conductive state according to data latched by the latch circuit. | 2015-12-03 |
20150348622 | RESISTIVE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME - A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer. | 2015-12-03 |
20150348623 | APPARATUSES AND METHODS FOR DETECTING WRITE COMPLETION FOR RESISTIVE MEMORY - Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability. | 2015-12-03 |
20150348624 | METHOD FOR IMPROVING SENSING MARGIN OF RESISTIVE MEMORY - A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously. | 2015-12-03 |
20150348625 | RESISTANCE CHANGE TYPE MEMORY - A resistance change type memory includes a memory cell including a first resistance change element as a memory element; a reference cell including a second resistance change element and a first element having a resistance value which is not higher than a resistance range of the first and second resistance change elements; and a read circuit including a first input terminal connected to the memory cell, and a second input terminal connected to the reference cell. | 2015-12-03 |
20150348626 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device. | 2015-12-03 |
20150348627 | CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE - A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices. | 2015-12-03 |
20150348628 | SEMICONDUCTOR INTEGRATED CIRCUIT - A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor. | 2015-12-03 |
20150348629 | Non-Volatile Ternary Content-Addressable Memory with Resistive Memory Device - A scheme for non-volatile ternary content-addressable memory with resistive memory device is proposed. The non-volatile ternary content-addressable memory comprises five transistors including a pair of search transistors with a first search transistor and a second search transistor, a read transistor, a write transistor and a match line transistor, wherein a match line is coupled to the match line transistor; and a pair of variable resistances have a first variable resistance and a second variable resistance. The pair of search transistors is coupled to the pair of variable resistances. | 2015-12-03 |
20150348630 | NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A non-volatile memory device includes a first word line, a second word line, first memory cells, second memory cells, and an address decoder. The second word line is adjacent to the first word line. The first memory cells are connected to the first word line. The second memory cells are connected to the second word line. The second memory cells are connected to the first memory cells, respectively. The address decoder applies a first voltage to the first word line and applies a second voltage to the second word line in an over program period of the first memory cells. The first voltage is higher than a program voltage of the first and second memory cells. The second voltage is lower than a pass voltage of the first and second memory cells. | 2015-12-03 |
20150348631 | NONVOLATILE MEMORY, NONVOLATILE PROGRAMMABLE LOGIC SWITCH INCLUDING NONVOLATILE MEMORY, AND NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile memory according to an embodiment includes a memory cell, the memory cell including: a memory transistor including a source, a drain, a gate electrode disposed above a channel between the source and the drain, and a gate insulating film disposed between the channel and the gate electrode; and a fuse element disposed between the gate electrode and a wiring line to which the gate electrode of the memory transistor is connected. | 2015-12-03 |
20150348632 | MITIGATION OF DATA RETENTION DRIFT BY PROGRAMMING NEIGHBORING MEMORY CELLS - A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group. | 2015-12-03 |
20150348633 | NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation. | 2015-12-03 |
20150348634 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF - A semiconductor memory device includes a plurality of memory cells coupled between a source line and a bit line, a voltage generation circuit suitable for applying an erase voltage to the source line during an erase operation, and a read and to circuit coupled to the bit line through a selection transistor and suitable for applying an operating voltage to a first node of the selection transistor during the erase operation. | 2015-12-03 |
20150348635 | METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY CELL COMPRISING A SHARED SELECT TRANSISTOR GATE - The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state. | 2015-12-03 |
20150348636 | OPERATING METHODS OF NONVOLATILE MEMORY DEVICES - Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage. | 2015-12-03 |
20150348637 | NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings. | 2015-12-03 |
20150348638 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device and a method of operating the same are provided. The semiconductor device includes a memory block including a plurality of pages having a plurality of first cells and a plurality of second cells, a circuit group configured to read first cells and second cells of a selected page of the pages, a strobe signal control circuit configured to store source bouncing information generated during a read operation of the first cells of the selected page and output a strobe signal based on stored information, and a control circuit configured to control the circuit group in response to the strobe signal during a read operation of the second cells of the selected page. | 2015-12-03 |
20150348639 | CELL STRING AND READING METHOD FOR THE CELL STRING - Provided are a cell string and a reading method for the cell string. The cell string includes a semiconductor body formed on a surface of an insulating layer, first and second semiconductor regions formed at respective ends of the semiconductor body and are formed by being doped with different types of impurities, two or more control electrodes which are separated from each other to be electrically isolated, and a gate insulating film stack which is formed between the semiconductor body and the control electrodes, wherein the semiconductor body is configured to include at least two layers, and adjacent layers of the semiconductor body have different energy band gaps, wherein the semiconductor body is formed by an intrinsic semiconductor or a semiconductor being doped with impurities, and wherein the first and second semiconductor regions are doped with impurities of which concentration is higher than that of the semiconductor body. | 2015-12-03 |
20150348640 | DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASE TRANSISTOR - The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer. | 2015-12-03 |
20150348641 | SEMICONDUCTOR MEMORY DEVICE WITH POWER INTERRUPTION DETECTION AND RESET CIRCUIT - A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric charge. A first discharge circuit is connected to a charge storage node of the charge circuit and discharges the stored electric charge when the control signal is activated. A second discharge circuit discharges the first node when the charge storage node has a potential exceeding a predetermined potential. | 2015-12-03 |
20150348642 | Storage Device and Method for Performing a Self-Refresh Operation - A storage device and method for performing a self-refresh operation are disclosed. In one embodiment, a storage device determines that the self-refresh operation needs to be performed. In response to that determination, the storage device performs the self-refresh operation by reading data from the memory and writing the data back to the memory without transferring the data outside of the storage device. | 2015-12-03 |
20150348643 | DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE - A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window. | 2015-12-03 |
20150348644 | READOUT OF INTERFERING MEMORY CELLS USING ESTIMATED INTERFERENCE TO OTHER MEMORY CELLS - A method includes storing data in a memory that includes multiple analog memory cells. After storing the data, an interference caused by a first group of the analog memory cells to a second group of the analog memory cells is estimated. The data stored in the first group is reconstructed based on the estimated interference caused by the first group to the second group. | 2015-12-03 |
20150348645 | RELIABLE READOUT OF FUSE DATA IN AN INTEGRATED CIRCUIT - An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses. | 2015-12-03 |
20150348646 | SHIFT REGISTER AND METHOD OF DRIVING THE SAME, AND GROUP OF SHIFT REGISTERS AND METHOD OF DRIVING THE SAME - A shift register circuit is disclosed. In some embodiments, the shift register circuit includes six transistors and no capacitors. A group of such shift register circuits is also disclosed. In some embodiments, the shift registers of the group are connected so as to be configured to provide driving signals for a display. A method of using the shift registers is also disclosed. | 2015-12-03 |
20150348647 | VIA STACK FAULT DETECTION - A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. A via on the selected die can be coupled to ground. A supply voltage is coupled to an end of the via stack and a resulting current measured. A calculated resistance is compared to an expected resistance to determine if a fault exists in the via stack. | 2015-12-03 |
20150348648 | APPARATUS FOR MEASURING SIGNAL SKEW OF ASYNCHRONOUS FLASH MEMORY CONTROLLER - A method of measuring skew between signals from an asynchronous integrated flash memory controller (IFC) includes connecting input/output (I/O) pins of the IFC to cycle based test equipment (ATE). The ATE applies a pattern of test signals as input drive to the IFC. Relative to the test cycle, the earliest delay time at which output signals from all of the I/O pins first correspond with expected results, and the latest delay time at which the output signals still correspond with the expected results are measured. The difference between the latest and the earliest delay times is compared with a limit value and a comparison report is generated. | 2015-12-03 |
20150348649 | BIT ERROR RATE MAPPING IN A MEMORY SYSTEM - A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program. | 2015-12-03 |
20150348650 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor system includes: a memory controller; and a memory which determines whether to enable a control signal in response to block mode entry signals applied from the memory controller, enters a repair mode in response to a first address and a first command applied from the memory controller, and blocks an entry to the repair mode during an enabling section of the control signal. | 2015-12-03 |
20150348651 | MULTIPLE ACCESS TEST ARCHITECTURE FOR MEMORY STORAGE DEVICES - A new architecture for use with computer memory storage devices is disclosed that provides means by which a memory storage device may be accessed both as standard archive file device as well as in any unique physical and native command set modes supported by the device. A system architecture for accessing a memory storage device that provides access to the storage device via a standard memory storage method while alternatively providing direct access to the full physical and functional capabilities of the storage device. The system architecture has four main elements. Firstly, a central processing system which acts as the user interface and controls access to all attached peripheral functions. Secondly, an electronic bridge connected on one side to the central processing system via a standard I/O channel and on the other side to the memory device through a memory bridge presenting the memory device to the central processing system as a standard memory peripheral. Thirdly, a second processing unit which on one side is connected to the central processing system and on the other side is connected to the memory storage device via the multiplexer thus providing the second processing unit direct access to the memory storage device. And finally, the multiplexer that can connect either the electronic memory bridge or the second processing system to the memory storage device. | 2015-12-03 |
20150348652 | DEPOSITION OF A PROTECTIVE COATING INCLUDING METAL-CONTAINING AND CHROMIUM-CONTAINING LAYERS ON ZIRCONIUM ALLOY FOR NUCLEAR POWER APPLICATIONS - The invention relates to compositions and methods for coating a zirconium alloy cladding of a fuel element for a nuclear water reactor. The coating includes a first tier or layer and a second tier or layer. The first layer includes an elemental metal and the second layer is an oxidation-resistant layer that includes elemental chromium. The first layer serves as an intermediate layer between the zirconium alloy substrate and the second layer. This intermediate layer can be effective to improve adhesion of the second layer to the zirconium alloy substrate. The multilayer coating forms a protective layer which provides improved capability for the zirconium alloy cladding to withstand normal and accident conditions to which it is exposed in the nuclear reactor. | 2015-12-03 |
20150348653 | MAGNETIC JACK TYPE IN-VESSEL CONTROL ELEMENT DRIVE MECHANISM - A magnetic jack type in-vessel control element drive mechanism includes: an upper coil assembly which includes a first sleeve configured to coaxially wrap a control element drive shaft, a first coil, and a first coil housing which is externally coupled to the first sleeve; a lower coil assembly which includes a second sleeve configured to coaxially wrap the control element drive shaft, a second coil, and a second coil housing which is externally coupled to the second sleeve, wherein the lower coil assembly is located under the upper coil assembly, a connecting member which connects the upper coil assembly and the lower coil assembly; a support tube which extends downward from the lower coil assembly; a motor assembly which is located between the control element drive shaft, and the first and second sleeves; and an anti-separation cap which prevents separation of the motor assembly. | 2015-12-03 |
20150348654 | Organically Cooled Nuclear Reactor for Enhanced Economics and Safety - An organically cooled nuclear reactor comprises fissionable fuel pellets and a neutron-moderator matrix in which the fissionable fuel pellets are distributed. The neutron-moderator matrix also defines coolant channels for flow of an organic coolant. | 2015-12-03 |
20150348655 | STABILITY COMPUTATION MONITORING DEVICE, REACTOR POWER STABILITY MONITORING SYSTEM AND REACTOR POWER STABILITY MONITORING METHOD - According to one embodiment, a stability computation monitoring device monitors in real time reactor power oscillation based on signals from neutron detectors. The device has: a detection sampling section sampling signals from the plurality of neutron detectors to output a detection sampling signal for each neutron detector; a local power monitoring section converting the detection sampling signal into a neutron flux signal; a low-pass filter applying low-pass filtering to neutron flux signal; a down-sampling section performing down-sampling for the neutron flux signals that have passed through the low-pass filter at a period longer than the detection sampling period; a wavelet transformation section applying Discrete Wavelet transformation to the neutron flux signals that have been subjected to the down-sampling to compute a DWT wavelet coefficient of each level; and a monitoring section monitoring the wavelet coefficient computed by the wavelet transformation section. | 2015-12-03 |
20150348656 | NEUTRON FLUX LEVEL MEASUREMENT SYSTEM, NEUTRON FLUX LEVEL COMPUTING DEVICE AND NEUTRON FLUX LEVEL MEASUREMENT METHOD - According to one embodiment, a neutron flux level computing component has: an analog signal processing system that amplifies an AC component of a detector output signal from a neutron detector and performs filtering for removal of a high-frequency component; a digitization system that converts, at a certain sampling period, an output signal from the analog signal processing system into a digital time-series signal; a wavelet analysis system that performs discrete wavelet transformation using the digital time-series signal to compute a wavelet coefficient; and a digital signal processing system that computes a mean square value of the wavelet coefficients and converts the computed mean square value into a neutron flux level value. | 2015-12-03 |
20150348657 | ANCHOR DEVICE AND NUCLEAR FACILITY COMPRISING SUCH AN ANCHOR DEVICE - An anchor device and a nuclear facility comprising such an anchor device are provided. This anchor device comprises a female part and a male part, the female part comprising a groove extending along a longitudinal axis, the groove having a width which decreases longitudinally and a transverse section, the male part comprising a slider with a shape mating that of the groove and able to be longitudinally inserted into the groove, the transverse section of the groove being configured so as to prevent the extraction of the slider out of the groove transversely to the longitudinal axis. The anchor device comprises a locking device able to prevent the slider from longitudinally sliding out of the groove. | 2015-12-03 |
20150348658 | NOZZLE REPAIR METHOD AND NUCLEAR REACTOR VESSEL - A nozzle repair method and a nuclear reactor vessel include: removing a trepanning portion ( | 2015-12-03 |
20150348659 | WATER JET PEENING APPARATUS AND WATER JET PEENING METHOD - Provided is a water jet peening apparatus and a water jet peening method including: a clamping cylinder ( | 2015-12-03 |
20150348660 | Radiation Shielding and Processes for Producing and Using the Same - Lead-free radiation shielding material and processes for producing and using the same are described. The radiation shielding comprising a heavy metal component, such as bismuth, and a polymer component while also being optically transparent. The bismuth can be bonded to the polymer component or can be embedded within the matrix of the polymer component without being bonded to the polymer. As well, the bismuth can be nanoparticles that are contained within the matrix of the polymer component without being bonded to the polymer. The bismuth provides a stable, environmentally benign alternative to lead, while blocking the radiation and also being optically transparent. Other embodiments are described. | 2015-12-03 |
20150348661 | VITRIFIED CHEMICALLY BONDED PHOSPHATE CERAMICS FOR IMMOBILIZATION OF RADIOISOTOPES - A method of immobilizing a radioisotope and vitrified chemically bonded phosphate ceramic (CBPC) articles formed by the method are described. The method comprises combining a radioisotope-containing material, MgO, a source of phosphate, and optionally, a reducing agent, in water at a temperature of less than 100° C. to form a slurry; curing the slurry to form a solid intermediate CBPC article comprising the radioisotope therefrom; comminuting the intermediate CBPC article, mixing the comminuted material with glass frits, and heating the mixture at a temperature in the range of about 900 to about 1500° C. to form a vitrified CBPC article comprising the radioisotope immobilized therein. | 2015-12-03 |
20150348662 | PROCESS AND APPARATUS FOR SEPARATION OF TECHNETIUM-99M FROM MOLYBDATE - Systems and methods for separation or isolation of technetium radioisotopes from aqueous solutions of radioactive or non-radioactive molybdate salts using a polyalkyl glycol-based cross-linked polyether polymer. Some embodiments can be used for the effective purification of radio-active technetium-99m produced from low specific activity | 2015-12-03 |
20150348663 | METHOD OF PRODUCING ISOTOPES IN POWER NUCLEAR REACTORS - In a method of producing isotopes in a light water power reactor, one or more targets within the reactor may be irradiated under a neutron flux to produce one or more isotopes. The targets may be assembled into one or more fuel bundles that are to be loaded in a core of the reactor at a given outage. Power operations in the reactor irradiate the fuel bundles so as to generate desired isotopes, such as one or more radioisotopes at a desired specific activity or stable isotopes at a desired concentration. | 2015-12-03 |
20150348664 | COPPER ALLOY FOR ELECTRONIC AND ELECTRIC DEVICES, COMPONENT FOR ELECTRONIC AND ELECTRIC DEVICES, AND TERMINAL - A copper alloy for electronic and electric devices has a composition in which the amount of Zr is in a range of 0.05% by mass to 0.15% by mass, the amount of Ca is in a range of 0.001% by mass to less than 0.08% by mass, the amount of Pb is less than 0.05% by mass, the amount of Bi is less than 0.01% by mass, and the balance Cu and inevitable impurities, the ratio Zr/Ca of the amount of Zr to the amount of Ca is 1.2 or more, the copper alloy includes two-phase particles made up of two phases of a phase containing Cu and Zr as main components and a phase containing Cu and Ca as main components and single-phase particles made of a single phase containing Cu and Zr as main components, and the conductivity is more than 88% IACS. | 2015-12-03 |
20150348665 | COPPER ALLOY FOR ELECTRIC AND ELECTRONIC DEVICE, COPPER ALLOY SHEET FOR ELECTRIC AND ELECTRONIC DEVICE, CONDUCTIVE COMPONENT FOR ELECTRIC AND ELECTRONIC DEVICE, AND TERMINAL - The present invention relates to a copper alloy for electric and electronic device, a copper alloy sheet for electric and electronic device, a conductive component for electric and electronic device, and a terminal. The copper alloy for electric and electronic device comprises more than 2.0 mass % and less than 23.0 mass % of Zn; 0.10 mass % to 0.90 mass % of Sn; 0.05 mass % to less than 1.00 mass % of Ni; 0.001 mass % to less than 0.100 mass % of Fe; 0.005 mass % to 0.100 mass % of P; and a balance including Cu and unavoidable impurities, in which 0.002≦Fe/Ni<1.500, 3.0<(Ni+Fe)/P<100.0, and 0.102015-12-03 | |
20150348666 | GRAPHENE, COMPOSITION FOR PREPARING GRAPHENE, AND METHOD OF PREPARING GRAPHENE USING THE COMPOSITION - Graphene, a composition for preparing graphene, and a method of preparing graphene using the composition are disclosed. | 2015-12-03 |
20150348667 | Carbon Nanotube-Graphene Hybrid Transparent Conductor and Field Effect Transistor - A nanotube-graphene hybrid film and method for forming a cleaned nanotube-graphene hybrid film. The nanotube-graphene hybrid film includes a substrate; nanotube film deposited over the substrate to produce a layer of nanotube film; and graphene deposited over the layer of nanotube film to produce a nanotube-graphene hybrid film. | 2015-12-03 |
20150348668 | NON-METALLIC LIGHT CONDUCTIVE WIRE AND ITS METHOD AND APPLICATION PRODUCTS - The invention discloses a non-metallic light weight conductive wire, a composite conductive wire, a special cable, a motor and the like application products made of the conductive wire, and a method of making the composite conductive wire. The invention has the advantages of novel structure and simple operation, and is easy for large scale industrialized production. Application of the conductive wire produced by the invention in fields of motor manufacturing, aerospace and the like helps drastically reduce the weight of wire. | 2015-12-03 |
20150348669 | Graphene/Graphite Polymer Composite Foam Derived From Emulsions Stabilized by Graphene/Graphite Kinetic Trapping - The present disclosure provides advantageous graphene/graphite stabilized composites (e.g., graphene/graphite stabilized emulsion-templated foam composites), and improved methods for fabricating such graphene/graphite stabilized composites. More particularly, the present disclosure provides improved methods for fabricating pristine, graphene/graphite/polymer composite foams derived from emulsions stabilized by graphene/graphite kinetic trapping. In exemplary embodiments, the present disclosure provides that, instead of viewing the insolubility of pristine graphene/graphite as an obstacle to be overcome, it is utilized as a means to create or fabricate water/oil emulsions, with graphene/graphite stabilizing the spheres formed. These emulsions are then the frameworks used to make foam composites that have shown bulk conductivities up to about 2 S/m, as well as compressive moduli up to about 100 MPa and breaking strengths of over 1200 psi, with densities as low as about 0.25 g/cm | 2015-12-03 |
20150348670 | CURABLE ANTISTATIC ORGANOPOLYSILOXANE COMPOSITION AND ANTISTATIC SILICONE FILM - A curable antistatic organopolysiloxane composition capable of alleviating problems originating from amine compounds and problems originating from water and an antistatic silicone film formed by curing said composition is provided. The curable antistatic organopolysiloxane composition includes: (I) a conductive polymer composition which is pseudo-solubly dispersed in a solvent consisting mainly of an organic solvent and which includes (a) a π-conjugated conductive polymer, (b) polyanions doping the π-conjugated conductive polymer (a), and (c) a reaction product of those anions of the polyanions (b) that were not needed for doping, and an oxirane group and/or oxetane group-containing organic compound; and (II) a curable organopolysiloxane composition including an antistatic silicone film which is formed by supplying said composition onto a substrate and curing the same. | 2015-12-03 |
20150348671 | CONDUCTIVE COMPOSITION, CONDUCTIVE COMPOSITION PRODUCTION METHOD, ANTI-STATIC RESIN COMPOSITION AND ANTISTATIC RESIN FILM - A transparent conductive film with fewer problems originating from amine compounds is provided using a conductive composition stably and pseudo-solubly dispersed in a solvent consisting mainly of an organic solvent. This invention relates to: a conductive composition which is pseudo-solubly dispersed in a solvent consisting mainly of an organic solvent and which contains (a) a π-conjugated conductive polymer, (b) polyanions doping the π-conjugated conductive polymer (a), and (c) a reaction product of those anions of the polyanions (b) that were not needed for doping, and an oxirane group- and/or oxetane group-containing organic compound; a production method of said conductive composition; an anti-static resin composition formed by mixing said conductive composition and a resin solution dissolved in an organic solvent; and antistatic resin film formed by curing said antistatic resin composition. | 2015-12-03 |
20150348672 | DIELECTRIC GLASS COMPOSITION - A dielectric glass composition suitable for use in an electronic device which comprises a sufficient amount of silicon dioxide to impart durability to the glass composition when subject to a humid environment, and one or more alkali metal oxides, wherein (i) the total content of the alkali metal oxides is at least about 10 wt % and no more than about 35 wt %, based upon 100% total weight of the glass composition, (ii) the median particle size (d | 2015-12-03 |
20150348673 | Mobile electronic device - A mobile electronic device comprising at least one part made of a polymer composition [composition (C), herein after] comprising at least one part made of a polymer composition [composition (C), herein after] comprising from at least one polyaryletherketone polymer [(PAEK) polymer], and at least one nitride (NI) of an element having an electronegativity (∈) of from 1.3 to 2.5, as defined in <>, CRC Press, 64 | 2015-12-03 |
20150348674 | TRANSMISSION CABLE - According to one embodiment, a transmission cable in one embodiment generally includes at least two cables. Each of the cables includes a central conductor including an axis and an outer circumference and an insulator covering the outer circumference of the central conductor, and including an insulation surface and grooves in the insulation surface. | 2015-12-03 |
20150348675 | SILVER NANOWIRE THIN FILM, MANUFACTURING METHOD THEREOF, AND ARRAY SUBSTRATE AND DISPLAY DEVICE - A silver nanowire thin film comprising a silver nanowire layer formed over a base substrate and a protective layer formed over the silver nanowire layer. A method for manufacturing the silver nanowire thin film comprising: forming a silver nanowire layer over a base substrate; forming a protective layer over the silver nanowire layer; forming a pattern of the silver nanowire layer covered with the protective layer thereon through a patterning process. An array substrate and a display device are further provided. | 2015-12-03 |
20150348676 | HIGH DENSITY SHIELDED ELECTRICAL CABLE AND OTHER SHIELDED CABLES, SYSTEMS, AND METHODS - A shielded electrical ribbon cable includes conductor sets each including one or more insulated conductors, and a first and second shielding film on opposite sides of the cable. In transverse cross section, cover portions of the shielding films substantially surround each conductor set, and pinched portions of the films form pinched portions of the cable on each side of each conductor set. Dense packing is achieved while maintaining high frequency electrical isolation between conductor sets. When the cable is laid flat, a quantity S/Dmin is in a range from 1.7 to 2, where S is a center-to-center spacing between nearest insulated conductors of two adjacent conductor sets, and Dmin is the lesser of the outer dimensions of such nearest insulated conductors. Alternatively, a first and second conductor set each having only one pair of insulated conductors can satisfy a condition that Σ/σ | 2015-12-03 |
20150348677 | JACKETED TORQUE BALANCED ELECTROMECHANICAL CABLE - An electromechanical cable that is crush-resistant and torque balanced is provided as well as a method for manufacturing a crush-resistant and torque balance electromechanical cable. The cable can include a core having a conductor surrounded by a first jacket layer, a second jacket layer surrounding the first jacket layer, a first all tor layer surrounding second jacket layer, a third jacket layer surrounding the first armor layer, a second armor layer surrounding the third jacket layer, and a fourth jacket layer surrounding the second armor layer. The first armor layer can be constructed as a plurality of wires and compressed partially into the second jacket layer. The second armor layer can be constructed from a plurality of three-wire strands and/or single wires and compressed partially into the third jacket layer. The three-wire strands can symmetric or asymmetric and can be compacted or non-compacted. | 2015-12-03 |
20150348678 | STRUCTURALLY AUGMENTED CABLE - A coaxial cable comprises inner and outer conductors disposed along an elongate axis, a dielectric insulating material disposed between the inner and outer conductors, a compliant outer jacket disposed over the inner and outer conductors, and a reinforcing outer jacket disposed over the compliant inner jacket, the outer jacket being physically separate from the inner jacket and comprising on-axis and off-axis fibers disposed in a binding matrix, the outer jacket comprising more on-axis than off-axis fibers. | 2015-12-03 |
20150348679 | PRECURSOR WIRE FOR NB3AL SUPERCONDUCTING WIRE, NB3AL SUPERCONDUCTING WIRE, METHOD FOR PRODUCING PRECURSOR WIRE FOR NB3AL SUPERCONDUCTING WIRE, AND METHOD FOR PRODUCING NB3AL SUPERCONDUCTING WIRE | 2015-12-03 |
20150348680 | LOW AC LOSS HIGH TEMPERATURE SUPERCONDUCTOR TAPE - A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region. | 2015-12-03 |
20150348681 | COATED CONDUCTOR HIGH TEMPERATURE SUPERCONDUCTOR CARRYING HIGH CRITICAL CURRENT UNDER MAGNETIC FIELD BY INTRINSIC PINNING CENTERS, AND METHODS OF MANUFACTURE OF SAME - A coated conductor comprises a substrate supporting a ReBCO superconductor adapted to carry current in a superconducting state. The superconductor is characterized in having peaks in critical current (J | 2015-12-03 |
20150348682 | INTEGRATED SUPERCONDUCTOR DEVICE AND METHOD OF FABRICATION - An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region. | 2015-12-03 |
20150348683 | EDGE-WOUND RESISTOR, RESISTOR ASSEMBLY, AND METHOD OF MAKING SAME - A resistor, resistor assembly, and a method of making them are described, with advantages over existing resistors, resistor assemblies, and methods. The resistor includes a helical resistor element wound on an insulator. The insulator has a regularly spaced plurality of teeth on each of two opposite sides, with the helical resistor element situated within the teeth. The insulator provides support for the helical resistor element without use of a separate core within the insulator. The resistor may be assembled by inserting two toothed insulator pieces into a helical resistor element and separating the two insulator pieces such that turns of the helical resistor element are within the teeth of the first and second insulator pieces. Alternatively, the resistor may be assembled by winding a helical resistor element onto a toothed insulator piece. | 2015-12-03 |
20150348684 | MAGNETIC MATERIAL AND METHOD FOR PRODUCING MAGNETIC MATERIAL - An internal structure of a magnetic material is phase-separated into at least a first phase and a second phase. At least one of the first phase and the second phase includes a compound having a perovskite structure. The first phase and the second phase include Mn, Sn, and N. According to this, it is possible to obtain a magnetic material in which magnetic properties such as a coercive force are improved. In addition, in a case where a rare-earth element is not included in elements that constitute the magnetic material, it is possible to obtain a magnetic material having corrosion resistance. | 2015-12-03 |
20150348685 | Nd-Fe-B SINTERED MAGNET AND METHODS FOR MANUFACTURING THE SAME - A sintered neodymium-iron-boron magnet, the main components thereof comprising rare-earth elements R, additional elements T, iron Fe and boron B, and having a rare-earth-enriched phase and a main phase of a Nd2Fe14B crystal structure. The sum of the numerical values of the maximum magnetic energy product (BH)max in units of MGOe and the intrinsic coercive force Hcj in units of kOe is not less than 70. The manufacturing method of the sintered neodymium-iron-boron magnet comprises alloy smelting, powder making, powder mixing, press forming, sintering and heat treatment procedures. By controlling the component formulation and optimizing the process conditions, the sintered neodymium-iron-boron magnet is enabled to simultaneously have a high maximum magnetic energy product and a high intrinsic coercive force. | 2015-12-03 |
20150348686 | HOT-ROLLED STEEL SHEET FOR PRODUCING NON-ORIENTED ELECTRICAL STEEL SHEET AND METHOD OF PRODUCING SAME - By using a hot-rolled steel sheet of a predetermined chemical composition, and annealing the hot-rolled steel sheet in nitrogen atmosphere at 1000° C. for 30 seconds, and then immersing in a solution of 7% HCl at 80° C. for 60 seconds to obtain a hot-rolled steel sheet having a pickling weight loss of 10 g/m | 2015-12-03 |
20150348687 | ISOLATED POWER CONVERTER WITH MAGNETICS ON CHIP - An integrated circuit fabricated with a number of layer may include a substrate, a transformer having a first winding, a second winding and a magnetic core. The first winding and the second winding may surround the magnetic core. The transformer may be disposed above a first side of the substrate. A flux conductor may be disposed on a second surface of the substrate opposite to the first surface. | 2015-12-03 |
20150348688 | COIL UNIT, DRIVE MECHANISM, WINDING DEVICE AND WINDING METHOD - A coil unit may include an even number of coils comprising a first coil and a second coil; and a coil holding member which holds the even number of the coils. An outer peripheral face of the coil holding member may include a side-face pair comprising a first side face and a second side face which are substantially parallel to each other. The first side face may be formed with a first protruded part around which the first coil is wound, the first protruded part being protruded to an outer peripheral side with respect to the coil holding member. The second side face may be formed with a second protruded part around which the second coil is wound, the second protruded part being protruded to an outer peripheral side with respect to the coil holding member. The first coil and the second coil may be structured from one conducting wire. | 2015-12-03 |
20150348689 | Superconducting Magnet System for Head Imaging - A superconducting magnet system for head imaging is disclosed which includes a cryocooler, a high-pressure helium container, a self-excitation heat pipe and a superconducting magnet. A second stage coldhead of the cryocooler is connected to the high-pressure helium container for converting the helium gas in the high-pressure helium container into liquid helium. The self-excitation heat pipe forms a closed cooling loop, and liquid helium in the high-pressure helium container flows circularly in the self-excitation heat pipe. The self-excitation heat pipe cools the superconducting magnet, wherein part of the liquid helium in the self-excitation heat pipe is converted into the helium gas due to the heat disturbance generated by the superconducting magnet, and the helium gas interacts with the liquid helium to generate liquid helium vibration. | 2015-12-03 |
20150348690 | SYSTEM FOR CONCENTRATING AND CONTROLLING MAGNETIC FLUX OF A MULTI-POLE MAGNETIC STRUCTURE - An improved system for concentrating magnetic flux of a multi-pole magnetic structure at the surface of a ferromagnetic target uses first pole pieces having a magnet-to-pole piece interface with a first area and a pole piece-to-target interface with a second area substantially smaller than the first area for concentrating flux of the multi-pole magnetic structure at each pole piece-to-target interface, where the target can be a ferromagnetic material, complementary pole pieces, or a gap. The improved system may also include a magnetic circuit having second pole pieces located between the first pole pieces and the target that controls the flux directed from the first pole pieces to the target. | 2015-12-03 |
20150348691 | SOLENOID ROBUST AGAINST MISALIGNMENT OF POLE PIECE AND FLUX SLEEVE - An electromagnetic solenoid is disclosed. The solenoid includes a coil, a bobbin, a flux sleeve, an armature, and a pole piece, arranged in such a way that the solenoid is robust against misalignment of the pole piece with the flux sleeve. The configuration facilitates the integration of either the pole piece or the flux sleeve into a hydraulic circuit. | 2015-12-03 |
20150348692 | ELECTROMAGNETIC INDUCTION COIL - A primary electromagnetic induction coil, which supplies power to a primary resonance coil in a pair of a primary and a secondary resonance coils that conduct non-contact power supply by magnetic field resonance, includes a coil main body and a wedge that mounts an end portion of the coil main body to separate the end portion from other portions. Impedance matching can be achieved by adjusting a position of the wedge and a number of turns of the coil main body. | 2015-12-03 |
20150348693 | Amorphous Core Transformer - An amorphous core transformer is provided which is capable of effectively suppressing influences, fluctuation, displacement or the like of a coil caused by an electromagnetic mechanical force or the like. In an amorphous core transformer | 2015-12-03 |
20150348694 | COOLING STRUCTURE FOR MAGNETIC COMPONENT AND POWER CONVERTER PROVIDED THEREWITH - A cooling structure for cooling a magnetic component, includes a housing adapted to house the magnetic component; a cold air flow path space arranged in the housing for a cold air to flow therethrough; an internal fan disposed inside the housing for flowing the cold air; and an attachment member adapted to fix the magnetic component mounted on a bottom portion of the housing at a position facing a suction side of the internal fan in the cold air flow path space, so that the cold air generated on the suction side of the internal fan passes inside the magnetic component. The bottom portion of the housing mounted with the magnetic component is a cooling body. | 2015-12-03 |
20150348695 | Method for Producing a Coil Integrated in a Substrate or Applied to a Substrate, and Electronic Device - The subject matter of the invention relates to a method of producing a coil integrated in a substrate, using the following steps: creating the cavity in a substrate, said cavity having an open end which interrupts a surface of the substrate, introducing a paste containing ferromagnetic particles into the cavity so as to produce a coil core, closing the cavity by applying a cover layer so as to bridge the interruption in the surface of the substrate, introducing first winding portions of the coil which are vertical with respect to the surface, with a plurality or all of the first winding portions passing through the coil core contained inside the cavity, and applying second winding portions of the coil onto the surfaces of the substrate, with the second winding portions contacting the first winding portions so as to create the windings of the coil. | 2015-12-03 |
20150348696 | INDUCTION CHARGING COIL DEVICE - An induction charging coil device is provided, in particular an induction charging coil device for a hand-held power tool, including at least one coil unit having at least one shielding unit, at least one core unit and at least one electronics unit and/or one cell unit to be shielded. It is provided that a projection area of the core unit, in the case of a projection in the direction of a winding axis of the coil unit, covers at least essentially the electronics unit and/or the cell unit to be shielded. | 2015-12-03 |
20150348697 | COIL CONSTRUCTIONS FOR IMPROVED INDUCTIVE ENERGY TRANSFER - An inductor coil for an inductive energy transfer system includes multiple layers of a single wire having windings that are interlaced within at least two of the multiple layers such that both an input end and an output end of the wire enter and exit the coil on a same side of the coil. The input end and the output end of the wire may abut one another at the location where the input and output wires enter and exit the inductor coil. The wire can include one or more bundles of strands and the strands in each bundle are twisted around an axis extending along a length of the wire, and when there are at least two bundles, the bundles may be twisted around the axis. At least one edge of the inductor coil can be formed into a variety of shapes, such as in a curved shape. | 2015-12-03 |
20150348698 | AN INDUCTOR AND INDUCTOR CORE - The inductor core has a higher magnetic permeability than air, and includes an endless channel adapted for containing an inductor winding, where the inductor core extends along a first axis A, and the inductor winding extends completely around the first axis A of the inductor core in such a way that the inductor winding has a number of discrete positions or first sections where it extends in a direction being perpendicular to the first axis A of the inductor core, and wherein the inductor winding, between the discrete positions or first sections, has second sections where it extends at least partly along the first axis A. | 2015-12-03 |
20150348699 | SWITCHING POWER SUPPLY, EMI FILTER, COMMON MODE INDUCTOR AND WRAPPING METHOD FOR THE COMMON MODE INDUCTOR - The present disclosure provides a switching power supply, an EMI filter, a common mode inductor and a wrapping method for the common mode inductor. The common mode inductor includes: a magnetic core; two multilayered coil windings symmetrically wrapped around the magnetic core; and two isolation gaps each of which is formed in respective one of the two multilayered coil windings, and is configured to divide, by beginning from a first layer, the respective one of the multilayered coil windings into two wrapping areas. | 2015-12-03 |
20150348700 | ON-CHIP INDUCTOR AND METHOD FOR MANUFACTURING THE SAME - There are provided an on-chip inductor, and a method for manufacturing the same. The on-chip inductor may include: a substrate; an oxide layer formed on the substrate; a spiral-shaped wiring layer formed on the oxide layer; and a shielding layer having a lattice shape interposed between the substrate and the wiring layer. | 2015-12-03 |
20150348701 | CONDUCTIVITY AND IMPEDANCE SENSOR - A conductivity sensor, preferably a structure with a pair of magnetic cores with a primary coil wire around a shared member of both cores, and a secondary coil wire around a non-shared section of each core. When part of one core is immersed in a fluid and current is applied to the primary coil, measurements taken at the secondary coils reveal the conductivity of the fluid. The same structure can be used to measure the level of the fluid, and to determine impedance. | 2015-12-03 |
20150348702 | PARAMETER-VARIABLE DEVICE, VARIABLE INDUCTOR AND DEVICE HAVING THE VARIABLE INDUCTOR - A device having a variable inductor includes an inductor having an inductance, a first conductor having a first grounding property, and a second conductor having a second grounding property. The device further includes a first single-mesh structure including a first grid. The first grid includes a first conducting wire electrically connected to the first conductor, and a second conducting wire electrically connected to the first conducting wire and the first conductor, wherein the first conducting wire, the second conducting wire and the first conductor are configured to form a first loop corresponding to the inductor for tuning the inductance. The first single-mesh structure further includes a second grid. The second grid includes a third conducting wire electrically connected to the first conducting wire and the second conductor, and a fourth conducting wire electrically connected to the third conducting wire and the second conductor, wherein the third conducting wire, the fourth conducting wire and the second conductor are configured to form a second loop corresponding to the inductor for tuning the inductance. | 2015-12-03 |
20150348703 | SYSTEM FOR SUPPLYING BUS SUBSCRIBER MODULES WITH CONTACTLESS ENERGY AND DATA - A supply system for supplying in a contact-free manner electrical energy and data signals to a subscriber module, including a support member, a supply bar mounted on the support member, which supply bar supports primary energy and data interfaces, and at least one bus subscriber module mounted on the support member, which bus subscriber module includes secondary energy and data interfaces arranged adjacent and spaced from the primary energy and data interfaces, respectively, whereby electrical energy and data signals supplied to the primary interfaces are transmitted in a contact-free manner to the secondary interfaces, respectively. Preferably the support member is a mounting rail having an inverted top-hat configuration, with the supply bar being mounted longitudinally in the space defined by the horizontal bottom and vertical side walls of the mounting rail. | 2015-12-03 |
20150348704 | 0.2Ss class special-type high-voltage measuring current transformer - 0.2Ss class special-type high-voltage measuring current transformer belongs to a field of current transformer. An iron core includes two kinds of “L”-shaped sheets with the same size, wherein a ratio of a long side to a short side of each “L”-shaped sheet is 3:2; a first kind of the “L”-shaped sheets are permalloy sheets (1) and a second kind of the “L”-shaped sheets are cold rolled silicon steel sheets (2); and required windings are wound on each side of the iron core. Sheets of the iron core of the current transformer include the permalloy sheets and the cold rolled silicon steel sheets, which improves performance of the iron core. Utilizing structural characteristics of the iron core of different materials, a fractional turn compensation of coils is formed, which realizes a precise measurement. | 2015-12-03 |
20150348705 | MOLD FOR MANUFACTURING SINTERED MAGNET AND METHOD OF MANUFACTURING SINTERED MAGNET - The present invention relates to a mold for manufacturing a sintered magnet, the mold containing: a main body having an opening; and a lid that covers the opening and has an inner surface which is located on a main body side in a state of covering the opening, in which the inner surface has a plane surface which intersects with an inner wall surface of the main body at an obtuse angle, or has a curved surface where a tangent plane of each point on an intersection line with the inner wall surface intersects with the inner wall surface at an obtuse angle. | 2015-12-03 |
20150348706 | COIL ELEMENT PRODUCTION METHOD - Provided is a method for manufacturing a coil element, capable of manufacturing a coil element using a resin mold and without performing releasing and transferring, and capable of thinning the coil element. A method for manufacturing a coil element using a resin mold that is soluble in organic solvent, includes, preparing a resin mold, on a surface of which an inverted coil element pattern is engraved, forming a metal seed film on the surface of the resin mold, removing the metal seed film in an area where the inverted coil element pattern is not formed, forming a center conductive film so as to fill an area where the inverted coil element pattern is engraved by first electroplating while using the metal seed film as a base, and dissolving the resin mold to take out the center conductive film. | 2015-12-03 |
20150348707 | MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic device comprises a lead frame, a first core body and a coil. The lead frame has a first portion and a second portion spaced apart from the first portion. A first core body is disposed on the lead frame, wherein the first core body comprises a first through opening and a second through opening. A coil is disposed on the first core body, wherein the coil has a first terminal and a second terminal, wherein the first portion is electrically connected with the first terminal via the first through opening, and the second portion is electrically connected with the second terminal via the second through opening, respectively. | 2015-12-03 |
20150348708 | HEATED CAPACITOR AND METHOD OF FORMING THE HEATED CAPACITOR - A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer. | 2015-12-03 |
20150348709 | DIELECTRIC CERAMIC COMPOSITION AND DIELECTRIC DEVICE - To provide a dielectric ceramic composition having a high dielectric constant, i.e., 3,000 or more, at elevated temperatures at or above 150° C. and having a practically sufficient relative dielectric constant at an applied DC electric field of 2 V/μm, and to provide a dielectric device including such a dielectric ceramic composition, a dielectric ceramic composition is a composite oxide represented by formula (1): | 2015-12-03 |
20150348710 | CASE-MOLD-TYPE CAPACITOR AND METHOD FOR PRODUCING SAME - A case-mold-type capacitor includes a capacitor element, first and second bus bars connected to the first and second electrodes of the capacitor element, a case accommodating the capacitor element and the first and second bus bars, and a mold resin filling the case therein. The case has a cutaway portion provided therein. A sealing plate joined to the case so as to seal the cutaway portion. The first and second bus bars pass through the sealing plate and are fixed to the sealing plate. The case-mold-type capacitor improves dimensional accuracy between terminal portions of the first and second bus bars without increasing material cost, and has high reliability. | 2015-12-03 |
20150348711 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON - A multilayer ceramic capacitor may include: a ceramic body; a first internal electrode is spaced apart from first and second end surfaces by a predetermined distance and includes first and second lead portions which are spaced apart from each other and exposed to a first main surface; and a second internal electrode is spaced apart from the first and second end surfaces by a predetermined distance and includes a third lead portion positioned between the first and second lead portions and exposed to the first main surface. The ceramic body may further include first and second dummy electrodes, a first dummy electrode being disposed on a dielectric layer on which the first internal electrode is disposed, and a second dummy electrode being disposed on a dielectric layer on which the second internal electrode is disposed. | 2015-12-03 |
20150348712 | MULTILAYER CERAMIC CAPACITOR, METHOD OF MANUFACTURING THE SAME, AND BOARD HAVING THE SAME - A multilayer ceramic capacitor may include: an active part including dielectric layers and internal electrodes which are alternately stacked therein; and a cover part disposed on at least one of an upper surface and a lower surface of the active part. The cover part may include an active part protective cover and an exterior cover, and the active part protective cover may be disposed adjacent to the active part. | 2015-12-03 |
20150348713 | CERAMIC ELECTRONIC COMPONENT AND METHOD FOR PRODUCING SAME - A ceramic electronic component which is easily downsized, has reduced difficulty in handling, and is hardly chipped in a chip; and a method for producing the ceramic electronic component. The method includes the steps of: forming an uncured ceramic pattern which forms a ceramic layer after firing and has a circular plane shape by applying a ceramic slurry, which contains a ceramic material, to a predetermined location one time or a plurality of times repeatedly using a non-contact-type printing device such as an ink-jet printer; and forming uncured internal electrode patterns which form internal electrodes after firing and each have a circular plane shape by applying an electrode paste, which contains an internal electrode material, to a predetermined location one time or a plurality of times repeatedly using an ink-jet printer. | 2015-12-03 |
20150348714 | INTEGRATED CAPACITIVELY-COUPLED BIAS CIRCUIT FOR RF MEMS SWITCHES - A switchable capacitor including a first electrode, a dielectric layer on the first electrode, a second electrode configured to be suspended in an undeflected position over the dielectric layer in a de-activated state, and to deflect toward the first electrode in an activated state in response to a voltage difference between the two electrodes, a gap between the second electrode and the dielectric layer in the activated state being less than a corresponding gap in the de-activated state, and a capacitor having a first and second end, coupled to one of the electrodes at the first end, and configured to reduce the voltage difference between the electrodes as the second electrode deflects toward the first electrode in the activated state, wherein the voltage difference between the electrodes corresponds to a bias voltage applied across the second end of the capacitor and an other one of the first and second electrodes. | 2015-12-03 |
20150348715 | Capacitor with Charge Time Reducing Additives and Work Function Modifiers - A capacitor, and method for making the capacitor, is provided with improved charging characteristics. The capacitor has an anode, a cathode comprising a conductive polymer layer and a work function modifier layer adjacent the conductive polymer layer and a dielectric layer between the anode and the cathode. | 2015-12-03 |