49th week of 2009 patent applcation highlights part 51 |
Patent application number | Title | Published |
20090298174 | Oligomeric Compounds And Compositions For Use In Modulation Of Small Non-Coding RNAs - Compounds, compositions and methods are provided for modulating the expression and function of small non-coding RNAs. The compositions comprise oligomeric compounds, targeted to small non-coding RNAs. Methods of using these compounds for modulation of small non-coding RNAs as well as downstream targets of these RNAs and for diagnosis and treatment of disease associated with small non-coding RNAs are also provided. | 2009-12-03 |
20090298175 | Steroidal Ligands and Their Use in Gene Switch Modulation - The present invention relates to steroidal ligands for use in nuclear receptor-based inducible gene expression systems. The invention further relates to methods of modulating the expression of genes of interest with a system containing one or more nuclear receptor complexes and one or more steroidal ligands. Further aspects include ligand compositions including therapeutic compositions. | 2009-12-03 |
20090298176 | siRNA targeting KRAS - Efficient sequence specific gene silencing is possible through the use of siRNA technology. By selecting particular siRNAs directed to silencing KRAS, one can maximize the generation of an effective gene silencing reagent, as well as methods for silencing genes. | 2009-12-03 |
20090298177 | DAT1 - A synthetic diaminoketothiazole, its process of preparation and its use as a microtubule inhibitor, a probe for tubulin-microtubule system and a cytotoxic agent. Diaminoketothiazole of the formula (I) wherein Ar is 4-OMe-C | 2009-12-03 |
20090298178 | GROWTH FACTORS FOR PRODUCTION OF DEFINITIVE ENDODERM - Disclosed herein are methods for generating endoderm lineage type cells derived from human pluripotent cells, such as human embryonic stem cells, by using various agents including, but not limited to, GDF8, GDF11 and GSK-3beta inhibitors. Also disclosed herein are endoderm lineage cell populations or compositions, such as populations or compositions comprising definitive endoderm and/or other definitive endoderm-derived cell types. | 2009-12-03 |
20090298179 | Methods For Treating Degenerative Diseases/Injuries - Invented is a method of treating degenerative diseases/injuries, in a mammal, including a human, in need thereof which comprises the administration of a therapeutically effective amount of a non-peptide TPO receptor agonist to such mammal. | 2009-12-03 |
20090298180 | CELL CULTURE APPARATUS AND METHOD - A cell culture apparatus includes a housing, a bag and an inflatable bladder. The bag is disposed in the housing and has an interior surface defining a chamber for culturing cells. The bladder is disposed in the housing, external to the bag, and is sufficiently inflatable and expandable to exert pressure on the bag when the chamber is substantially free of fluid. The bladder may be inflated and expanded to reduce movement of the bag within the housing. Alternatively, or in addition, the bladder may be inflated and expanded to apply a mechanical stress on cells cultured within the chamber of the bag. | 2009-12-03 |
20090298181 | METHOD OF CULTIVATING CELL OR TISSUE - A method for cultivating a culture of a cell, tissue, etc. There is provided a method of cultivating a culture including a cell or tissue (cell construct), imparting bending motion to the culture. By virtue of applying bending force to a culture of a cell, tissue, etc. (cell construct) to thereby curve the culture, continuous compression and extension in a direction of thickness from a concave portion toward a convex portion thereof are induced. The physical stimulation and deformation not attained by conventional pressurization, shear and tension, then can be loaded on the culture to thereby realize the culture appropriate for restoration of tissue at a region accompanied by bending. | 2009-12-03 |
20090298182 | HANDHELD ANALYZER FOR TESTING A SAMPLE - The invention relates to a handheld analyzer for testing a sample, in particular of a biological fluid, for a medically significant component. It comprises a test unit, which detects the correct positioning of an analytical consumable means in a conveyance pathway. According to this invention, the test unit has both an electric switch component which mechanically senses the positioning of the analytical consumable means and an optical sensor unit which optically senses the positioning of the analytical consumable means on the conveyance pathway. The handheld analyzer is controlled as a function of a comparison of the signals of the electric switch component and the optical sensor unit. It is possible in this way to reduce malfunctions or operating errors associated therewith. | 2009-12-03 |
20090298183 | METHOD AND APPARATUS FOR ANALYZING ARSENIC CONCENTRATIONS USING GAS PHASE OZONE CHEMILUMINESCENCE - A method of detecting arsenic comprising acidifying at least one sample comprising a known arsenic concentration, reducing arsenic in the sample having the known arsenic concentration to arsine, contacting the arsine in the sample having the known arsenic concentration with a reagent to produce a chemiluminescent emission, measuring the intensity of chemiluminescent emission produced by the sample having the known arsenic concentration, acidifying at least one sample comprising an unknown arsenic concentration, reducing arsenic in the sample having the unknown arsenic concentration to arsine, contacting the arsine in the sample having the unknown arsenic concentration with a photoagent to produce a chemiluminescent emission, measuring the intensity of chemiluminescence emission produced by the sample having the unknown arsenic concentration, and determining the arsenic content in the sample having an unknown arsenic concentration by comparing the intensity of chemiluminescent emission of the sample comprising a known arsenic concentration to the chemiluminescent emission of the sample comprising an unknown arsenic concentration, wherein the arsine is not subjected to a low-temperature trap prior to the reaction with a photoagent. | 2009-12-03 |
20090298184 | Polypeptide Markers for the Diagnosis of Prostate Cancer - A method for the diagnosis of prostate cancer, comprising the step of determining the presence or absence of at least three polypeptide markers in a sample, wherein the polypeptide marker is selected from markers 1 to 44 and 52 to 78 (frequency markers), or determining the amplitude of at least one polypeptide marker selected from markers 45 to 51 and 79 to 115 (amplitude markers), wherein said sample is a urine sample or seminal fluid sample. | 2009-12-03 |
20090298185 | Protein Detection Reagents and Methods with Dyes and Dextrins - The invention provides reagents, methods and kits for detection of proteins and quantitative determination of protein concentration. The reagents comprise a protein-complexing dye, such as a Coomassie dye and one or more dextrins, for the elimination of interference caused by detergents. | 2009-12-03 |
20090298186 | Method to Assess Stability of Proteins - A method for determining conformational stability of proteins detects the change in free sulfhydryls accessible to reaction with a fluorescent probe after combined chemical and thermal denaturation. The method is useful in any application where the stability and integrity of a protein preparation is useful information. The method can be used to screen protein variants for desirable stability profile. | 2009-12-03 |
20090298187 | COMPOSITIONS, METHODS, AND KITS USING SYNTHETIC PROBES FOR DETERMINING THE PRESENCE OF A TARGET NUCLEIC ACID - Compositions, methods, and kits are provided for determining the presence of a target nucleic acid in a sample using synthetic probes. | 2009-12-03 |
20090298188 | MEASUREMENT OF A DICARBOXYLATE IN URINE SAMPLES AS A NOVEL BIOMARKER OF KIDNEY DAMAGE - The present invention relates in general to the discovery of urinary succinate as a novel biomarker of kidney disease. More specifically, the invention provides for the measurement of succinate in urine samples that has great potential for the easy and early diagnosis of kidney damage and would allow early prediction of kidney disease and therapeutic intervention. | 2009-12-03 |
20090298189 | Hydrophobic Ionic Liquids - The subject of the invention at hand are novel, a little basic, fluorinated pentafluorophenyl imide anions, which can be used as anions in ionic liquids. Methods for producing ionic liquids are described, which contain these novel pentafluorophenyl imide ions as anions, as well as quaternary organic ammonium ions, guanidinium ions, N-organo-pyridinium ions, imidazolium, imidazolidinium or benzimidazolidinium ions, alkyl-alkylidene phosphoranes or aryl-alkylidene phosphoranes as cations. Alternative methods according to the present invention provide ionic liquids through reaction of ketene N,N-diacetals or alkyl or aryl-alkylidene phosphoranes with acids. | 2009-12-03 |
20090298190 | METHOD AND TEST DEVICE FOR DETECTING ORGANIC CORROSION INHIBITORS IN COOLANTS - A test substrate for determining concentration of an organic corrosion inhibitor in a coolant fluid is provided. The test substrate comprises a porous substrate having at least a surface treated with a sufficient amount of at least a metal salt for reacting with a molar equivalent amount of the organic corrosion inhibitor in a representative sample of the coolant fluid, and at least a color indicator. The color indicator reacts with the metal salt and/or the organic corrosion inhibitor, forming an irreversibly colored complex and causing a color change in the test substrate. | 2009-12-03 |
20090298191 | Lateral Flow and Flow-through Bioassay Devices Based On Patterned Porous Media, Methods of Making Same, and Methods of Using Same - Embodiments of the invention provide lateral flow and flow-through bioassay devices based on patterned porous media, methods of making same, and methods of using same. Under one aspect, an assay device includes a porous, hydrophilic medium; a fluid impervious barrier comprising polymerized photoresist, the barrier substantially permeating the thickness of the porous, hydrophilic medium and defining a boundary of an assay region within the porous, hydrophilic medium; and an assay reagent in the assay region. | 2009-12-03 |
20090298192 | DETERMINING EFFLUENT CONCENTRATION PROFILES AND SERVICE LIVES OF AIR PURIFYING RESPIRATOR CARTRIDGES - A method for determining at least one of an effluent concentration profile, a breakthrough time and a filter cartridge recommendation includes receiving at least one input parameter, determining at least one of the effluent concentration profile, the breakthrough time and the filter cartridge recommendation based on the input parameter, and graphically displaying at least one of the effluent concentration profile, the breakthrough time, and the filter cartridge recommendation. The effluent concentration profile includes a plot of a concentration of a chemical species over a period of time. The breakthrough time includes a time at which a predetermined concentration of the chemical species passes through a filter cartridge. | 2009-12-03 |
20090298193 | ATOMIC EMISSION SPECTROSCOPY ON A CHIP - A method of inducing explosive atomization of materials is provided using a metal-oxide-semiconductor (MOS)-based structure under electrical excitation. Explosive atomization of the gate electrode and surrounding dielectric materials creates a microplasma that is substantially confined with the device at the metal/dielectric interface. The device can generate a microplasma in either the accumulation or inversion regime. The high degree of confinement of the microplasma allows chip-scale implementation of atomic emission spectroscopy and detection using a minimal amount of analyte. | 2009-12-03 |
20090298195 | SYNTHETIC IMMUNOGLOBULIN DOMAINS WITH BINDING PROPERTIES ENGINEERED IN REGIONS OF THE MOLECULE DIFFERENT FROM THE COMPLEMENTARITY DETERMINING REGIONS - Method for engineering an immunoglobulin comprising at least one modification in a structural loop region of said immunoglobulin and determining the binding of said immunoglobulin to an epitope of an antigen, wherein the unmodified immunoglobulin does not significantly bind to said epitope, comprising the steps of:—providing a nucleic acid encoding an immunoglobulin comprising at least one structural loop region,—modifying at least one nucleotide residue of at least one of said structural loop regions,—transferring said modified nucleic acid in an expression system,—expressing said modified immunoglobulin,—contacting the expressed modified immunoglobulin with an epitope, and—determining whether said modified immunoglobulin binds to said epitope, as well as modified immunoglobulins. | 2009-12-03 |
20090298196 | QUANTITATIVE MEASUREMENT METHOD FOR RECOMBINANT PROTEIN - The present invention is intended to provide a method of rapidly, simply and accurately measuring a recombinant protein. As means for resolution, the protein quantity is measured by causing the expression of a fusion protein with the target protein and epitope tags containing two types of epitopes, bringing them into contact with detection antibodies which specifically recognize each epitope, and detecting a phenomenon caused by both detection antibodies coming close to each other. | 2009-12-03 |
20090298197 | SERS-BASED METHODS FOR DETECTION OF BIOAGENTS - An assay and method of assay for optical detection of bioagents, a target nucleic acid or a target protein using a surface enhanced Raman scattering (SERS) active biomolecule molecular beacon. The present invention also provides the assay and method in a multiplexed format. | 2009-12-03 |
20090298198 | DIAGNOSING AND MONITORING INFLAMMATORY DISEASES BY MEASURING COMPLEMENT COMPONENTS ON WHITE BLOOD CELLS - The invention is related to methods of diagnosing inflammatory diseases or conditions by determining levels of components of the complement pathway on the surface of white blood cells. | 2009-12-03 |
20090298199 | IMMUNOSORBENT ASSAY SUPPORT AND METHOD OF USE - Embodiments of the present invention provide an immunosorbent assay support immobilized with an intermediate binding antibody and their method of use in an improved immunoassay format. | 2009-12-03 |
20090298200 | Spin Transfer MRAM Device with Separated CPP Assisted Writing - A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R | 2009-12-03 |
20090298201 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device, a first insulating film covering a ferroelectric capacitor is formed, and a first opening that has a relatively large diameter and reaches an electrode of the ferroelectric capacitor is formed in the first insulating film, and then recovery annealing of the ferroelectric capacitor is performed, and thereby, a path for oxygen can be secured in performing the recovery annealing, and the sufficient recovery annealing can be performed without causing problems during a manufacturing process. | 2009-12-03 |
20090298202 | Techniques for Coupling in Semiconductor Devices - Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step. Ferromagnetic exchange coupling is provided of the magnetic layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. | 2009-12-03 |
20090298203 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An aluminum oxide film covering a ferroelectric capacitor is formed. Next, an opening ( | 2009-12-03 |
20090298204 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film | 2009-12-03 |
20090298205 | Pattern verifying method, pattern verifying device, program, and manufacturing method of semiconductor device - An overlapping margin of a second pattern for a first pattern is corrected for at least one of the first pattern and the second pattern (S | 2009-12-03 |
20090298206 | METHOD AND APPARATUS TO MINIMIZE STRESS DURING REFLOW PROCESS - Utilizing an appropriately configured laser interferometer, the warpage of a silicon chip can be easily monitored during the solder reflow attachment process in an effort to determine the amount of stress encountered by the chip. Warpage measurements can then be continuously monitored throughout the process and related data can be stored to easily suggest the level of warpage generated by various processing parameters. By dynamically monitoring warpage in conjunction with processing parameters, a correlation can be established between the various parameters chosen, and resulting warpage. Based upon this correlation, the evaluators can easily identify those parameters which produce minimum stress, thus avoiding potential for breakage and damage during reflow operations. | 2009-12-03 |
20090298207 | METHOD FOR BONDING WAFERS - The invention relates to a method for bonding wafers along their corresponding surfaces. | 2009-12-03 |
20090298208 | METHOD OF FORMING SEMICONDUCTOR THIN FILM AND INSPECTION DEVICE OF SEMICONDUCTOR THIN FILM - A method of forming a semiconductor thin film includes: a step of forming an amorphous semiconductor thin film over a transparent substrate; a step of forming a crystalline semiconductor thin film by irradiating the amorphous semiconductor thin film with laser light to provide heat treatment and thereby crystallizing the amorphous semiconductor thin film; and an inspection step of inspecting the crystalline semiconductor thin film. The inspection step includes a step of obtaining a transmission image of the crystalline semiconductor thin film by irradiating the crystalline semiconductor thin film with light from a rear side of the transparent substrate and taking an image, and a screening step of performing screening of the crystalline semiconductor thin film based on the obtained transmission image. | 2009-12-03 |
20090298209 | OPTOELECTRONIC DEVICE MANUFACTURING - A method for manufacturing an optoelectronic device including a capping layer for improving out-coupling and optical fine-tuning of emission characteristics includes steps of: producing an optoelectronic member for generating photons of a predefined wavelength; producing a light emitting surface on the optoelectronic member; and producing a capping layer on the light emitting surface. | 2009-12-03 |
20090298210 | LIGHT EMITTING DEVICE - An inexpensive light emitting device and inexpensive electric equipment are provided. A substrate on which a semiconductor element or a light emitting element is formed and a color filter are manufactured by separate manufacturing processes, and they are bonded to each other to complete the light emitting device. Thus, the yield of the light emitting device is improved and the manufacture period is shortened. | 2009-12-03 |
20090298211 | METHOD FOR MANUFACTURING FLEXIBLE DISPLAY - A method for manufacturing a flexible display is provided. A sacrificial layer is formed on a substrate support, the sacrificial layer having an absorptivity of 1 E+02 to 1 E+06 cm | 2009-12-03 |
20090298212 | Silicon Based Solid State Lighting - A semiconductor device includes a substrate comprising a first surface having a first orientation and a second surface having a second orientation and a plurality of III-V compound layers on the substrate, wherein the plurality of III-V compound layers are configured to emit light when an electric current is produced in one or more of the plurality of III-V compound layers. | 2009-12-03 |
20090298213 | LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies. | 2009-12-03 |
20090298214 | METHOD OF GROWING NITRIDE SINGLE CRYSTAL AND METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a method of growing a nitride single crystal. A method of growing a nitride single crystal according to an aspect of the invention may include: growing a first nitride single crystal layer on a substrate; forming a dielectric pattern having an open area on the first nitride single crystal layer, the open area exposing a part of an upper surface of the first nitride single crystal layer; and growing a second nitride single crystal layer on the first nitride single crystal layer through the open area while the second nitride single crystal layer grows to be equal to or larger than a height of the dielectric pattern, wherein the height of the dielectric pattern is greater than a width of the open area so that dislocations in the second nitride single crystal layer move laterally, collide with side walls of the dielectric pattern, and are terminated. | 2009-12-03 |
20090298215 | Method of Enclosing a Micro-Electromechanical Element - A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being accessible through via holes in a layer of insulating material deposited thereon, and the layer of insulating material being covered by a thin film layer of conductive material. The method further comprises the step of hydrophobically treating at least a portion of the inner surface of the cavity. Finally the method comprises the steps of submerging the wafer in an electroplating solution and electroplating a conductive layer onto the thin film layer of conductive material such that the cavity remains free of electroplating solution. | 2009-12-03 |
20090298216 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. First, a first electrode is formed over a first region of a substrate. Then, a dielectric layer covering the first electrode is formed over the substrate. After that, a plurality of openings is formed on the first region of the substrate. Thereafter, a conductive layer covering the dielectric layer and the openings is formed over the substrate. Then, the conductive layer in the bottom of the openings is removed to form second electrodes. After that, the dielectric layer between the second electrode and the first electrode is removed. | 2009-12-03 |
20090298217 | METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICES ON LIGHTWEIGHT SUBSTRATES - A method for making a semiconductor device having front-surface electrical terminals in which the device is manufactured so as to include a bottom electrode, a top electrode and a semiconductor body therebetween. A first bus bar is disposed in a groove in the semiconductor body. It is in electrical communication with the bottom electrode, and includes a tab portion which projects from the device. A second bus bar is in electrical communication with the top electrode, and is disposed atop the first electrode, and electrically insulated therefrom. The tab of the first bus bar provides one terminal of the device and is folded onto the second bus bar and is electrically insulated therefrom. The second bus bar provides the second terminal of the device. | 2009-12-03 |
20090298218 | LEAD FRAME THERMOPLASTIC SOLAR CELL RECEIVER - A lead frame thermoplastic package for a solar cell, and a method of manufacturing the same. The lead frame being either a single-lead frame design or a dual-lead frame design. The single-lead frame design being made up of a single-lead metal frame. The dual-lead frame design being made up of a die pad lead frame, a wire bond lead frame, and being encapsulated in a thermoplastic resin. Optionally, the single lead frame or at least one of the dual-lead frames is coated with a dielectric material. The lead frame providing connections for a semiconductor die, a diode, and the associated electrical connections. The lead frame also providing a large surface area metal pad for cooling, and mounting tabs for securing various optics systems to the package. Optionally, the lead frame is incorporated into a solar cell including the lead frame, a semiconductor die, a diode, an optics system, and an integrated electrical connection system. | 2009-12-03 |
20090298219 | Method for Manufacturing Solid-State Image Pickup Device Module - A method for manufacturing a solid-state pickup device module of the present invention includes: a step of processing a transparent substrate so that each of transparent substrates for a chip is held opposite to each of solid-state image pickup devices when the transparent substrate and a substrate having a plurality of solid-state image pickup devices are opposed to each other (step of processing a transparent substrate; S | 2009-12-03 |
20090298220 | IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A method of fabricating a CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical function. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 2009-12-03 |
20090298221 | IMAGE SENSOR CLOCKING METHOD - A method for reducing dark current within a charge-coupled device, the method includes each gate phase n having a capacitance C | 2009-12-03 |
20090298222 | Method for manufacturing Chalcogenide devices - A method of chalcogenide device formation includes treatment of the surface upon which the chalcogenide material is deposited. The treatment reduces or eliminates native oxides and other contaminants from the surface, thereby increasing the adhesion of the chalcogenide layer to the treated surface, eliminating voids between the chalcogenide layer and deposition surface and reducing the degradation of chalcogenide material due to the migration of contaminants into the chalcogenide. | 2009-12-03 |
20090298223 | SELF-ALIGNED IN-CONTACT PHASE CHANGE MEMORY DEVICE - A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode. | 2009-12-03 |
20090298224 | Memory and Access Device and Method Therefor - Briefly, in accordance with an embodiment of the invention, a memory and a method to manufacture the memory is provided. The memory may include a phase change material over a substrate. The memory may further include a switching material coupled to the phase change material, wherein the switching material comprises a chalcogen other than oxygen and wherein the switching material and the phase change material form portions of a vertical structure over the substrate. | 2009-12-03 |
20090298225 | Doped Metal Oxide Films and Systems for Fabricating the Same - A method of fabricating a doped metal oxide film comprising the steps of: (a) providing a semiconductor substrate in a vacuum chamber; (b) generating plasma comprising at least metal (M) , oxygen (O) and dopant ions within said chamber in the presence of an inert carrier gas; (c) forming a doped metal oxide (MO) film on said substrate from said plasma; and (d) controlling, during step (c) , the amount of O ions relative to said dopant ions within said plasma to form at least one of an n-type MO film and a p-type MO film on said substrate. A system for fabricating the doped metal oxide is also disclosed. | 2009-12-03 |
20090298226 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - During a process of forming an active layer of a semiconductor device using a ZnO film, the ZnO film is laser-annealed with an ultraviolet pulsed laser to reduce the resistance of the film, and then oxidation treatment is applied to increase the specific resistance value at a channel portion of the ZnO film, which once has excessively low resistance after the laser annealing, to 10 | 2009-12-03 |
20090298227 | METHOD OF FABRICATING A STACKED TYPE CHIP PACKAGE STRUCTURE AND A STACKED TYPE PACKAGE STRUCTURE - A method of fabricating a stacked type chip package structure is provided. The method includes following steps. First, a substrate, a first chip, and a second chip are provided. A number of bumps are disposed on a surface of the second chip. The second chip is then fixed on a surface of the first chip. Next, the second chip and the first chip on the substrate are turned upside down, and then the second chip is electrically connected to the substrate through the bumps by using a flip chip bonding technique. After that, the first chip is electrically connected to the substrate. Finally, a molding compound is formed on the substrate for encapsulating the first chip, the second chip, and the bumps. | 2009-12-03 |
20090298228 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A resin layer made of thermoplastic resin is formed on a supporting substrate, and then, an insulating layer is formed on the first resin layer. Then, an interlayer connector is formed through the insulating layer and then, a wiring layer is formed on the first resin layer so as to be electrically connected with the interlayer connector. Thereafter, a first semiconductor chip is mounted on the wiring layer. Then, the first resin layer is heated so that the supporting substrate and the insulating layer are relatively shifted one another to shear the first resin layer, thereby separating the supporting substrate and the insulating layer and forming a semiconductor device. | 2009-12-03 |
20090298229 | FLIP CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit board in a face-down type and having a plurality of bonding pads; conductive polymers for electrically and mechanically connecting the bonding pads of the semiconductor chip and the electrode terminals of the printed circuit board with each other; and an encapsulant for molding one surface of the printed circuit board including the conductive polymers and the semiconductor chip. | 2009-12-03 |
20090298230 | Stacked Module Systems and Methods - The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry. | 2009-12-03 |
20090298231 | Cmos process for fabrication of ultra small or non standard size or shape semiconductor die - A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes. | 2009-12-03 |
20090298232 | METHOD OF FORMING A LEADED MOLDED ARRAY PACKAGE - In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages. | 2009-12-03 |
20090298233 | Method for Fabricating Semiconductor Elements - The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements. | 2009-12-03 |
20090298234 | METHOD OF FABRICATING SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR WAFER, AND METHOD OF SAWING THE SEMICONDUCTOR WAFER - A method of fabricating a semiconductor chip package, in which a protection layer is formed on a scribe lane of a wafer including a plurality of semiconductor chips, an encapsulation layer is formed on the semiconductor chips and the protection layer, and at least two types of lasers having different respective wavelengths are sequentially irradiated to the scribe lane so as to separate the semiconductor chips. Therefore, the wafer can be protected from the laser that is used to saw the encapsulation layer. | 2009-12-03 |
20090298235 | CLIPLESS INTEGRATED HEAT SPREADER PROCESS AND MATERIALS - In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips. | 2009-12-03 |
20090298236 | Integrated Module for Data Processing System - An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias. | 2009-12-03 |
20090298237 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor chip sealed with an encapsulation resin prevented from overflowing from an inside of the outer edge by a wiring pattern extended portion extending from the wiring pattern along an outer edge of a solder resist pattern at an outside of the outer edge of the solder resist pattern. | 2009-12-03 |
20090298238 | METHODS FOR FABRICATING MEMORY CELLS AND MEMORY DEVICES INCORPORATING THE SAME - A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure. A first source region is formed adjacent the first gate structure, a common drain/cathode region is formed between the first and second gate structures, a second source region is formed adjacent the third gate structure, a common drain/source region is formed between the third and fourth gate structures, and a drain region is formed adjacent the fourth gate structure. A first base region is formed that extends into the first well region under the insulating spacer block adjacent the first gate structure, and an anode region is formed in the first well region that extends into the first well region adjacent the first base region. | 2009-12-03 |
20090298239 | Method for making thin film transistor - A method for making a thin film transistor, the method includes the steps of: providing a plurality of carbon nanotubes and an insulating substrate; flocculating the carbon nanotubes to acquire a carbon nanotube structure, applying the carbon nanotube structure on the insulating substrate; forming a source electrode, a drain electrode, and a gate electrode; and covering the carbon nanotube structure with an insulating layer. The source electrode and the drain electrode are connected to the carbon nanotube structure, the gate electrode is electrically insulated from the carbon nanotube structure by the insulating layer. | 2009-12-03 |
20090298240 | SELF-ALIGNED THIN-FILM TRANSISTOR AND METHOD OF FORMING SAME - A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure. | 2009-12-03 |
20090298241 | METHOD OF FABRICATING VERTICAL THIN FILM TRANSISTOR - A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained. | 2009-12-03 |
20090298242 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Disclosed herein is a method for manufacturing a semiconductor device that includes forming a gate pattern on a substrate having a stacked structure including a lower silicon layer, an insulating layer, and an upper silicon layer. The method further includes forming spacers on sidewalls of the gate pattern. Still further, the method includes etching the upper silicon layer using the gate pattern as a mask to form a floating body and expose a portion of the insulating layer. The method further includes depositing a conductive layer over the gate pattern and exposed insulating layer, and performing a thermal process on the conductive layer to form a source/drain region in the floating body. | 2009-12-03 |
20090298243 | SOI DEVICES AND METHODS FOR FABRICATING THE SAME - Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer. | 2009-12-03 |
20090298244 | Mobility Enhanced FET Devices - NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states. | 2009-12-03 |
20090298245 | Low Power Circuit Structure with Metal Gate and High-k Dielectric - FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation. | 2009-12-03 |
20090298246 | TECHNIQUES FOR FABRICATING A NON-PLANAR TRANSISTOR - Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may encounter various mechanical stresses, e.g., inertial forces during movement of the substrate and fluid forces during cleaning steps. If the forces on the fin are too large, the fin may fracture and possibly render a transistor inoperative. Supporting one side of a fin before forming the second side of a fin creates stability in the fin structure, thereby counteracting many of the mechanical stresses incurred during manufacturing. | 2009-12-03 |
20090298247 | Method and device for providing a contact structure - An approach is provided for semiconductor devices and methods for providing a contact structure. Methods may include forming a gate pattern on a substrate including a device isolation pattern provided to define an active region, the gate pattern crossing over the active region and being disposed on the device isolation pattern, and forming a first doped region and a second doped region in the active region adjacent to opposite sides of the gate pattern, respectively. The methods may include sequentially forming a gate spacer and a sacrificial spacer on both sidewalls of the gate pattern, forming an interlayer dielectric on the entire surface of the substrate, planarizing the interlayer dielectric to expose the gate spacer and the sacrificial spacer, removing a portion of the sacrificial spacer to form a groove to expose the first doped region, and forming a contact structure in the groove. | 2009-12-03 |
20090298248 | Two-Step STI Formation Process - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate. | 2009-12-03 |
20090298249 | DRIVE CURRENT INCREASE IN TRANSISTORS BY ASYMMETRIC AMORPHIZATION IMPLANTATION - By providing a substantially non-damaged semiconductor region between a pre-amorphization region and the gate electrode structure, an increase of series resistance at the drain side during the re-crystallization may be reduced, thereby contributing to overall transistor performance, in particular in the linear operating mode. Thus, symmetric and asymmetric transistor architectures may be achieved with enhanced performance without unduly adding to overall process complexity. | 2009-12-03 |
20090298250 | BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD - A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed. | 2009-12-03 |
20090298251 | NORMAL PRESSURE AEROSOL SPRAY APPARATUS AND METHOD OF FORMING A FILM USING THE SAME - An aerosol spray apparatus and a method of forming a film using the aerosol spray apparatus are disclosed. The aerosol spray apparatus in accordance with an embodiment of the present invention includes: a carrier gas injection unit, which forms carrier gas by vaporizing liquefied gas and increases the pressure of the carrier gas; an aerosol forming unit, which forms an aerosol by mixing the carrier gas with powder; and a film forming unit, which sprays the aerosol in a normal pressure environment such that the film is formed on the surface of the board. The apparatus can perform a coating process with no restriction of the type and size of powder, simplify the process because the film can be formed in a normal temperature and pressure environment, and control a wide range of film thickness in a short time. | 2009-12-03 |
20090298252 | FIELD-ENHANCED PROGRAMMABLE RESISTANCE MEMORY CELL - A method for fabricating a field-enhanced programmable resistance memory cell. In an example embodiment, a resistor includes a resistance structure between a first electrode and a second electrode. The resistance structure includes an insulating dielectric material. The second electrode includes a protrusion extending into the resistance structure. The insulating dielectric material includes a material in which a confined conductive region with a programmable resistance is formable via a conditioning signal. | 2009-12-03 |
20090298253 | RESISTOR WITH IMPROVED SWITCHABLE RESISTANCE AND NON-VOLATILE MEMORY DEVICE - A resistor with improved switchable resistance and a non-volatile memory device includes a first electrode, a second electrode facing the first electrode and a resistance structure between the first electrode and the second electrode. The resistance structure includes an insulating dielectric material in which a confined switchable conductive region is formed between the first and second electrode. The resistor further includes a perturbation element, locally exerting mechanical stress on the resistance structure in the vicinity of the perturbation element at least during a forming process in which the confined switchable conductive region is formed. | 2009-12-03 |
20090298254 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer. | 2009-12-03 |
20090298255 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode. | 2009-12-03 |
20090298256 | SEMICONDUCTOR INTERCONNECT AIR GAP FORMATION PROCESS - A semiconductor package including an interconnect air gap and method for making the same. The semiconductor package includes a dielectric layer, a metallic interconnect, an air gap disposed between the dielectric layer and interconnect, and a spacer interspersed between the metallic interconnect and air gap. The metallic interconnect is laterally supported by and isolated from the air gap by the spacer. A method for making the same is also provided. | 2009-12-03 |
20090298257 | DEVICE ISOLATION TECHNOLOGY ON SEMICONDUCTOR SUBSTRATE - A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing. | 2009-12-03 |
20090298258 | QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE - The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition. | 2009-12-03 |
20090298259 | Method for transferring one-dimensional micro/nanostructure - As the conventional nanowire technology has many restrictions, the present invention discloses a method for transferring a one-dimensional micro/nanostructure to diversify the fabrication and application of nanocomponents, wherein a micro/nanostructure having formed on one substrate can be arbitrarily transferred to another substrate, whereby a micro/nanostructure can be integrated with different substrates. | 2009-12-03 |
20090298260 | BACK-ILLUMINATED IMAGER USING ULTRA-THIN SILICON ON INSULATOR SUBSTRATES - A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator substrate (UTSOI) is disclosed. The UTSOI substrate is formed by providing a handle wafer comprising a mechanical substrate and an insulator layer substantially overlying the mechanical substrate. A donor wafer is provided. Hydrogen is implanted in the donor wafer to form a bubble layer. The donor wafer is doped with at least one dopant to form a doped layer proximal to the bubble layer. The handle wafer and the donor wafer are bonded between the insulator layer of the handle wafer and a surface of the donor wafer proximal to the doped layer to form a combined wafer having a portion substantially underlying the bubble layer. The portion of the combined wafer substantially underlying the bubble layer is removed so as to expose a seed layer. An epitaxial layer is grown substantially overlying the seed layer, wherein at least one dopant diffuse into the epitaxial layer. At the completion of the growing of the epitaxial layer, there exists a net dopant concentration in the seed layer and the epitaxial layer which has maximum value at or near an interface between the seed layer and the insulator layer. | 2009-12-03 |
20090298261 | Method For Producing Bonded Wafer - A bonded wafer is produced by comprising a step of implanting oxygen ions from a surface of a wafer for active layer to form an oxygen ion implanted layer at a given position inside the wafer for active layer; a step of bonding the wafer of active layer to a wafer for support substrate directly or through an insulating film; a step of subjecting the resulting bonded wafer to a heat treatment for increasing a bonding strength; a step of removing a portion of the wafer for active layer in the bonded wafer to a given position not exposing the oxygen ion implanted layer by a given method; a step of exposing the entire surface of the oxygen ion implanted layer; and a step of removing the exposed oxygen ion implanted layer to obtain an active layer of a given thickness, wherein the step of exposing the entire surface of the oxygen ion implanted layer is carried out by a dry etching under given conditions. | 2009-12-03 |
20090298262 | METHOD OF SPLITTING BRITTLE MATERIALS WITH TRENCHING TECHNOLOGY - One aspect of the invention relates to a method for splitting an object made of brittle material into at least two pieces. The object has a first flat surface and a second flat surface opposite to each other. The method includes etching at least one trench in at least one of the surfaces so as to form at least one line on the surface. The method also includes splitting the object into separate pieces along the line. | 2009-12-03 |
20090298263 | DIVIDING METHOD FOR WAFER HAVING FILM ON THE FRONT SIDE THEREOF - A wafer dividing method for dividing a wafer having a film on the front side thereof. The wafer dividing method includes a modified layer forming step of applying a laser beam having a transmission wavelength to the substrate of the wafer from the front side thereof along the streets so that a focal point of the laser beam is set inside the substrate, thereby forming a modified layer in the substrate along each street, a film dividing step of applying a laser beam having an absorption wavelength to the film from the front side of the wafer along each street to thereby form a laser processed groove for dividing the film along each street, a back grinding step of grinding the back side of the substrate of the wafer to thereby reduce the thickness of the wafer to a predetermined thickness, a wafer supporting step of attaching the wafer to a dicing tape supported to an annular frame, and a wafer breaking step of applying an external force to the wafer by expanding the dicing tape to thereby break the wafer along each street. | 2009-12-03 |
20090298264 | METHOD OF CUTTING ADHESIVE FILM ON A SINGULATED WAFER BACKSIDE - On the back surface of the chip of which a front surface is formed with an electronic circuit, an adhesive film of a shape and dimensions corresponding to at least the back surface of the chip is adhered to obtain the semiconductor chip with the entire back surface covered with the adhesive film. Such a semiconductor chip is obtained by forming a division groove in the front surface of a semiconductor wafer to be divided into plural chips, grinding a back surface of the wafer until the division groove appears to divide the wafer into plural chips, adhering the adhesive film and a dicing tape on the entire back surface of the wafer, and stretching the dicing tape to cut the adhesive film along the division groove. | 2009-12-03 |
20090298265 | Method of Manufacturing III Nitride Crystal, III Nitride Crystal Substrate, and Semiconductor Device - Affords III-nitride crystals having a major surface whose variance in crystallographic plane orientation with respect to an {hkil} plane chosen exclusive of the {0001} form is minimal. A method of manufacturing the III-nitride crystal is one of: conditioning a plurality of crystal plates ( | 2009-12-03 |
20090298266 | DOPANT CONFINEMENT IN THE DELTA DOPED LAYER USING A DOPANT SEGREGRATION BARRIER IN QUANTUM WELL STRUCTURES - A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×10 | 2009-12-03 |
20090298267 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - It is an apparatus for semiconductor device production in which a feed gas is fed into a chamber having a semiconductor wafer placed therein to deposit a thin film on the surface of the semiconductor wafer based on a catalyzed chemical reaction. It comprises the chamber for placing a semiconductor wafer therein, a feed gas supply means with which a feed gas which is a raw material for the thin film is sent into the chamber, and a gas-blowing means which has a gas-blowing opening through which the feed gas sent from the feed gas supply means is blown against the surface of the semiconductor wafer placed in the chamber. The gas-blowing means changes in the state of the gas-blowing opening according to the feed gas blowing position to thereby regulate the amount of the feed gas to be blown. | 2009-12-03 |
20090298268 | Method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same - A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and a Si0 | 2009-12-03 |
20090298269 | STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME - A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate. | 2009-12-03 |
20090298270 | METHOD FOR PRODUCING A SEMICONDUCTOR - A method for producing a semiconductor is disclosed. One embodiment provides a p-doped semiconductor body having a first side and a second side. An n-doped zone is formed in the semiconductor body by implantation of protons into the semiconductor body via the first side down to a specific depth of the semiconductor body and by subsequent heating at least of the proton-implanted region of the semiconductor body. A pn junction arises in the semiconductor body. The second side of the semiconductor body is removed at least as far as a space charge zone spanned at the pn junction. | 2009-12-03 |
20090298271 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device prevents failure of self-aligned contacts to improve the yield of the semiconductor device. A height of a device isolating film is larger than a height of an active region. A recess region of the device isolating film is planarized by a wet etching process to remove a hard mask layer when a recess gate is etched. A contact plug is then formed in the recess region between adjacent recess gates. | 2009-12-03 |
20090298272 | SINGLE POLY CMOS IMAGER - More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate. | 2009-12-03 |
20090298273 | METHODS OF FORMING RECESSED GATE ELECTRODES HAVING COVERED LAYER INTERFACES - Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers. | 2009-12-03 |
20090298274 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming core material patterns comprising first films separated from each other above a substrate, modifying surfaces of the core material patterns so that a second film is formed so as to be selectively etchable with the first films internally remaining, covering an upper surface and sides of the second film and forming a third film on the substrate, etching back the third film so that an upper surface of the second film is exposed and a base layer of the core material patterns is exposed between the patterns, and causing the third film to selectively remain, removing the second film more rapidly than the first and third films, and patterning the base layer with the first and third films remaining on the base layer serving as a mask after the second film has been removed, thereby forming a base layer pattern. | 2009-12-03 |