48th week of 2010 patent applcation highlights part 31 |
Patent application number | Title | Published |
20100302798 | POLARIZED DIFFRACTIVE BACKLIGHT - A backlight is provided for illuminating an at least partially transmissive display. The backlight includes a light source. A light guide receives the light from an edge surface and guides the light by total internal reflection. The light is extracted from the lightguide using sub-wavelength extraction features designed on the basis of two interleaved grating structures. The emitted light, using this arrangement has a high level of polarization. | 2010-12-02 |
20100302799 | Moving light effect using a light-guide structure - A plurality of light sources are arranged with a light-guide structure such that light emitted by the sources propagates longitudinally through the light-guide structure. The light-guide structure scatters and/or redirects the emitted light and outputs the scattered and/or redirected light laterally. A controller is configured to dynamically correlate the light emitted from the plurality of light sources and to dynamically tune intensity of the light emitted from the plurality of light sources. The result is a dynamic light effect that appears to the observer as moving light. | 2010-12-02 |
20100302800 | Back light module and light guide plate thereof - A light guide plate adapted to a backlight module is provided. The backlight module has a plurality of point light sources providing a light beam of a predetermined wavelength. The light guide plate includes a light emitting surface, a bottom opposite to the light emitting surface, a light incident surface connecting the light emitting surface and the bottom, a plurality of grating structures, and a plurality of diffusion dots. The light incident surface is near the point light sources. The diffusion dots are disposed on the bottom. At least portions of the grating structures are disposed on the light incident surface. Each of the grating structures has a plurality of concave parts and a plurality of protruding parts. Each of the concave parts is disposed between two neighboring protruding parts. A ratio of the predetermined wavelength to a pitch between two neighboring protruding parts is ranged between 1.2 to 1.3. | 2010-12-02 |
20100302801 | LIGHT GUIDE PLATE AND BACKLIGHT SOURCE HAVING SAME - An exemplary light guide plate includes an light incident surface, an light emitting surface, a number of parallel V-shaped structures, and a Fresnel lens portion. The light incident surface is configured for receiving light beams. The light emitting surface is adjacent to the light incident surface, and configured for emission of the light beams. The V-shaped grooves are defined in the light incident surface and arranged perpendicular to the light emitting surface. The Fresnel lens portion is provided on the light incident surface between each two neighboring V-shaped grooves. | 2010-12-02 |
20100302802 | ILLUMINATION DEVICES - Illumination device and methods of making the same are disclosed. In one embodiment, an illumination device includes a light source, a light guide having a first planar surface, a first end and a second end, and a length therebetween, the light guide positioned to receive light from the light source into the light guide first end, and the light guide configured such that light from the light source provided into the first end of the light guide propagates towards the second end, a plurality of light turning features that are configured to reflect light propagating towards the second end of the light guide out of the planar first surface, and one or more light redirection features configured to redirect light within the light guide at more useful angles. | 2010-12-02 |
20100302803 | ILLUMINATION DEVICES AND METHODS OF FABRICATION THEREOF - Illumination devices and methods of making same are disclosed. In one embodiment, an illumination apparatus includes a light source, a light guide having a planar first surface, a first end and a second end, and a length therebetween, the light guide positioned to receive light from the light source into the light guide first end, and the light guide configured such that light from the light source provided into the first end of the light guide propagates towards the second end, and a plurality of light turning features that are configured to reflect light propagating towards the second end of the light guide out of the planar first surface of the light guide, each light turning feature having a turning surface and an interferometric stack formed on the turning surface. | 2010-12-02 |
20100302804 | Surface light emitting apparatus - A surface emitting apparatus includes a light guide plate, a plurality of point light sources, a diffusing member, and a spacer member. The light guide plate has an end surface and a light emitting surface and is configured to allow light incident on the end surface to be emitted from the light emitting surface. The plurality of point light sources is provided to oppose the end surface of the light guide plate. The diffusing member is provided on a light emitting surface side of the light guide plate. The spacer member defines a space between the light emitting surface and the diffusing member such that a distance between the light emitting surface and the diffusing member is larger than a thickness of the light guide plate. | 2010-12-02 |
20100302805 | LED BACK-LIGHT UNIT AND DISPLAY DEVICE - A back-light unit including a plurality of substrates, a plurality of light sources respectively disposed on the plurality of substrates and configured to emit light, and N (N ≧2) light guide plates respectively disposed adjacent to the plurality of light sources, each light guide plate including a light incidence part having a light incidence surface for receiving light emitted in a first direction from a corresponding light source, and a light emission part for emitting the received incident light in a second direction different than the first direction. Further, at least one of the light guide plates includes light-extracting surface patterns disposed on the light emission part, and the light-extracting surface patterns comprise a first region of light-extracting surface patterns having a higher pattern-density than a second region of light-extracting surface patterns next to the first region. | 2010-12-02 |
20100302806 | Planar illumination device - A planar illumination device comprises a light guide plate, a point-like light source arranged on an incoming-light face of the light guide plate, an inner frame formed substantially in a U-shape on a top view, and an outer frame having a seat portion and side walls wherein the light guide plate is accommodated in the inner frame and mounted on the seat portion of the outer frame, while the point-like light source is arranged along the incoming-light face of the light guide plate and held between the incoming-light face and the side wall of the outer frame. At the inner frame, an elastic action portion which is elastically deformed so as to make a partial contact with the outer frame and energizes the light guide plate toward the point-like light source is provided. | 2010-12-02 |
20100302807 | Light Guide plate for a turning film system - The present invention provides a light guide plate comprising: (a) an input surface for receiving light from a light source into the light guide plate, (b) an output surface for emitting light, (c) a bottom surface opposing to the output surface, wherein discrete elements are located at least one of the output or bottom surface, the density function D(x) of the discrete elements has a minimal value Dmin(x | 2010-12-02 |
20100302808 | Power source apparatus - A power source apparatus includes: a first alternating current line; a second alternating current line; an electric power inputting portion including a rectifying circuit for rectifying an alternating current voltage supplied from an alternating current power source, the electric power inputting portion serving to output the rectified voltage to each of the first and second alternating current lines; a first converter including a switching element for converting the alternating current voltage into a first direct current voltage; a second converter for converting the first direct current voltage obtained in the first converter into a second direct current voltage; and a control circuit for carrying out control for driving at least the switching element of the first converter so as to be turned ON or OFF. | 2010-12-02 |
20100302809 | Piezoelectric transformer driving device and image forming device - A piezoelectric transformer driving device includes a piezoelectric transformer for outputting an alternating high voltage, a switching control part configured to control the control frequency of the control signal, a reference voltage waveform generation part configured to switch between a first voltage value, a second voltage value and a third voltage value, a monitor voltage generation part configured to generate a monitor voltage waveform based on the high voltage output from the piezoelectric transformer, and a comparison part configured to compare the reference voltage waveform with the monitor voltage waveform to generate a comparison result, and configured to supply the comparison result to the switching control part. | 2010-12-02 |
20100302810 | VOLTAGE CONVERTERS WITH INTEGRATED LOW POWER LEAKER DEVICE AND ASSOCIATED METHODS - Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate. | 2010-12-02 |
20100302811 | SINGLE-STAGE POWER SUPPLY WITH POWER FACTOR CORRECTION AND CONSTANT CURRENT OUTPUT - An example controller includes first, second and third inputs, a delayed ramp generator and a drive signal generator. The first, second and third inputs are coupled to receive an input voltage sense signal, an output voltage sense signal, and an input current sense signal, respectively. The drive signal generator is coupled to receive an input charge control signal generated by an input charge control signal generator and a delayed ramp signal generated by a delayed ramp generator. The input charge control signal is generated responsive to an integral of the input current sense signal multiplied by a ratio of the input voltage sense signal to the output voltage sense signal, where the drive signal generator produces a drive signal responsive to the input charge control signal and the delayed ramp signal, the drive signal to be coupled to control a switch of a power supply to regulate an output of the power supply. | 2010-12-02 |
20100302812 | ADAPTER POWER SUPPLY - The present invention relates to an adapter power supply, which includes a switching unit for switching a DC voltage; a transformer which has a primary winding connected to the switching unit, a secondary winding electromagnetically coupled to the primary winding, and an auxiliary winding electromagnetically coupled to the primary winding; a rectifier for rectifying a voltage outputted from the transformer; and a controller for controlling the switching unit to operate according to the PWM scheme in a normal operation mode, and to operate according to a quasi-resonant scheme in a standby mode, by detecting information of a load connected to the rectifier. | 2010-12-02 |
20100302813 | DUAL-MODE CONSTANT LOAD CONTROL CIRCUITS AND ASSOCIATED METHODS - Dual-mode AC/DC power converters and associated methods of operation are disclosed herein. In one embodiment, the AC/DC converter includes a primary winding, a switching transistor coupled to the primary winding, the switching transistor configured to carry a drain-source current, and a feedback voltage port configured to carry a feedback voltage. The feedback voltage port is coupled to the switching transistor to switch off the switching transistor when the drain-source current reaches a peak current limit. The peak current limit increases with increasing feedback voltage if and only if the feedback voltage satisfies an ordered relationship with a threshold. | 2010-12-02 |
20100302814 | CONTROLLER FOR SWITCHING POWER SUPPLY - A switching power supply has an inductor that includes a coil. A chopper circuit chops the primary current drawn through the coil, for the inductor to output an induced current. A multifunction junction of the power supply has a multifunction voltage that is a function of a primary voltage that drives the coil. A first circuit suspends the chopping in response to a first sensed voltage crossing a first threshold, the first sensed voltage being a function of the multifunction voltage. A second circuit suspends the chopping in response to a second sensed voltage crossing a second threshold, the second threshold being a function of the multifunction voltage. | 2010-12-02 |
20100302815 | SWITCHING MODE POWER SUPPLY WITH A MULTI-MODE CONTROLLER - A switching mode power supply with a multi-mode controller is provided. The switching mode power supply may include a transformer having a primary winding and a secondary winding to supply power to a load. A feedback circuit may be included to generate a feedback signal that varies in relation to the load on the secondary winding. The multi-mode controller may include a switching circuit, a frequency control circuit and a current limiting circuit. The switching circuit may be coupled to the primary winding to control current flow through the primary winding. The frequency control circuit may control a switching frequency of the switching circuit based on the feedback signal. The current limiting circuit may limit current flow through the primary winding by causing the switching circuit to suspend current flow through the primary winding when the current reaches a peak current limit that is set based on the feedback signal. | 2010-12-02 |
20100302816 | SWITCHING MODE POWER SUPPLY WITH A SPECTRUM SHAPING CIRCUIT - In accordance with the teachings described herein, systems and methods are provided for a switching mode power supply. In one example, the switching mode power supply may include a transformer, a switching circuit and a switching control circuit. The transformer receives a DC input voltage on a primary winding and generates a DC output voltage on a secondary winding. The switching circuit, which may include a MOSFET switch, is coupled to the transformer and is configured to switch the transformer on and off. The switching control circuit generates a switching control signal to control the switching circuit in order to regulate the DC output voltage of the transformer. The switching control circuit is configured to generate the switching control signal as a function of a timing signal having a varying frequency, wherein the varying frequency of the timing signal causes a switching frequency of the switching circuit to vary over a period of time in order to reduce electromagnetic interference caused by the switching circuit. | 2010-12-02 |
20100302817 | DC-DC CONVERTER - A DC-DC converter includes a plurality of switch elements connected in series between both ends of a DC power source, a series circuit of a primary winding of a transformer and a capacitor, connected between a connection point of the plurality of switch elements and an end of the DC power source, a rectifying-smoothing circuit to rectify and smooth a voltage generated by a secondary winding of the transformer into a DC voltage, and a controller to change a switching frequency of the plurality of switch elements according to a feedback signal generated from the DC voltage and alternately turn on/off the plurality of switch elements. The controller includes a nonlinear response unit | 2010-12-02 |
20100302818 | POWER FACTOR CORRECTION CONVERTER CAPABLE OF FAST ADJUSTING LOAD - A power factor correction converter capable of fast adjusting load functions to (a) convert a single-phase AC voltage into a DC voltage output; (b) control an input current and an input voltage for a correspondent electrical phase, namely the power factor that is 1; and (c) control a DC output voltage level. The converter is provided with a booster-based AC-DC converter as a core, in which the circuit includes a rectification circuit, a switching circuit consisting of a DC inductor and a power crystal, an energy-saving capacitor, a protection circuit, a microprocessor, and auxiliary circuits around. The power factor control, output voltage, and current control and filter modules function in the form of software program instead of conventional hardware circuits. Further, a powerful controller uses an output current feedback to enhance the DC output voltage to suppress the disturbance of load. | 2010-12-02 |
20100302819 | SOLAR INVERTER AND CONTROL METHOD - A power generation system including a photovoltaic (PV) module to generate direct current (DC) power is provided. The system includes a controller to determine a maximum power point for the power generation system and a boost converter for receiving control signals from the controller to boost the power from the PV module to a threshold voltage required to inject sinusoidal currents into the grid. A DC to alternating current (AC) multilevel inverter is provided in the system to supply the power from the PV module to a power grid. The system also includes a bypass circuit to bypass the boost converter when an input voltage of the DC to AC multilevel inverter is higher than or equal to the threshold voltage. | 2010-12-02 |
20100302820 | Inverter drive power supply circuit - An inverter drive power supply circuit for driving a plurality of inverter switching devices that form an inverter circuit, includes a number N of transformers (N is an integer equal to or larger than 2) adapted to a push-pull method, each having a first winding and a second winding for a primary winding and a first winding and a second winding for a secondary winding, and supplying an output voltage of the secondary winding to the inverter switching devices. | 2010-12-02 |
20100302821 | Operating Resonant Load Circuit, Dimming Circuit and Dimming Method - An operating resonant load circuit, a dimming circuit and a dimming method are disclosed. The operating resonant load circuit includes: an input unit including a plurality of input terminals, for receiving an AC voltage; a rectifier, for transforming the AC voltage received by the input unit into a DC bus voltage; and a controller, for dividing the DC bus voltage based on an conducting status of the input terminals to output a corresponding DC reference voltage. The dimming circuit and dimming method use the operating resonant load circuit to perform dimming. | 2010-12-02 |
20100302822 | Flyback Power converters - Designs of flyback power converters are described. According to one aspect of the designs, a power converter includes a primary side including a primary winding of a transformer coupled to an input voltage and a primary switch for switching on or off the primary winding, a secondary side including a secondary winding of the transformer for generating an output voltage, and a loop controller configured to sample a feedback voltage representative of the output voltage, generate a gate signal with a fixed falling edge and an adjustable rising edge to drive the primary switch, and adjust a duty cycle of the gate signal by adjusting the rising edge of the gate signal until the feedback voltage converges to a reference voltage. | 2010-12-02 |
20100302823 | METHOD AND APPARATUS FOR ELECTRICAL BUS CENTERING - A bus centering device for use in an aircraft electrical power distribution system that includes a positive bus rail, a negative bus rail, and a ground is described. The device includes a central node, a first and second switching component configured to couple the central node to the positive rail and the negative rail for a first and second predetermined duty cycle, respectively. The device includes an inductive component coupled between the central node and ground, and is configured to maintain a voltage at the central node substantially equal to ground, wherein a voltage between the positive rail and the central node is maintained substantially equal to a voltage between the negative rail and the central node. The device includes a first and second current limiting device configured to maintain a continuity of current from the inductive component when the first and second switching components are turned off. | 2010-12-02 |
20100302824 | Power source apparatus - Disclosed herein is a power source apparatus utilizing a synchronous rectification system, including: a main transformer; a first field effect transistor; a second field effect transistor; and a gate driver. | 2010-12-02 |
20100302825 | SINGLE-PHASE VOLTAGE SOURCE AC-DC POWER CONVERTER AND THREE-PHASE VOLTAGE SOURCE AC-DC POWER CONVERTER - The present invention is a single-phase voltage source AC-DC power converter and a three-phase voltage source AC-DC power converter. Each of the single-phase voltage source AC-DC power converter and the three-phase voltage source AC-DC power converter includes a voltage source AC-DC power converting circuit that converts power from a DC voltage source into AC power to output the AC power from an AC terminal; and target current producing means that includes a filter voltage command device and a voltage controller, the filter voltage command device generating a filter voltage command value that becomes a reference of the AC power output from the AC terminal, the AC output voltage at the AC terminal being input as an input signal to the voltage controller, the voltage controller integrating a difference between the filter voltage command value from the filter voltage command device and the AC output voltage at the AC terminal, the target current producing means outputting a PWM command such that the integration value of the difference between the filter voltage command value from the filter voltage command device and the AC output voltage at the AC terminal becomes zero. | 2010-12-02 |
20100302826 | CAM CELL CIRCUIT OF NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A Code Address Memory (CAM) cell circuit of a nonvolatile memory device includes a CAM cell unit configured to store data, a control circuit unit configured to read data stored in the CAM cell unit and to output data read as read data, and register units each configured to comprise a number of registers for storing the read data. Each of the registers is reset such that first data are latched when a reset operation is performed, and is configured to maintain the first data or newly latch second data in response to the read data. | 2010-12-02 |
20100302827 | CODE ADDRESS MEMORY (CAM) CELL READ CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA OF CAM CELL - A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit. | 2010-12-02 |
20100302828 | ADDRESSING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND ADDRESSING METHOD THEREFOR - The addressing circuit of a semiconductor memory device includes a plurality of register units coupled to an input unit and a plurality of memory cell arrays, wherein the plurality of register units are configured to store inputted data in response to register control signals, and a control unit configured to generate the register control signals, using defect information of respective memory cell arrays, to control whether or not the register units store the inputted. | 2010-12-02 |
20100302829 | SEMICONDUCTOR MODULE AND DATA MEMORY MODULE HAVING THE SAME - A semiconductor module and a data memory module having the same are provided. The semiconductor module includes a substrate having a semiconductor device, a ground terminal, a protection pattern, and a switching element. The ground terminal and the protection pattern are formed on the substrate. The switching element connects the ground terminal and the protection pattern in series. The switching element electrically connects the protection pattern and the ground terminal when a voltage applied to the substrate is beyond a set voltage range. | 2010-12-02 |
20100302830 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a number of chips, each of the chips including a chip enable detection unit configured to simultaneously output a first signal and a second signal in response to a chip enable signal, a chip operation detection unit configured to output an operation state signal in response to the first signal, and an internal circuit configured to operate in response to a power source voltage and a control signal in response to the second signal being received. | 2010-12-02 |
20100302831 | SEMICONDUCTOR STORAGE DEVICE - A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line. | 2010-12-02 |
20100302832 | NON-VOLATILE LOGIC DEVICES USING MAGNETIC TUNNEL JUNCTIONS - The present disclosures concerns a register cell comprising a differential amplifying portion containing a first inverter coupled to a second inverter such as to form an unbalanced flip-flop circuit; a first and second bit line connected to one end of the first and second inverter, respectively; and a first and second source line connected to the other end of the first and second inverter, respectively; characterized by the register cell further comprising a first and second magnetic tunnel junction electrically connected to the other end of the first and second inverter, respectively. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. | 2010-12-02 |
20100302833 | Semiconductor device having nonvolatile memory element and manufacturing method thereof - To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other. | 2010-12-02 |
20100302834 | F-RAM device with current mirror sense amp - A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device. | 2010-12-02 |
20100302835 | LIMITED CHARGE DELIVERY FOR PROGRAMMING NON-VOLATILE STORAGE ELEMENTS - A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. In one aspect a circuit that has one or more clock inputs is run for a predetermined number of clock cycles. The circuit generates an amount of charge over the predetermined number of clock cycles. At most the amount of charge is provided to non-volatile storage element to program the non-volatile storage element. It is determined whether the non-volatile storage element is programmed to a desired state as a result of providing at most the amount of charge to the non-volatile storage element. Techniques disclosed herein can be applied to program memory cells other than memory cells with reversible resistance-switching elements. | 2010-12-02 |
20100302836 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, Ni | 2010-12-02 |
20100302837 | MEMORY WITH READ CYCLE WRITE BACK - A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle. | 2010-12-02 |
20100302838 | Read disturb-free SMT reference cell scheme - We describe a reference cell structure for determining data storing cell resistances in an SMT (spin moment transfer) MTJ (magnetic tunneling junction) MRAM array by comparing data cell currents with those of the reference cell. Since the reference cell also utilizes spin moment transfer (SMT) magnetic tunneling junction (MTJ) cells, there would ordinarily be the danger that the act of reading the reference cell could change its magnetization orientations and be a source of error for subsequent comparisons. Therefore the present invention describes a new circuit arrangement for the reference cell that directs read currents through two SMT MTJ cells in opposite directions so that the transfer of spin moments cannot affect the relative magnetization directions of the cells. | 2010-12-02 |
20100302839 | STATIS SOURCE PLANE IN STRAM - A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions. | 2010-12-02 |
20100302840 | PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS FOR CONTROLLING DATA TRANSMISSION - A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat. | 2010-12-02 |
20100302841 | PHASE CHANGE MEMORY APPARATUS AND TEST CIRCUIT THEREFOR - A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal. | 2010-12-02 |
20100302842 | SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF, DATA PROCESSING SYSTEM, AND DATA PROCESSING DEVICE - A semiconductor memory device includes: first and second impurity diffusion layers that form a part of a semiconductor substrate, each of the impurity diffusion layers function as one and the other of an anode and a cathode, respectively of a pn-junction diode; a recording layer connected to the second impurity diffusion layer; and a cylindrical sidewall insulation film provided on the first impurity diffusion layer. At least a part of the second diffusion layer and at least a part of the recording layer are formed in a region surrounded by a sidewall insulation film. According to the present invention, because a pillar-shaped pn-junction diode and the recording layer are formed in a self-aligned manner, the degree of integration of a semiconductor memory device can be increased. Further, because a silicon pillar is a part of the semiconductor substrate, a leakage current attributable to a crystal defect can be reduced. | 2010-12-02 |
20100302843 | Spin Transfer Torque - Magnetic Tunnel Junction Device and Method of Operation - A method is disclosed that includes controlling current flow direction for current sent over a source line or a bit line of a magnetic memory device. A current generated magnetic field assists switching of a direction of a magnetic field of a free layer of a magnetic element within a spin transfer torque magnetic tunnel junction (STT-MTJ) device. | 2010-12-02 |
20100302844 | METHOD AND APPARATUS FOR PROVIDING A NON-VOLATILE MEMORY WITH REDUCED CELL CAPACITIVE COUPLING - A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling. | 2010-12-02 |
20100302845 | MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME - The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits. | 2010-12-02 |
20100302846 | CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY - A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell. | 2010-12-02 |
20100302847 | MULTI-LEVEL NAND FLASH MEMORY - According to one embodiment, a multi-level NAND flash memory executes a writing of an upper data to a LM flag. When an address of a flag assigns a bad column, a data transfer control circuit and a address control circuit control a write operation of upper data in the flag by an operation of transmitting the upper data of the flag from the bad column data hold circuit to the data latch circuit, reading the lower data of the flag from a redundancy column storing the flag into the data latch circuit, generating an address of a redundancy column storing the flag based on the address of the flag, and forcefully inverting the lower data of the flag in the data latch circuit by using the address of the redundancy column storing the flag. | 2010-12-02 |
20100302848 | TRANSISTOR HAVING PERIPHERAL CHANNEL - Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel region is formed around a perimeter of the source/drain region. Such transistors should facilitate a reduction in edge effect and leakage as the channel of the transistor is not bordering on an isolation region. Additionally, the use of a source/drain region extending through a channel region facilitates high-power, high-voltage operation. | 2010-12-02 |
20100302849 | NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE - Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration. | 2010-12-02 |
20100302850 | Storage device and method for reading the same - The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution. | 2010-12-02 |
20100302851 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device and a method of programming the device includes a memory cell array configured to have a number of memory cells, a row decoder coupled to the memory cells through word lines, page buffers coupled to the memory cells through bit lines, and a control unit configured to output correction voltages for reducing a difference in voltage between a selected one of the word lines and a channel region of a selected one of the memory cells in response to a program operation being performed. | 2010-12-02 |
20100302852 | NONVOLATILE MEMORY DEVICE AND METHOD OF VERIFYING THE SAME - A nonvolatile memory device having a memory cell array configured to include a number of memory cells coupled to a bit line, a control circuit configured to output a code signal in response to a verification operation command signal during a verification operation being performed, a page buffer operation voltage generator configured to generate a precharge signal and a sense signal in response to the code signal, and a page buffer configured to precharge the bit line in response to the precharge signal and to sense data programmed into the memory cell in response to the sense signal. A sense signal having a sequentially lowered voltage level is outputted in response to the verification operation being repeatedly performed. | 2010-12-02 |
20100302853 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a high voltage generation unit configured to generate a program voltage and a pass voltage, a block selection unit coupled to the high voltage generation unit through global word lines, a memory cell array coupled to the block selection unit through word lines, a discharge unit coupled to the global word lines and configured to change a level of voltage supplied to the global word lines, and a discharge control unit configured to generate a discharge signal, and transfer the discharge signal to the discharge unit in response to the program voltage. | 2010-12-02 |
20100302854 | Area-Efficient Electrically Erasable Programmable Memory Cell - Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed. | 2010-12-02 |
20100302855 | MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME - The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively. | 2010-12-02 |
20100302856 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING AND READING THE SAME - A nonvolatile memory device includes a control circuit configured to generate a control signal by counting a number of first data among input data, a buffer unit configured to temporarily store the input data, invert the input data in response to the control signal, and store the inverted data or the input data as the program data, and a memory cell block configured to receive and store the program data. | 2010-12-02 |
20100302857 | METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS - A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation. | 2010-12-02 |
20100302858 | DATA LINE MANAGEMENT IN A MEMORY DEVICE - Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells. | 2010-12-02 |
20100302859 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a memory block including a number of cell strings, a channel voltage detection unit configured to detect channel voltages of the cell strings in which the channel voltages are changed based on voltages supplied to memory cells of the cell strings during a program operation and to generate channel voltage code based on an average channel voltage of the detected channel voltages, and a voltage supply unit configured to change a level of a pass voltage of the voltages supplied to memory cells in which the pass voltage is supplied to the memory cells during the program operation according to the channel voltage code. | 2010-12-02 |
20100302860 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, including page buffers each configured to store program data for memory cells or store data read from the memory cells, and a control unit configured to, when a program operation is first performed after power is supplied, count a number of program pulses until a verification operation using a first verification voltage is a pass, compare the counted number and a first number of program pulses, select either the first or second program start voltages according to a result of the comparison, and control the program operation to be performed using the selected program start voltage until the power is off. | 2010-12-02 |
20100302861 | Program and erase methods for nonvolatile memory - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device. | 2010-12-02 |
20100302862 | Non-volatile Memory Device - The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage. | 2010-12-02 |
20100302863 | Reading Method for MLC Memory and Reading Circuit Using the Same - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages. | 2010-12-02 |
20100302864 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level. | 2010-12-02 |
20100302865 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device comprises a memory cell array comprising memory cells, an operation voltage generation unit configured to generate a first pass voltage when a verification voltage for a memory cell to be programmed is higher than a reference voltage and to generate a second pass voltage lower than the first pass voltage when the verification voltage for the memory cell to be programmed is lower than the reference voltage, a high voltage switch unit configured to transfer the first or second pass voltage to global word lines other than a selected global word line and to transfer the verification voltage to the selected global word line of the global word lines, and a block selection unit coupled between the global word lines and word lines and configured to transfer the verification voltage and the first or second pass voltage to the word lines. | 2010-12-02 |
20100302866 | METHOD OF TESTING FOR A LEAKAGE CURRENT BETWEEN BIT LINES OF NONVOLATILE MEMORY DEVICE - A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer. | 2010-12-02 |
20100302867 | CIRCUIT FOR PRECHARGING BIT LINE AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - A nonvolatile memory device includes a memory cell array configured to comprise a number of cell strings, a number of page buffers each coupled to the cell strings of the memory cell array through bit lines, and a bit line precharge circuit configured to precharge a selected bit line up to a voltage of a first level before one of the page buffers precharges the selected bit line. | 2010-12-02 |
20100302868 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell. | 2010-12-02 |
20100302869 | FLASH MEMORY DEVICE OPERATING AT MULTIPLE SPEEDS - A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats. | 2010-12-02 |
20100302870 | Nonvolatile memory device and method of operating and fabricating the same - Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line. | 2010-12-02 |
20100302871 | CONCURRENT INTERSYMBOL INTERFERENCE ENCODING IN A SOLID STATE MEMORY - Methods and devices are provided for concurrent intersymbol interference encoding in a solid state memory. In an illustrative embodiment, a write data signal is received as input to a processing component. A channel-effect-corrected encoding of the write data signal is produced, where the channel-effect-corrected encoding is based on the write data signal and a channel effect factor that models concurrent intersymbol interference of the write data signal in a target data storage component in communicative connection with the processing component. An output signal based on the channel-effect-corrected encoding of the write data signal is produced from the processing component. | 2010-12-02 |
20100302872 | BUFFER CONTROL SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - A buffer control signal generation circuit includes a burst start signal generator, a command decoder, a burst controller, and a burst column controller. The burst start signal generator shifts a write pulse into a first period to generate a first burst start signal and shifts the write pulse into a second period to generate a second burst start signal, such that the second period being shorter than the first period. The command decoder generates a burst period pulse and a column active pulse in response to the second burst start signal and a column control signal. The burst controller receives the column active pulse and buffers the burst period pulse to generate a burst end signal. The burst column controller generates the column control signal from the burst end signal and the column active pulse. | 2010-12-02 |
20100302873 | MODE-REGISTER READING CONTROLLER AND SEMICONDUCTOR MEMORY DEVICE - A mode-register reading controller includes a switching signal generator, first and second transmitters, and a control signal generator. The switching signal generator generates a switching signal that is activated when the reset command is input during a mode-register reading operation. The first transmitter buffers and transfers the mode-register read signal in response to the switching signal. The second transmitter, in response to the switching signal, delays and transfers the enable signal at a predetermined delay time. The control signal generator receives a signal from one of the first and second transmitters and generates a first control signal and a second control signal for transferring the data into a data output buffer from the input/output line. | 2010-12-02 |
20100302874 | SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING THE SAME, AND CONTROLLER - To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased. | 2010-12-02 |
20100302875 | SEMICONDUCTOR DEVICE HAVING NONVOLATILE MEMORY ELEMENT AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation. | 2010-12-02 |
20100302876 | PACKAGE APPARATUS AND METHOD OF OPERATING THE SAME - A package apparatus includes at least one memory chip, a voltage detection circuit configured to make a determination of whether a voltage supplied to the memory chip is a specific voltage or higher, and a controller configured to control an operation of the memory chip based on a result of the determination. | 2010-12-02 |
20100302877 | MEMORY DEVICE HAVING REDUCED STANDBY CURRENT AND MEMORY SYSTEM INCLUDING SAME - A memory device includes a plurality of banks, a first generator generating standby current in response to a standby signal, and a switching circuit supplying the standby current to at least one of the plurality of banks in response to a plurality of active signals. | 2010-12-02 |
20100302878 | SENSE AMPLIFIER AND DRIVING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SENSE AMPLIFIER - The semiconductor memory device includes a bank having a cell array and a sense amplifier. A back bias voltage generating unit supplies a back bias voltage to the cell array of the bank. A negative drive voltage generating unit generates negative driving voltages including a normal pull-up voltage, an overdrive voltage, a normal pull-down voltage, and a negative voltage and supplies the negative driving voltages to the sense amplifier of the bank. A switching unit opens a connection between the back bias voltage generating unit and the negative drive voltage generating unit when in active mode and shares the back bias voltage between the back bias voltage generating unit and the negative drive voltage generating unit when in a refresh mode, in response to an external command. | 2010-12-02 |
20100302879 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 2010-12-02 |
20100302880 | DUAL POWER RAIL WORD LINE DRIVER AND DUAL POWER RAIL WORD LINE DRIVER ARRAY - A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is coupled between the word line and a node. A pull-down unit is coupled between the node and a ground. A pull-up unit is coupled between the node and a second supply voltage higher than or equal to the first supply voltage. The signal buffering unit provides a word line signal corresponding to the predecode signal to the memory array via the word line when the pull-down unit is turned on by the predecode signal and a first pulse signal and the pull-up unit is turned off by a second pulse signal. There is no level shifter on a critical timing path of the dual power rail word line driver. | 2010-12-02 |
20100302881 | VOLTAGE GENERATION CIRCUIT AND NONVOLATILE MEMORY DEVICE USING THE SAME - A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit. | 2010-12-02 |
20100302882 | Random Access Memory for Use in an Emulation Environment - A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. | 2010-12-02 |
20100302883 | Method of estimating self refresh period of semiconductor memory device - In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal. | 2010-12-02 |
20100302884 | Method of preventing coupling noises for a non-volatile semiconductor memory device - Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result. | 2010-12-02 |
20100302885 | DELAY LOCKED LOOP AND METHOD AND ELECTRONIC DEVICE INCLUDING THE SAME - A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals. The second delay locked loop receives the data signal, the selected second clock signal, and the plurality of phase resolution control signals, generates a plurality of third clock signals having variable phase resolution based on the selected second clock signal and at least one of the plurality of phase resolution control signals, and performs a locking operation on the plurality of third clock signals and the data signal. | 2010-12-02 |
20100302886 | MAT COMPRESS CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A mat compress circuit includes a pre-control signal generator that generates a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank selection address in a mat compression test, and a control signal transmitter that inverts and transfers the first and second pre-control signals in response to a switching signal activated when there is an input of a block selection address in the mat compression test. | 2010-12-02 |
20100302887 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected to the memory cell and the spare memory cell, a data holding circuit connected to the decoder, and a battery which supplies electric power to the data holding circuit. The spare memory cell operates in accordance with an output from the data holding circuit. | 2010-12-02 |
20100302888 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND INSPECTION METHOD THEREOF - A memory cell potentially including a retention fault attributable to a random change over time of data retention capability is screened by applying a bias to a gate electrode such that holes are accumulated on an interface of a substrate that is a component of a memory cell transistor on the side of the gate electrode and, after applying the bias, performing a pause-refresh test for inspecting the data retention capability of the memory cell. | 2010-12-02 |
20100302889 | SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a plurality of memory cells, a refresh request generator circuit for generating a refresh request signal to refresh the plurality of memory cells based on a number of clock cycles elapsed in a clock signal, a clock cycle detector circuit for detecting the clock cycle of the clock signal, and a refresh controller circuit for controlling a number of memory cells to refresh from among the plurality of memory cells, in accordance with the detected clock cycle. | 2010-12-02 |
20100302890 | Electrical Fuse, Semiconductor Device Having the Same, and Method of Programming and Reading the Electrical Fuse - Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the first anode to the cathode, and a second fuse link couples the second anode to the cathode. | 2010-12-02 |
20100302891 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device includes a power-up operation unit configured to perform a power-up operation in response to a power-up enable signal and to output a powered-up control signal, and configured to output a power-up completion signal after the power-up operation is completed, an internal circuit configured to operate in response to the powered-up control signal, and a power-up detection unit configured to output a power-up flag signal in response to the power-up completion signal. | 2010-12-02 |
20100302892 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase. | 2010-12-02 |
20100302893 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER THAT CONTROLS THE SAME, AND INFORMATION PROCESSING SYSTEM - To include a power-down control circuit that suspends an operation of a predetermined internal circuit in response to a power-down command, and an external terminal to which a selection signal is input from outside simultaneously with issuance of a power-down command. The power-down control circuit suspends an operation of a DLL circuit when the selection signal is at a low level, and continues an operation of the DLL circuit when the selection signal is at a high level. According to the present invention, by using the selection signal input simultaneously with a power-down command, mode selection can be made on-the-fly. | 2010-12-02 |
20100302894 | WORD LINE SELECTION CIRCUIT AND ROW DECODER - A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals. | 2010-12-02 |
20100302895 | ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK GENERATION - A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals. | 2010-12-02 |
20100302896 | Systems and methods for Stretching Clock Cycles in the Internal Clock Signal of a Memory Array Macro - Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro receives a regular periodic external clock signal and generates an internal clock signal. The local clock buffer includes a first signal path that has one or more faster-than-nominal components so that the first rising edge of the internal clock cycle occurs early than it would in a clock buffer with nominal components. When the memory array macro is active for a data access, the local clock buffer stretches a clock cycle of the internal clock signal so that the first and second half-periods of the internal clock cycle are each greater than the half-periods of the external clock signal. | 2010-12-02 |
20100302897 | TUMBLER WITH STIRRING ASSEMBLY - A container having a removable lid, a hollow interior for storing contents, and a stirring assembly. The stirring assembly includes a rotatable wheel mounted to an outside portion of the removable lid and a shaft extending into the hollow interior of the container. The rotatable wheel is manually rotatable about a first axis of rotation. The shaft is rotatable by the wheel. When the wheel is rotated about the first axis of rotation, the wheel rotates the shaft about a second axis of rotation. At least one paddle extends outwardly from the shaft into the hollow interior of the container and stirs or agitates the contents of the container when the rotation of the shaft about the second axis of rotation rotates the at least one paddle inside the hollow interior of the container. | 2010-12-02 |