48th week of 2008 patent applcation highlights part 27 |
Patent application number | Title | Published |
20080291674 | Lighting device utilizing an LED light source for projection of a light pattern onto a surface - A lighting device utilizing a light emitting diode (LED) light source for projection of a light pattern onto a surface with an LED lamp socket, an adjustable LED lens attachment, and a mechanism for varying the focal length by adjusting the distance from the LED lamp socket relative to the lens attachment. The device preferably utilizes a replaceable, multiple LED lamp as a light source and a lighting fixture allowing for imaging of the LED light source onto a surface at varying distances from the light source. The device illuminates a surface with an image of the LED element array present in the replaceable lamp. Through adjustment of the LED lamp light source with respect to the imaging lens, the image of the LED array may be focused and distorted for a desired visual effect. | 2008-11-27 |
20080291675 | LIGHT EMITTING DIODE LAMP - A light emitting diode (LED) lamp including a substrate, a plurality of wire units, a plurality of LED chips, a lamp cap, and a control circuit module is provided. The substrate has a carrying portion and a ring frame connected to the periphery thereof. The carrying portion has a plurality of openings. The wire units are respectively disposed inside the openings. Each wire unit has a wire and an insulating material covering the periphery of the wire, such that the wire is electrically isolated from the substrate. The LED chips are disposed on the carrying portion, and each LED chip is electrically connected to the corresponding wires. The lamp, cap is disposed on the bottom of the substrate and has two power contacts. The control circuit module is disposed between the substrate and the lamp cap and electrically connected to wires and power contacts, to control operations of LED chips. | 2008-11-27 |
20080291676 | SIMULATED HOLIDAY LIGHT DISPLAYS AND METHOD OF HOLIDAY DECORATING USING SAME - A simulated holiday light display is provided. The simulated holiday light display includes one or more model buildings decorated and designed in any style with a plurality of first and second openings in the walls of the one or more model building, and a light source within the model building. Simulated holiday lights such as translucent beads or the like are received in at least a portion of the plurality of first openings. The plurality of second openings appears as window openings. When illuminated, the light from within the model building shines exteriorly of the model building though the simulated holiday lights and the window openings to create the appearance of a home or business that has been decorated with holiday lights, including Christmas string lights. Changing the color, design, placement of the simulated holiday lights changes the holiday light design on the simulated holiday light display. | 2008-11-27 |
20080291677 | LED LAMP WITH A PERFORATED COVER PLATE - A LED lamp includes a housing, a circuit unit, and a cover plate. The housing includes a housing body surrounding an axis and having an opening. The circuit unit is disposed in the housing body, and includes a base plate that has a first plate surface facing the opening in the housing body, and a light emitting unit that is mounted to the first plate surface of the base plate. The cover plate is disposed in the housing body between the base plate of the circuit unit and the opening in the housing body, and is formed with a through hole unit corresponding in position to the light emitting unit of the circuit unit. | 2008-11-27 |
20080291678 | Illumination Unit for Satellite Dish - The invention is a light ( | 2008-11-27 |
20080291679 | VENTILATION FAN AND LIGHT - A ventilation fan and light ( | 2008-11-27 |
20080291680 | Luminaire with a Compound Parabolic Reflector - Luminaires for illuminating a target zone having target zone subregions in front of and to the sides of the luminaire. The luminaire includes a housing, a lamp holder in the housing positioned to support an electric lamp in a generally vertical orientation, and a compound parabolic reflector in the housing partially surrounding a lamp light-emitting segment location having plural regions. Preferred forms of the compound parabolic reflector include segmented center and side portions. The preferred segmented center portion has a first plurality of two-dimensional parabolic segments each of which has a focal point in a different one of the plural light-emitting segment location regions. The preferred segmented side portions are each provided with a second plurality of two-dimensional parabolic segments having focal points along the light-emitting segment location. The parabolic segments are effective to direct a preponderance of light toward the plural target zone subregions. | 2008-11-27 |
20080291681 | Inflatable portable lamp - The lamp includes an inflatable balloon-like enclosure composed of translucent or transparent material. When the lamp is not in use, the enclosure may be deflated and stowed within a receptacle which serves as a base for the lamp. The lamp is illuminated by a strip of one or more rings of light emitting diodes suspended within the enclosure. Alternatively. The lamp may be illuminated by incandescent or fluorescent bulbs or white or black halide lights suspended within the enclosure. | 2008-11-27 |
20080291682 | LED luminance-augmentation via specular retroreflection, including collimators that escape the etendue limit - The diffuse reflectivity of an LED source is utilized to recycle some of its emission, thereby enabling a luminaire to escape the étendue limit. Retroreflectors intercept the rays destined for the outer part of the luminaire aperture, which can then be truncated. The resulting smaller aperture has the same beam-width as the full original, albeit with lesser flux due to recycling losses. A reduction to half the original area is possible. | 2008-11-27 |
20080291683 | Near Field Lens - A lens for use with a light emitting source is provided. The lens has a main body with a light-collecting face and a light-emitting face and which defines an optical axis extending through the centers of these two faces. A pocket for receiving light from the light source is defined in the light-collecting face by an inner axially-facing surface surrounded by an inner radially-facing surface. The inner axially-facing surface is concave and has a spherical shape. The inner radially-facing surface has a non-spherical, tapered shape and extends between the axially-facing surface and an open end of the pocket. A light assembly incorporating the lens includes a light-emitting diode. | 2008-11-27 |
20080291684 | PILLOW READING LAMP - A reading lamp includes a lamp assembly. The lamp assembly includes a housing has a first aspect and a second aspect in opposed relation to the first aspect. A lamp is situated substantially at the first aspect. The lamp is configured to cast illumination away from the first and second aspects in response to application of a current between a first and second terminal. A cushion is configured to support the housing substantially at the second aspect. | 2008-11-27 |
20080291685 | Vehicle-purpose lighting tool - A vehicle-purpose lighting tool is featured by comprising: a light-conducting member having a front light-emitting plane, a rear plane having a concave/convex shape, and a side edge plane; and a light source arranged at a position opposite to the side edge plane; in which within external light which is entered via the front light-emitting plane into the light-conducting member, a portion of the external light which is directly traveled to the side edge plane is totally reflected on a boundary plane of the side edge plane portion; a plurality of reflecting portions are formed on the rear plane and are coupled to each other via a coupling portion in such a direction that the reflecting portions are separated apart from the side edge plane side; and distances between the plurality of reflecting portions and the front light-emitting plane are changed in a discontinuous manner along the separating direction. | 2008-11-27 |
20080291686 | EXTENDED AVIONICS LCD BACKLIGHT - An aircraft avionics display assembly comprises a first and second liquid crystal display, each operable to display avionics flight data in an aircraft. A backlight is operable to backlight both the first and second liquid crystal displays. In some embodiments, the backlight comprises a primary light source and a redundant light source, wherein the primary light source and the redundant light source are controlled by a common backlight controller. | 2008-11-27 |
20080291687 | Optical filter assembly and method - A filter assembly includes a mounting element for receiving and mounting on a forward portion of a headlight, and a central opening, and a frame rotatably coupled to the mounting element, the frame having an optical filter for selectively blocking wavelengths below a first limit from the optical path between the source and the output. The frame is rotatable between a closed position in which the filter substantially covers the central opening of the mounting element, and an open position in which the central opening of the mounting element is substantially open. Both the mounting element and the frame have a central axis through their respective openings, which axis is substantially the central axis of light being emitted from a headlight when the filter assembly is mounted on a headlight. | 2008-11-27 |
20080291688 | LIGHT EMITTING DEVICE MODULE - A light emitting device module is provided. The light emitting device module includes a plurality of light emitting devices; a submount on which the light emitting devices are mounted; and a heat-radiant substrate to which the submount is fixed. The submount includes a positive front surface electrode; a negative front surface electrode; at least one relay front surface electrode, wherein the plurality of light emitting devices are electrically coupled to each other in series via the at least one relay front surface electrode; a plurality of through electrodes; a positive back surface electrode coupled to the positive front surface electrode via a through electrode; a negative back surface electrode coupled to the negative front surface electrode via a through electrode; and at least one relay back surface electrode which is coupled to the at least one relay front surface electrode via a through electrode. The heat-radiant substrate includes a positive circuit electrode bonded to the positive back surface electrode; a negative circuit electrode bonded to the negative back surface electrode; and at least one relay circuit electrode bonded to the at least one relay back surface electrode and being floated electrically. | 2008-11-27 |
20080291689 | LIGHT SOURCE DEVICE AND VEHICLE LIGHTING DEVICE - An LED light source device can have a simple configuration which can easily create a desired light distribution pattern with a low profile and light weight. An illumination apparatus and a vehicle lighting device can also be configured to use the LED light source device. The light source device can include a light guide plate made of a flat plate-like material that is transparent in the visible range, and which has a front surface serving as a light emission surface. A point light source can be opposed to an end surface of the light guide plate. A rear surface of the light guide plate can include a luminance control element configured to control a luminance distribution on the light emission surface. The luminance control element controls light from the light source, incident through the end surface of the light guide plate, so that a reduced inversion of a light distribution pattern that is to be emitted is formed on the light emission surface as the luminance distribution. The light guide plate can include a polarizing film for making the light emission surface emit p-polarized (parallel polarized) light. | 2008-11-27 |
20080291690 | Headlamp Adjuster - A headlamp adjuster includes an output shaft driven by a co-rotatable gear. Threads on the shaft engage splines in a thin wall boss, the splines having limited circumferential engagement with the screw. The thin wall boss deflects outwardly in response to forces that build in the engagement of the shaft and splines, to release driving engagement between the splines and the shaft. | 2008-11-27 |
20080291691 | SIDE-EMISSION TYPE LIGHT-EMITTING DIODE AND A BACKLIGHT UNIT USING THE LIGHT-EMITTING DIODE - A side-emission type light-emitting diode including: a first substrate having a concave formed in one of side surfaces of the first substrate, the concave including an inner surface which is configured to be a first reflecting surface; an LED-element-mounting board of thin plate shape, arranged on the lower surface of the first substrate, the board configured to close the concave at the lower surface of the first substrate; an LED element mounted on the board and arranged in the concave; and a light-transmitting resin filled in the concave and configured to seal the LED element. | 2008-11-27 |
20080291692 | IMPRESSION-TYPE WRITING BOARD - An exemplary writing board includes a deformable thin film, a backlight module, and a light-transmissive film. The thin film has a writing surface and a light incident surface on an opposite side of the thin film to the writing surface. The backlight module is arranged adjacent to the light incident surface and configured for providing light incident onto the light incident surface. The light-transmissive film is arranged between the thin film and the backlight module. A clearance is formed between the light-transmissive film and the thin film, and a distance of the clearance, along a thicknesswise direction of the thin film, is less than or equal to a maximum deformation amount of the thin film at the same direction. | 2008-11-27 |
20080291693 | STRUCTURE OF PLANAR ILLUMINATOR - A structure of a backlight module, which includes: a light source frame, including: a top plate having a plurality of slits; a bottom plate arranged apart from the top plate; and at least two edge plates arranged oppositely, wherein each of the edge plates has a top end and a bottom end, and both of the bottom ends are separately connected with the bottom plate; wherein the inner surfaces of the top plate, the bottom plate and the edge plates form a reflective cavity; and at least one light source arranged in the reflective cavity. There are several advantages of the backlight module according to the present invention, which includes: 1. the required uniformity and brightness of the backlight module are achieved; 2. its weight is largely reduced; and 3. it can be tiled up to form a large-area backlight module for a large size display. | 2008-11-27 |
20080291694 | PLANAR LIGHT SOURCE DEVICE AND DISPLAY DEVICE - The present invention is aimed to obtain a highly reliable planar light source device even when an ambient temperature is high, without lowering brightness of the planar light source device. A planar light source device of the present invention includes a light source (point light source), a first light guide plate having an incident surface and an emitting surface for emitting planar light, and a second light guide plate having an incident surface opposing to the light source (point light source) and an emitting surface opposing to the incident surface of the first light guide plate, wherein a distance from the incident surface to the emitting surface opposite to each other of the second light guide plate (light guide distance) is not less than 1.5 mm. | 2008-11-27 |
20080291695 | Display Device - The present invention is to provide a display device capable of displaying a prescribed display pattern by making the pattern luminous as needed, while the rear side can usually be seen through easily. In order to achieve it, a display pattern | 2008-11-27 |
20080291696 | Integrated Light Guide Panel and Method of Manufacturing the Same - An integrated light guide panel for use in a backlight unit for an LCD and a method for manufacturing the same are disclosed. The integrated light guide panel includes a light guide panel for guiding light, to form surface light, a reflective coating layer arranged beneath the light guide panel, to reflect light emerging from a lower surface of the light guide panel such that the light is again incident to the light guide panel, a diffusive coating layer arranged over the light guide panel, to diffuse light emerging from the light guide panel, a prism coating layer arranged over the diffusive coating layer, to concentrate light emerging from the diffusive coating layer, and low refractive coating layers respectively arranged between the light guide panel and the reflective coating layer and between the light guide panel and the diffusive coating layer. | 2008-11-27 |
20080291697 | Light guide plate with protrusion,backlight module with same, and liquid crystal display with same - A light guide plate includes: a light emitting surface; a bottom surface opposite to the light emitting surface; a light incident surface perpendicularly connected with the light emitting surface; a first side surface perpendicularly connected with both the light incident surface and the light emitting surface; a second side surface opposite to the first side surface; two protrusions outwardly extending from the first side surface; and two protrusions outwardly extending from the second side surface. A thickness of each protrusion of the first side surface decreases with increasing distance away from the light incident surface, and a thickness of each protrusion of the second side surface also decreases with increasing distance away from the light incident surface. | 2008-11-27 |
20080291698 | Control Method and Controller for Pwm Cyclo-Converter - A control method for a PWM cyclo-converter is provided in which a voltage can be accurately generated even when a voltage command is small. | 2008-11-27 |
20080291699 | Low-Loss Rectifier with Optically Coupled Gate Shunting - A rectifier circuit ( | 2008-11-27 |
20080291700 | POWER CONVERTER HAVING PWM CONTROLLER FOR MAXIMUM OUTPUT POWER COMPENSATION - A PWM controller compensates a maximum output power of a power converter having a power switch. The PWM controller includes an oscillator for generating a saw signal and a pulse signal, a power limiter coupled to the oscillator for generating a saw-limited signal in response to the saw signal, and a PWM unit coupled to the power limiter and the oscillator to generate a PWM signal for controlling the power switch in response to the saw-limited signal and the pulse signal. The saw-limited signal has a level being flattened during a period of time before an output voltage is generated, and is then transformed to a saw-limited waveform after the period of time. | 2008-11-27 |
20080291701 | POWER CONVERTER FOR COMPENSATING MAXIMUM OUTPUT POWER AND PWM CONTROLLER FOR THE SAME - A PWM controller compensates a maximum output power of a power converter, and includes a PWM unit and a compensation circuit. The PWM unit generates a PWM signal for controlling a power switch to switch a power transformer, which has a primary winding connected to the power switch and is supplied with an input voltage of the power converter. A pulse width of the PWM signal is correlated to an amplitude of the input voltage. The compensation circuit generates a current boost signal in response to the PWM signal by pushing up a peak value of a current-sense signal generated by a current-sense device in response to a primary-side switching current of the power transformer. A peak value of the current boost signal is adjusted by the pulse width of the PWM signal for compensating a difference of the maximum output power caused by the amplitude of the input voltage. | 2008-11-27 |
20080291702 | SWITCHING POWER SUPPLY APPARATUS - In a switching power supply apparatus, an inductor, a transformer, a first switching circuit, a second switching circuit, and a capacitor are connected to each other so that a first switching element and a second switching element can be alternately turned on and off, an output can be obtained from a secondary winding of the transformer, and an output voltage can be controlled by controlling the ON period of the first switching element. The secondary winding of the transformer is connected to a first rectifying and smoothing circuit. A first control circuit is configured to operate using a DC voltage supplied from a second rectifying and smoothing circuit. After the second switching element has been turned on, the second switching element is forcefully turned off at a predetermined time set by a turn-off circuit included in a second control circuit that operates using an AC voltage. | 2008-11-27 |
20080291703 | SIGNAL CONVERTING APPARATUS AND SIGNAL CONVERSION METHOD - A signal converting apparatus is disclosed and includes a swing range converting unit converting an error signal swinging in a first swing range to an adjusted error signal swinging in a second swing range, an oscillator generating a periodic oscillation signal swinging in approximately the second swing range, and a comparator receiving and comparing the adjusted error signal and the oscillation signal, and generating a pulse-width modulated signal in relation to the comparison. | 2008-11-27 |
20080291704 | DRIVING DEVICE AND METHOD FOR PROVIDING AN AC DRIVING SIGNAL TO A LOAD - In a driving device and method for providing an AC driving signal to a load, a first voltage converting unit converts an external AC voltage signal into a DC voltage signal using pulse width modulation in response to a feedback signal that is generated by a summing unit based on a standard voltage signal generated by a voltage detecting unit from the DC voltage signal, and a current detecting signal corresponding to a current flowing through the load and generated by a current detecting unit. A second voltage converting unit converts the DC voltage signal from the first voltage converting unit into the AC driving signal based on an external burst signal, and outputs the AC driving signal to the load. | 2008-11-27 |
20080291705 | Method for regulating a voltage or a current of an RLC filter, a recording medium and vehicles for this method - This deadbeat control method for regulating an output voltage U | 2008-11-27 |
20080291706 | COMMON MODE FILTER SYSTEM AND METHOD FOR A SOLAR POWER INVERTER - A photovoltaic system, method and apparatus are disclosed. In an exemplary embodiment, the system includes a photovoltaic array, a distribution system that distributes power within a premises of a demand-side energy consumer, an inverter coupled to the distribution system that is configured to convert DC power from the photovoltaic array to AC power and apply the AC power to the distribution system, a damping portion configured to damp high frequency voltages derived from the inverter, and trapping circuitry coupled to the damping portion that is configured to reduce a level of low frequency current traveling through the damping portion. | 2008-11-27 |
20080291707 | Universal AC high power inveter with galvanic isolation for linear and non-linear loads - A universal alternating current (AC) inverter system with galvanic isolation takes an unregulated direct current (DC) input and provides a high-quality AC output that may be used in conjunction with both linear and non-linear loads. The universal AC inverter system includes a DC-DC converter for converting an unregulated DC input to a regulated DC output, and a DC-AC inverter for converting the regulated DC output to a high-quality AC output. The DC-DC converter includes a DC link isolation high frequency transformer that provides galvanic isolation between the unregulated DC input and the AC output. To avoid saturation of the transformer, the controller for the DC-DC converter employs a DC offset correction loop that prevents accumulation of DC content on the primary side of the transformer. The universal AC inverter system includes a 4-phase inverter topology that converts the regulated DC voltage provided by the DC-DC converter to an AC output. An inverter controller employs a number of feedback loops that are used to control switches within the 4-phase inverter topology to provide a high-quality AC output voltage for both linear and non-linear loads, including a fast voltage control loop, a slow voltage control loop, a AC output capacitor current control loop, and a DC content control loop. | 2008-11-27 |
20080291708 | PROTECTIVE CIRCUIT AND METHOD FOR MULTI-LEVEL CONVERTER - A protective circuit for a multi-level converter including a DC link capacitor bank includes: an energy absorbing element; switches, wherein at least two of the switches each couple the energy absorbing element to the capacitor bank; and a controller configured to provide control signals to the switches to selectively actuate the switches to enable control of energy dissipation and to enable control of voltage balance on the capacitor bank of the multi-level converter. | 2008-11-27 |
20080291709 | Switching power supply apparatus - A switching power supply apparatus | 2008-11-27 |
20080291710 | Semiconductor module and inverter device - A semiconductor module includes a base plate; a plurality of substrates placed on one surface of the base plate, with each substrate of the plurality of substrates including a switching element, a diode element, and a connection terminal area; and a parallel flow forming device that forms parallel coolant flow paths that are provided so as to be in contact with the other. | 2008-11-27 |
20080291711 | Step-down switching regulator with freewheeling diode - A freewheeling DC/DC step-down converter includes a high-side MOSFET, an inductor and an output capacitor connected between the input voltage and ground. A freewheeling clamp, which includes a freewheeling MOSFET and diode, is connected across the inductor. When the high-side MOSFET is turned off, a current circulates through the inductor and freewheeling clamp rather than to ground, improving the efficiency of the converter. The converter has softer diode recovery and less voltage overshoot and noise than conventional Buck converters and features unique benefits during light-load conditions. | 2008-11-27 |
20080291712 | INTERLEAVED SOFT SWITCHING BRIDGE POWER CONVERTER - An interleaved soft switching bridge power converter comprises switching poles operated in an interleaved manner so as to substantially reduce turn-on switching losses and diode reverse-recovery losses in the switching pole elements. Switching poles are arranged into bridge circuits that are operated so as to provide a desired voltage, current and/or power waveform to a load. By reducing switching turn on and diode reverse recovery losses, soft switching power converters of the invention may operate efficiently at higher switching frequencies. Soft switching power converters of the invention are well suited to high power and high voltage applications such as plasma processing, active rectifiers, distributed generation, motor drive inverters and class D power amplifiers. | 2008-11-27 |
20080291713 | MODULAR FLASH MEMORY CARD EXPANSION SYSTEM - A memory card system is disclosed. The memory card system comprises at least one flash memory card and a module for holding the at least one memory card. The module comprises a plurality of supports. The supports include rails to guide the at least one memory card in place and a latch system for securing the at least one memory card to the module. The present invention provides a modular flash memory card expansion system using any standard Secure Digital card; the flash memory card can be any flash-based memory card, such as SD, Compact Flash (CF), MMC, Memory Stick or others. | 2008-11-27 |
20080291714 | SEMICONDUCTOR MEMORY DEVICE - Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line. | 2008-11-27 |
20080291715 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS - A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1. | 2008-11-27 |
20080291716 | METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line. | 2008-11-27 |
20080291717 | SEMICONDUCTOR STORAGE DEVICE INCORPORATED INTO A SYSTEM LSI WITH FINER DESIGN RULES - In the present invention, a row decoder circuit is made up of a transistor having a first gate oxide film thickness, a transistor having a second gate oxide film thickness, and a transistor having a third gate oxide film thickness. Thus even a control circuit at a lower voltage can drive word lines at high speeds while achieving reliability. | 2008-11-27 |
20080291718 | VARIABLE RESISTANCE MEMORY DEVICE WITH AN INTERFACIAL ADHESION HEATING LAYER, SYSTEMS USING THE SAME AND METHODS OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material. | 2008-11-27 |
20080291719 | Streaming mode programming in phase change memories - A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down. | 2008-11-27 |
20080291720 | SPIN TORQUE TRANSFER MRAM DEVICE - The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area. | 2008-11-27 |
20080291721 | METHOD AND SYSTEM FOR PROVIDING A SPIN TRANSFER DEVICE WITH IMPROVED SWITCHING CHARACTERISTICS - A method and system for providing a magnetic element is described. The magnetic element includes a first pinned layer, a first spacer layer, a free layer, a second spacer layer, and a second pinned layer. The first and second pinned layers have first and magnetizations oriented in first and second directions, respectively. The first and second spacer layers are nonferromagnetic. The first and second spacer layers are between the free layer and the first and second pinned layers, respectively. The magnetic element is configured either to allow the free layer to be switched to each of multiple states when both a unidirectional write current is passed through the magnetic element and the magnetic element is subjected to a magnetic field corresponding to the each states or to allow the free layer to be switched to each of the plurality of states utilizing a write current and an additional magnetic field that is applied from at least one of the first pinned layer and the second pinned layer substantially only if the write current is also applied. | 2008-11-27 |
20080291722 | Charge trapping memory and accessing method thereof - An accessing method for a charge trapping memory including memory cells and tracking cells for storing expected data. The method includes the following steps. In a specific time first, the expected data is written into the tracking cells and the memory cells are not being programmed, read or erased. Next, the data stored in the tracking cells is sensed as read data according to a present reference current. Then, the present reference current is adjusted to an adjusted reference current according to a difference between the read data and the expected data so that the data stored in tracking cells is sensed as corresponding with the expected data according to the adjusted reference current. Thereafter, the memory cells are read according to the adjusted reference current. | 2008-11-27 |
20080291723 | SOURCE BIASING OF NOR-TYPE FLASH ARRAY WITH DYNAMICALLY VARIABLE SOURCE RESISTANCE - A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e., close to zero) during read operations. The variable source resistance is set to a relatively high impedance value (i.e., close to being an open circuit) during flash erase operations. The variable source resistance is set to a first intermediate resistance value at least during soft-programming where the first intermediate resistance value is one that raises V | 2008-11-27 |
20080291724 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits. | 2008-11-27 |
20080291725 | Memory cell array and semiconductor memory - A memory cell array includes a plurality of memory cells disposed in matrix, a plurality of word lines extending to the column direction wherein the gates in the memory cells disposed in each column are commonly connected to one of the word lines, a plurality of sub bit lines extending to the row direction wherein the source in the memory cells disposed in a first row and the drain in the memory cells disposed in a second row, which is adjacent to the first row, are commonly connected to one of the sub bit lines, and a plurality of pairs each having a source selector and a drain selector wherein each pair is disposed at one of the locations, which sandwich the word lines, alternatively, and which are located at both ends of the sub bit lines, which are adjacent to each other. | 2008-11-27 |
20080291726 | BANDGAP ENGINEERED SPLIT GATE MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation. | 2008-11-27 |
20080291727 | Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory - Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied. | 2008-11-27 |
20080291728 | Single-Poly Non-Volatile Memory Cell - A non-volatile memory cell is provided that includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate. | 2008-11-27 |
20080291729 | Non-Volatile Memory With High Reliability - A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced. | 2008-11-27 |
20080291730 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial V | 2008-11-27 |
20080291731 | Methods For Optimizing Page Selection In Flash-Memory Devices - The present invention discloses methods for storing data in a flash-memory storage device, the method including the steps of: receiving, by the device, primary data to be stored in the device and to be read from the device at a primary reading speed; storing at least part of the primary data only in fast pages in the device, wherein the fast pages are located in multi-level cells of the device; designating, by the device, secondary data to be read from the device at a secondary reading speed, wherein the secondary reading speed is slower than the primary reading speed; and storing at least part of the secondary data only in slow pages in the device, wherein the slow pages are located in the multi-level cells. Preferably, the method further includes the step of: moving the secondary data from a previously-stored area in the device to the slow pages. | 2008-11-27 |
20080291732 | Three cycle SONOS programming - A method to eliminate over-erase in a nonvolatile trapped-charge memory array during write operations includes a three-cycle process of bulk programming the memory array, bulk erasing the memory array and selectively inhibiting one or more memory cells in the memory array while applying a programming voltage to the memory array. | 2008-11-27 |
20080291733 | LOADING DATA WITH ERROR DETECTION IN A POWER ON SEQUENCE OF FLASH MEMORY DEVICE - A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result. | 2008-11-27 |
20080291734 | NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE WORDLINE VOLTAGE OF THE SAME - A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided. | 2008-11-27 |
20080291735 | METHOD FOR USING TRANSITIONAL VOLTAGE DURING PROGRAMMING OF NON-VOLATILE STORAGE - To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb. | 2008-11-27 |
20080291736 | NON-VOLATILE STORAGE SYSTEM WITH TRANSITIONAL VOLTAGE DURING PROGRAMMING - To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb. | 2008-11-27 |
20080291737 | PROGRAM AND ERASE METHODS FOR NONVOLATILE MEMORY - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device. | 2008-11-27 |
20080291738 | METHODS AND CIRCUITS FOR GENERATING A HIGH VOLTAGE AND RELATED SEMICONDUCTOR MEMORY DEVICES - Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed. | 2008-11-27 |
20080291739 | METHODS OF PROGRAMMING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES USING DIFFERENT PROGRAM VERIFICATION OPERATIONS AND RELATED DEVICES - A method of programming a non-volatile memory device includes receiving data to be programmed into memory cells of the memory device, programming the memory cells with the data, and selectively performing one of a plurality of program verify operations based on a current program loop number to determine whether the memory cells have been successfully programmed. For example, one of a wired-OR pass/fail check operation and a Y-scan pass/fail check operation may be performed according to the current program loop number. Related methods and devices are also discussed. | 2008-11-27 |
20080291740 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array, a row decoder which selects a word line, and applies a voltage to the selected word line, and a voltage generator which generates a boosted voltage, and outputs the boosted voltage as the voltage, the voltage generator includes a comparator which compares a first voltage with a second voltage, and outputs a comparison result signal, a constant current circuit which generates a first control signal in accordance with the comparison result signal, a first delay circuit which generates a second control signal by delaying the comparison result signal, and a charge pump circuit which generates the boosted voltage in response to the first and second control signals. | 2008-11-27 |
20080291741 | BIT LINE DECODER ARCHITECTURE FOR NOR-TYPE MEMORY ARRAY - A bit line decoder for sensing states of memory cells of a memory array includes control devices and a control module. The control devices selectively communicate with bit lines. The control devices are arranged in a multi-level configuration having a plurality of levels, each level having a plurality of the control devices. The control module selects from the bit lines a first bit line and a second bit line associated with a memory cell located in the memory array when determining a state of the memory cell. The control module generates first control signals that deselect one or more of the control devices at each level. When one or more control devices at each level are deselected, a first group of the bit lines including the first bit line is charged to a first potential, and a second group of the bit lines including the second bit line is charged to a second potential. | 2008-11-27 |
20080291742 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is disclosed, which includes a plurality of NAND cells each comprising a plurality of series-connected memory cell transistors, and a drain-side select transistor and a source-side select transistor connected to a drain-side end and a source-side end of the series-connected memory cell transistors, respectively, a source line commonly connected to the source-side select transistors in the plurality of NAND cells, a first discharge circuit which is connected between the source line and a reference potential and whose conduction/non-conduction is controlled by a first control signal, and a second discharge circuit which is connected between the source line and the reference potential and whose conduction/non-conduction is controlled by a second control signal different from the first control signal. | 2008-11-27 |
20080291743 | SEMICONDUCTOR STORAGE DEVICE - This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node. | 2008-11-27 |
20080291744 | PORTABLE MEDICAL STORAGE DEVICE AND PROGRAM - A medical self-portable device and program on portable drive containing medical information that would be useful and pertinent for doctors and pharmacists to access and have the ability to update. This medical information is necessary for medical personnel to accurately and efficiently treat life-threatening emergency, non-life-threatening emergency, critical care, and/or routine care in doctors' offices or hospitals. | 2008-11-27 |
20080291745 | METHOD AND SYSTEM FOR SIMULTANEOUS READS OF MULTIPLE ARRAYS - A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set oft input selector signals. The method includes enabling each multiplexing circuit with a distinct combination of the set of input selector signals. The distinct combinations of the set of input selector signals cause each input selector signal to drive a comparable number of multiplexers. Each multiplexing circuit selects a memory location from the coupled indexed array. Further, the method includes reading the data at the selected memory locations through the output of each multiplexing circuit. | 2008-11-27 |
20080291746 | Semiconductor Storage Device and Burst Operation Method - The present invention is a PSRAM in which a burst length can be increased without increasing consumed current, and a burst operation method therefor. In operation, column selection lines CSL | 2008-11-27 |
20080291747 | Buffered Memory Device - A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers. | 2008-11-27 |
20080291748 | WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS - A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command. | 2008-11-27 |
20080291749 | METHOD AND APPARATUS FOR TIMING ADJUSTMENT - A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section. | 2008-11-27 |
20080291750 | Semiconductor device that uses a plurality of source voltages - A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line and a bit line, a word-line driving circuit configured to drive the word line, and a sense amplifier configured to sense information stored in the memory cell. The voltage adjusting portion includes: a voltage modifying circuit configured to step down or boost up the third voltage at a predetermined mode to generate a fourth voltage higher than the second voltage, and supply the fourth voltage to the sense amplifier or the word-line driving circuit. | 2008-11-27 |
20080291751 | SCR MATRIX STORAGE DEVICE - One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device. This is accomplished by actively changing the forward voltage of the diodes in the storage array such that a diode connected to the selected row line but that is not connected to the selected column line is in its high impedance state and a diode connected to the selected column line but that is not connected to the selected row line is in its high impedance state; only a diode that is connected to both the selected row line and the selected column line will switch to its low impedance state. The present invention is an enhancement to all types of arrays of diodes or arrays of other nonlinear conducting elements including: storage devices, programmable logic devices, display arrays, sensor arrays, and many others. | 2008-11-27 |
20080291752 | Semiconductor Device - A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line. The semiconductor device may include a data transfer unit which receives first data, and outputs second data obtained by driving the first data to a predetermined level to a data transfer line; a data receiver which receives the second data transferred via the data transfer line; a delay which outputs a plurality of delay signals respectively obtained by delaying the second data outputted from the data transfer unit by different delay periods; a delay controller which selects one of the delay signals in accordance with an operation mode of the semiconductor device, and outputs at least one adjustment signal for adjusting a driving period of the data transfer unit for the first data based on the delay period of the selected delay signal; and a transfer controller which receives the first data and the at least one adjustment signal, and outputs at least one transfer control signal for controlling the operation of the data transfer unit, based on the received first data and adjustment signal. | 2008-11-27 |
20080291753 | Semiconductor memory device and latency signal generating method thereof - A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal. | 2008-11-27 |
20080291754 | Semiconductor memory device with low standby current - In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small. | 2008-11-27 |
20080291755 | OUTPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE AND DATA OUTPUT METHOD - An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to a voltage level of a second power supply higher than a voltage level of the first power supply. In an active state, a voltage level of the gate terminal of the outputting PMOS transistor is changed to a voltage level of the first power supply in response to an active command or a read command, or in response to the state of a semiconductor memory device changing to the active state or a read state, and either the outputting PMOS transistor or the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell. | 2008-11-27 |
20080291756 | Semiconductor memory device of controlling bit line sense amplifier - A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation. | 2008-11-27 |
20080291757 | SIGNAL MASKING METHOD, SIGNAL MASKING CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A signal masking circuit includes a detection circuit, a delayed read data strobe signal generation circuit, a gating circuit, a counting circuit, and a masking circuit. The detection circuit detects a period of a logic “L” of a read data strobe signal. The gating circuit gates a delayed read data strobe signal, and generates a first masked read data strobe signal. The counting circuit counts the falls of the first masked read data strobe signal until the count reaches a predetermined number, and generates a masking signal for masking the first masked read data strobe signal. The masking circuit masks the first masked read data strobe signal, and outputs a second masked read data strobe signal. | 2008-11-27 |
20080291758 | READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA - Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting. | 2008-11-27 |
20080291759 | APPARATUS AND METHOD OF GENERATING OUTPUT ENABLE SIGNAL FOR SEMICONDUCTOR MEMORY APPARATUS - A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop) clock so as to generate an even-numbered divided clock and an odd-numbered divided clock. An even-numbered output enable signal generator generates an even-numbered output enable signal on the basis of an external read command, the timing signal, a CL (CAS Latency), and the even-numbered divided clock. An odd-numbered output enable signal generator generates an odd-numbered output enable signal on the basis of the external read command, a timing signal in which the timing signal is inverted, the CL, and the odd-numbered divided clock. A logical unit logically operates the even-numbered output enable signal and the odd-numbered output enable signal and outputs an output enable signal. | 2008-11-27 |
20080291760 | Sub-array architecture memory devices and related systems and methods - Memory devices, systems and methods implementing an architecture for partitioning a memory area of normally used memory cells and redundant memory cells are disclosed. A memory area is partitioned into a plurality of substantially equally sized sub-arrays of normally used memory cells and redundant memory cells. The groups of memory cells in a first portion of the sub-arrays are each selectable by a first quantity of select signals and a second portion of the sub-arrays are each selectable by a second quantity of select signals. One of the plurality of sub-arrays partially includes all of the groups of the redundant memory cells selectable by respective redundant select signals. | 2008-11-27 |
20080291761 | Burn-in test apparatus - A burn-in test apparatus and a semiconductor device using the same are disclosed. The burn-in test apparatus includes a flag signal generating unit configured to receive an external input signal and an external address externally inputted for a burn-in test and generate a flag signal, and a burn-in test unit configured to receive the flag signal, generate a toggled output enable signal, and drive an input/output line to toggle a signal on the input/output line. | 2008-11-27 |
20080291762 | SEMICONDUCTOR MEMORY DEVICE FOR PRECHARGING BIT LINES EXCEPT FOR SPECIFIC READING AND WRITING PERIODS - A semiconductor memory device includes a memory cell having an FET of a floating body type, and a capacitor for storing a data charge; a bit line to which the source or the drain of the FET is connected; a precharging device for performing precharge control so that the bit line has a predetermined precharge voltage; a sense amplifier for amplifying and storing the potential of the bit line, which is set in accordance with the data charge read from the memory cell; a switching device, provided between the bit line and the sense amplifier, for performing selective connection therebetween; and a control part for controlling the precharging device, the sense amplifier, and the switching device. Except for each period for performing data reading or writing, the control part makes the precharging device perform the precharge control and makes the switching device disconnect the bit line from the sense amplifier. | 2008-11-27 |
20080291763 | MEMORY DEVICE - A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status. | 2008-11-27 |
20080291764 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: word lines; global bit lines intersecting therewith; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each of which includes memory cells each having a vertical transistor structure connected to the local bit lines at a lower portion and each being formed at an intersection of the word line and the local bit line, and is arranged corresponding to each section of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line. | 2008-11-27 |
20080291765 | Methods, circuits, and systems to select memory regions - Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location. | 2008-11-27 |
20080291766 | Memory architecture having local column select lines - A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections of memory. Each section of memory having a plurality of memory cells arranged in rows and columns of memory and a plurality of sense amplifiers located in each of the plurality of regions. The sense amplifiers coupled to a respective column of memory. A plurality of column select lines are located in each of the plurality of regions with each column select line coupled to a group of column select switches associated with a section of memory to activate the respective column select switches. | 2008-11-27 |
20080291767 | MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL - A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer. | 2008-11-27 |
20080291768 | BITCELL WITH VARIABLE-CONDUCTANCE TRANSFER GATE AND METHOD THEREOF - A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first transfer gate is configurable to at least four conductance states based on a state of the first word line and a state of the second word line. The memory device further comprises control logic to configure, for an access to the bit cell, the state of the first word line and the state of the second word line based on an access type of the access. | 2008-11-27 |
20080291769 | Multiport semiconductor memory device - In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD-Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented. | 2008-11-27 |
20080291770 | PLL CIRCUIT FOR INCREASING POTENTIAL DIFFERENCE BETWEEN GROUND VOLTAGE AND REFERENCE VOLTAGE OR POWER SOURCE VOLTAGE OF OSCILLATION CIRCUIT - A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal, a power source voltage, and a predetermined reference voltage; and a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage. A transistor in the oscillation circuit can operate in a saturation area, thereby operating the PLL circuit at a high speed with a low power source voltage, without being easily affected by a variation in the temperature or other process conditions. | 2008-11-27 |
20080291771 | Mixing Drum - A rotary concrete mixing drum ( | 2008-11-27 |
20080291772 | Building material mixer - The present invention relates to a building material mixer having a mixer drum which can be rotationally driven by a mixer drive, with the mixer drum being rotatably supported by the mixer drive at a mixer frame part, in particular a traveling gear frame part, at one of its end face ends and with the mixer drive having a drive part, in particular a hydraulic motor, and a drive transmission connected to the mixer drum. In accordance with the invention, the building material mixer is characterized in that the mixer drive is movably supported by movable bearing means at the mixer frame part allowing tilting movements; and in that the mixer drum is fastened to the transmission housing of the drive transmission. | 2008-11-27 |
20080291773 | Soil Cement Manufacturing Machine Quipped with Impeller Having Scratching Blade - The present invention provides a soil cement manufacturing machine which prevents blades of an impeller from becoming worn and prevents soil cement from becoming stuck to and remaining in a mixing tub. The soil cement manufacturing machine includes an input part ( | 2008-11-27 |