47th week of 2015 patent applcation highlights part 56 |
Patent application number | Title | Published |
20150332940 | METHOD AND APPARATUS FOR CLEANING SEMICONDUCTOR WAFER - A method and apparatus ( | 2015-11-19 |
20150332941 | METHODS AND APPARATUS FOR PROCESSING SUBSTRATES USING AN ION SHIELD - Methods and apparatus for processing a substrate are provided. In some embodiments, a method of processing a substrate having a first layer may include disposing a substrate atop a substrate support in a lower processing volume of a process chamber beneath an ion shield having a bias power applied thereto, the ion shield comprising a substantially flat member supported parallel to the substrate support, and a plurality of apertures formed through the flat member, wherein the ratio of the aperture diameter to the thickness flat member ranges from about 10:1-1:10; flowing a process gas into an upper processing volume above the ion shield; forming a plasma from the process gas within the upper processing volume; treating the first layer with neutral radicals that pass through the ion shield; and heating the substrate to a temperature of up to about 550 degrees Celsius while treating the first layer. | 2015-11-19 |
20150332942 | PEDESTAL FLUID-BASED THERMAL CONTROL - Thermal control of substrate carrier is described using a thermal fluid. In one example, a thermally controlled substrate support includes a top surface to support a substrate, the top surface being thermally coupled to substrate, a thermal fluid channel thermally coupled to the top surface to carry a thermal fluid, the thermal fluid to draw heat from and provide heat to the top surface, and a heat exchanger to supply thermal fluid to the thermal fluid channel, the heat exchanger alternately heating and cooling the thermal fluid to adjust the substrate temperature. | 2015-11-19 |
20150332943 | POLISHING APPARATUS - A polishing apparatus for polishing a substrate is provided. The polishing apparatus includes: a polishing table holding a polishing pad; a top ring configured to press the substrate against the polishing pad; first and second optical heads each configured to apply the light to the substrate and to receive reflected light from the substrate; spectroscopes each configured to measure at each wavelength an intensity of the reflected light received; and a processor configured to produce a spectrum indicating a relationship between intensity and wavelength of the reflected light. The first optical head is arranged so as to face a center of the substrate, and the second optical head is arranged so as to face a peripheral portion of the substrate. | 2015-11-19 |
20150332944 | CARRIER SUBSTRATE AND METHOD FOR FIXING A SUBSTRATE STRUCTURE - A carrier substrate for supporting a substrate structure having a process substrate and a frame structure has a base portion and a support portion. The support portion is arranged on the base portion. The support portion and the base portion form a recess region for receiving the frame structure of the substrate structure. The support portion has a support surface area for supporting the process substrate of the substrate structure. | 2015-11-19 |
20150332945 | SUBSTRATE TRANSFER SYSTEM, SUBSTRATE PROCESSING SYSTEM, AND SUBSTRATE TRANSFER ROBOT - A substrate transfer system includes a substrate transfer robot disposed in a robot installment area defined between a first apparatus and a second apparatus. The first apparatus includes cassettes. The cassettes are each configured to accommodate at least one substrate. The second apparatus includes a second wall opposite to a first wall. The substrate transfer robot transfers the at least one substrate from each of the cassettes to the second apparatus. The substrate transfer robot includes a base stationary, a hand, and arms. A first arm includes a first end and a second end. The first end is rotatably coupled to the base. A second arm includes a third end and a fourth end. The third end is rotatably coupled to the second end. The second end of the first arm moves beyond the second wall when the substrate transfer robot takes out the substrate from the first apparatus. | 2015-11-19 |
20150332946 | SUBSTRATE TRANSFER SYSTEM, SUBSTRATE PROCESSING SYSTEM, AND SUBSTRATE TRANSFER ROBOT - A substrate transfer robot is disposed in a robot installment area defined between a first apparatus and a second apparatus including an opening. The first apparatus includes a first wall, the second apparatus including a second wall. The first apparatus accommodates the substrate at each of a lowest height position and a highest height position. The substrate transfer robot includes a base stationary, a hand configured, and an arm. The arm is rotatably mounted to the base to move the hand. The hand and the arm move in a height direction between a movable range defined between a lowest position and a highest position. The arm rotates with partially entering the opening when the substrate transfer robot takes out the substrate from the first apparatus. The substrate is accommodated at each of the lowest height position and the highest height position. | 2015-11-19 |
20150332947 | SUBSTRATE TRANSFER SYSTEM, SUBSTRATE PROCESSING SYSTEM, AND SUBSTRATE TRANSFER ROBOT - A substrate transfer system includes a substrate transfer robot disposed in a robot installment area defined between a first apparatus and a second apparatus. The first apparatus includes a first cassette, a second cassette and a first wall. The second apparatus includes a second wall. The substrate transfer robot transfers a substrate from each of the first cassette and the second cassette to the second apparatus. The substrate transfer robot includes a hand and an arm. The arm includes a first arm rotatable about a center of rotation. The first cassette is closer to the center of rotation than the second cassette. The arm moves with being partially disposed beyond the second wall in plan view and the arm moves without being disposed beyond the second wall in plan view when taking out the substrate from the first cassette. | 2015-11-19 |
20150332948 | TRANSPORT SYSTEM AND TRANSPORT METHOD - In a transport system, overhead travelling vehicles each including a hoist travel along an overhead travelling vehicle travelling route. A local vehicle travelling route is disposed under the overhead travelling vehicle travelling route and over load ports at a position higher than the load ports. Local vehicles each including hoist travel along the local vehicle travelling route. Buffers are disposed along the local vehicle travelling route. The local vehicle travelling route includes a plurality of local vehicle travelling routes that are provided in parallel, and the local vehicles are configured to diverge and merge from one local vehicle travelling route to another local vehicle travelling route. The local vehicles transport articles between a load port and a buffer under control of a controller. The overhead travelling vehicles, under control of the controller, transfer articles to and from a load port or a buffer and transport articles between a load port or a buffer and a section other than the local vehicle travelling routes. | 2015-11-19 |
20150332949 | Method For Reducing Particle Generation At Bevel Portion Of Substrate - A method for transporting a substrate using an end effector which mechanically clamps a periphery of the substrate includes: before transporting the substrate, depositing a compressive film only on, at, or in a bevel portion of the substrate; and transporting the substrate whose bevel portion is covered by the compressive film as the outermost film, using an end effector while mechanically clamping the periphery of the substrate. | 2015-11-19 |
20150332950 | ON-END EFFECTOR MAGNETIC WAFER CARRIER ALIGNMENT - Embodiments include methods and apparatuses for transferring and aligning a carrier ring. In an embodiment, a method includes lifting the carrier ring from a first location with a robot arm that includes an end effector wrist and an end effector. Front dowel pins and rear dowel pins are coupled to the end effector. In an embodiment, the end effector wrist includes a plunger that has a gripping device. Embodiments include securing the plunger to the carrier ring with the gripping device and extending the plunger out from the end effector wrist until the carrier ring contacts the front dowel pins. Thereafter, the carrier ring is transferred from the first location to the second location. The plunger and the carrier ring are then retracted until the rear dowel pins engage an alignment notch and an alignment flat on the carrier ring. | 2015-11-19 |
20150332951 | Wafer Releasing - Embodiments of the present invention provide a chuck system for handling a wafer that comprises a first and a second main surface. The chuck system includes a chuck configured to hold the wafer at the second main surface facing the chuck and a release device. The chuck system further includes an actuator configured to lift the release device away from the chuck. The release device is configured such that the release device mechanically engages with the wafer at an edge portion of the second main surface of the wafer when being lifted, thereby releasing the wafer from the chuck. | 2015-11-19 |
20150332952 | SUPPORT PLATE AND METHOD FOR FORMING SUPPORT PLATE - A support plate to which a front surface of a wafer having a device region in which plural devices are formed and a peripheral surplus region surrounding the device region on the front surface is stuck. The support plate includes a base plate in which a recess is formed in a front surface region corresponding to the device region of the wafer to be stuck to the support plate and an annular groove is formed in a region corresponding to the peripheral surplus region of the wafer, and a soft member packed in the recess of the base plate. The wafer is stuck to a front surface of the support plate with the intermediary of an adhesive by injecting the adhesive into the annular groove. | 2015-11-19 |
20150332953 | BARRIER LAYER STACK FOR BIT LINE AIR GAP FORMATION - Air gaps are formed between conductive metal lines that have an inner barrier layer and an outer barrier layer. An etch step to remove sacrificial material is performed under a first set of process conditions producing a byproduct that suppresses further etching. A byproduct removal step performed under a second set of process conditions removes the byproduct. | 2015-11-19 |
20150332954 | SEMICONDUCTOR DEVICE HAVING AIR GAP STRUCTURES AND METHOD OF FABRICATING THEREOF - One method includes forming a conductive feature in a dielectric layer on a substrate for a semiconductor device. A hard mask layer and an underlying etch stop layer are formed on the substrate. The hard mask layer and the underlying etch stop layer are then patterned. The patterned etch stop layer is disposed over the conductive feature. At least one of the patterned hard mask layer and the patterned etch stop layer are used as a masking element during etching of a trench in the dielectric layer adjacent the conductive feature. A cap is then formed over the etched trench. The cap is disposed on the patterned etch stop layer disposed on the conductive feature. | 2015-11-19 |
20150332955 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns. | 2015-11-19 |
20150332956 | MECHANICAL STRESS-DECOUPLING IN SEMICONDUCTOR DEVICE - According to a method in semiconductor device fabrication, a first trench and a second trench are concurrently etched in a semi-finished semiconductor device. The first trench is a mechanical decoupling trench between a first region of an eventual semiconductor device and a second region thereof. The method further includes concurrently passivating or insulating sidewalls of the first trench and of the second trench. A related semiconductor device includes a first trench configured to provide a mechanical decoupling between a first region and a second region of the semiconductor device. The semiconductor device further includes a second trench and a sidewall coating at sidewalls of the first trench and the second trench. The sidewall coating at the sidewalls of the first trench and at the sidewalls of the second trench are of the same material. | 2015-11-19 |
20150332957 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH REDUCED LEAK PATHS - A method of fabricating a semiconductor device with reduced leak paths is disclosed. The method comprises etching a void in non-conductive material in the semiconductor device to provide a conduction path between isolated material, forming a non-conductive surface layer on an unintended conductive item adjacent to the void, and filling the void with a conductive material. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void using plasma oxidation operations. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void using plasma oxidation operations. The unintended conductive item may comprise a conductive impurity or conductive residue. The void may comprise a trench or a hole for a via. | 2015-11-19 |
20150332958 | Sublithographic Kelvin Structure Patterned With DSA - In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate. | 2015-11-19 |
20150332959 | METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION - Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions. | 2015-11-19 |
20150332960 | CONDUCTIVE LINES IN CIRCUITS - In a method, conductive lines used in a circuit are formed. Signal traces of a plurality of signal traces are grouped to a first group of first signal traces or a second group of second signal traces. A first mask is used to form a first conductive line for a first signal trace of the first group. A second mask is used to form a second conductive line for a second signal trace of the second group. The first traces each have a first width. The second traces each have a second width different from the first width. The grouping is based on at least one of following conditions: a current flowing through a signal trace of the signal traces of the plurality of signal traces, a length of the signal trace, a resistivity of the signal trace, or a resistivity-capacitive constant of the signal trace. | 2015-11-19 |
20150332961 | Cu Wiring Fabrication Method and Storage Medium - Cu wiring fabrication method for fabricating Cu wiring with respect to substrate having interlayer dielectric film having trench formed thereon, includes: forming barrier film on surface of the trench; forming Ru film on surface of the barrier film by CVD; burying the trench by forming Cu film or Cu alloy film on the Ru film; forming Cu film or Cu alloy film at corners of bottom of the trench while re-sputtering the formed Cu film or Cu alloy film in a condition where first formed Cu film or Cu alloy film re-sputtered by an ion action of the plasma generation gas; and subsequently burying the Cu film or the Cu alloy film in the trench in condition where the Cu film or the Cu alloy film is formed on field portion of the substrate, and reflows in the trench by an ion action of the plasma generation gas. | 2015-11-19 |
20150332962 | Structure and Method for Semiconductor Device - Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view. | 2015-11-19 |
20150332963 | T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE - A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling. | 2015-11-19 |
20150332964 | SELF-LIMITING SILICIDE IN HIGHLY SCALED FIN TECHNOLOGY - A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on a fin structure of a single crystal semiconductor material, and forming a metal including layer on the semiconductor material layer. Metal elements from the metal including layer may then be intermixed metal elements with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure. A core of the fin structure of the single crystal semiconductor material is substantially free of the metal elements from the metal including layer. | 2015-11-19 |
20150332965 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacture method for display device includes the steps of: (a) forming a metal film on a substrate; (b) forming a metal layer by patterning the metal film; and (c) following the step (b) and forming, on the metal layer, a low reflection layer of a resin. The step (b) includes the steps of: (b1) forming an etching protection film; (b2) patterning the etching protection film; and (b3) following the step (b2) and etching the metal film. | 2015-11-19 |
20150332966 | WAFER FRONTSIDE-BACKSIDE THROUGH SILICON VIA - A wafer frontside-backside through silicon via and methods of manufacture are disclosed. The method includes forming a plurality of frontside metalized vias into a partial depth of a substrate. The method further includes forming a backside via in the substrate which exposes, from the backside, the plurality of frontside metalized vias. The method further includes forming a metal in the via in contact with the plurality of metalized frontside vias. | 2015-11-19 |
20150332967 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. | 2015-11-19 |
20150332968 | Semiconductor Having A High Aspect Ratio Via - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer. | 2015-11-19 |
20150332969 | SEMICONDUCTOR DIE SINGULATION METHOD AND APPARATUS - In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. | 2015-11-19 |
20150332970 | CARRIER WITH THERMALLY RESISTANT FILM FRAME FOR SUPPORTING WAFER DURING SINGULATION - Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The frame is composed of a thermally resistant material. The carrier also includes a carrier tape coupled to the frame and disposed at least within the inner opening of the frame. The carrier tape includes a base film. | 2015-11-19 |
20150332971 | Integrate Circuit with Nanowires - A method includes providing a substrate having a metal-oxide-semiconductor (MOS) region. The MOS region includes first gate, source, and drain regions for a first device, and second gate, source, and drain regions for a second device. The first gate region has a first length. The second gate region has a second length different from the first length. The method further includes forming first and second fins in the first and second gate regions, forming first and second semiconductor layer stacks over the first and second fins, and performing a thermal oxidation process to the first and second semiconductor layer stacks, thereby forming first and second nanowire sets in the first and second gate regions respectively. The first and second nanowire sets are wrapped by respective semiconductor oxide layers. The first nanowire set has a first diameter. The second nanowire set has a second diameter different from the first diameter. | 2015-11-19 |
20150332972 | FABRICATING RAISED FINS USING ANCILLARY FIN STRUCTURES - A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure. | 2015-11-19 |
20150332973 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME - The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention. | 2015-11-19 |
20150332974 | LAYOUT METHOD TO MINIMIZE CONTEXT EFFECTS AND DIE AREA - An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor. | 2015-11-19 |
20150332975 | METHOD FOR FABRICATING METAL GATE ELECTRODE - Exemplary methods for fabricating a metal gate electrode include forming a dielectric layer on a substrate, and forming a first trench having a first width and a second trench having a second width in the dielectric layer where the first width is less than the second width. Also included is depositing a work-function metal layer over the dielectric layer and into the first and second trenches where the deposited work-function layer is in direct contact with the top surface of the dielectric layer. A first signal metal layer is deposited over the work-function metal layer filling the second trench and a second signal metal layer is deposited filling the first trench. | 2015-11-19 |
20150332976 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench. | 2015-11-19 |
20150332977 | ELECTRICALLY ISOLATED SiGe FIN FORMATION BY LOCAL OXIDATION - A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein. | 2015-11-19 |
20150332978 | WARP CORRECTION DEVICE AND WARP CORRECTION METHOD FOR SEMICONDUCTOR ELEMENT SUBSTRATE - A warp correction apparatus includes an injection mechanism including a nozzle that performs injection treatment, an adsorption table that holds the semiconductor element substrate by adsorption at a principal surface side or a film surface side, a moving mechanism that moves the adsorption table so that the semiconductor element substrate relatively moves with respect to an injection area of an injection particle by the nozzle, an injection treatment chamber that houses the semiconductor element substrate held on the adsorption table and in the interior of which injection treatment is performed, a measurement mechanism that measures a warp of the semiconductor element substrate, and a control device that, based on a difference between a target warp amount and a warp amount measured by the measurement mechanism, performs at least either one of a setting processing of an injection treatment condition of the injection mechanism and an accept/reject determination of the semiconductor element substrate for which injection treatment has been performed. | 2015-11-19 |
20150332979 | MANUFACTURING METHOD OF ARRAY SUBSTRATE - An embodiment of the present invention provides a manufacturing method of an array substrate comprising forming a gate detecting pattern on the array substrate with gate lines and common electrode lines formed thereon, the gate detecting pattern being arranged on one side of a pixel region of the array substrate and used to connect all the common electrode lines for pixel units; and performing a short circuit or a open circuit detection, wherein if the difference between a signal received by a receiving terminal for a gate line and a signal transmitted from a transmitting terminal for the gate line is larger than a predetermined detection threshold value, it is determined that short circuit between the gate line and a common electrode line or open circuit in the gate line occurs. | 2015-11-19 |
20150332980 | PROGRAMMABLE STITCH CHAINING OF DIE-LEVEL INTERCONNECTS FOR RELIABILITY TESTING - A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state. | 2015-11-19 |
20150332981 | METHOD FOR WAFER ETCHING IN DEEP SILICON TRENCH ETCHING PROCESS - A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S | 2015-11-19 |
20150332982 | METAL BASE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING METAL BASE SUBSTRATE - A metal base substrate of the present invention includes a copper plate made of copper, a metal layer that is formed on the copper plate and is made of a metal different from the copper, an insulating resin sheet that is formed by bonding a sheet made of an insulating resin onto the metal layer, and a circuit pattern formed on the insulating resin sheet. | 2015-11-19 |
20150332983 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a wiring circuit substrate or a semiconductor device in which connection portions of a plurality of semiconductor chips are electrically connected to each other, the method comprising a step of sealing at least part of the connection portions with an adhesive for a semiconductor comprising a compound having a group represented by the following formula (1): | 2015-11-19 |
20150332984 | UNDERFILL COMPOSITION AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a solid preapplication underfill material that has excellent workability, has a high degree of freedom for solder bonding processes, and enables the formation of a solder bond with high reliability. (Resolution Means) The underfill composition of the present disclosure contains a hardened epoxy resin and has a viscosity of 1000 Pa·s or more at 30° C. The hardening epoxy resin includes a crystalline epoxy resin at not less than 50 wt % relative to an entire resin composition. | 2015-11-19 |
20150332985 | PROTECTIVE PACKAGING FOR INTEGRATED CIRCUIT DEVICE - A method for packaging an integrated circuit (IC) device in which conventional manufacturing steps of mechanically bonding a die to a corresponding interconnecting substrate, wire bonding the die, and encapsulating the die in a protective shell are replaced by a single manufacturing step that includes thermally treating an appropriate assembly of parts to both form proper electrical connections for the die in the resulting IC package and cause the molding compound(s) to encapsulate the die in a protective enclosure. | 2015-11-19 |
20150332986 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIP COVERED WITH SEALING RESIN - A semiconductor device includes a wiring substrate, a sealing resin layer formed on the wiring substrate out of a filler-containing resin and having a one-sided filler content ratio, and at least one semiconductor chip mounted on the wiring substrate such that the semiconductor chip is located offset to be closer to an area where the filler content ratio is relatively low in the sealing resin layer and is sealed in its offset location in the sealing resin layer. | 2015-11-19 |
20150332987 | Microelectronic Assembly including Built-In Thermoelectric Cooler and Method of Fabricating Same - A method for fabricating a microelectronic assembly including a built-in TEC, a microelectronic assembly including a built-in TEC, and a system including the microelectronic assembly. The method includes providing a microelectronic device, and fabricating the TEC directly onto the microelectronic device such that there is no mounting material between the TEC and the microelectronic device. | 2015-11-19 |
20150332988 | Semiconductor Package with Multiple Dies - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 2015-11-19 |
20150332989 | GANG CLIPS HAVING DISTRIBUTED-FUNCTION TIE BARS - Gang clips ( | 2015-11-19 |
20150332990 | PACKAGE - A package includes: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package; a die pad region surrounded with the lead frames in a plane view; a semiconductor chip mounted on the die pad region; a plurality of bonding pads disposed on the semiconductor chip; and a plurality of bonding wires configured to connect the lead frames and the bonding pads, respectively, wherein the bonding wires are respectively connected to front end portions of the lead frames by bonding with an angle ranging from 45 to 135 degrees with respect to a trace of front end portions of the lead frames in the plane view. | 2015-11-19 |
20150332991 | METHOD OF FORMING A THIN SUBSTRATE CHIP SCALE PACKAGE DEVICE AND STRUCTURE - In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure. | 2015-11-19 |
20150332992 | Semiconductor Package - A semiconductor package with a leadframe to mount a transistor device prevents malfunction. The semiconductor package includes a leadframe including at least one or more transistor die attach pads where a first transistor device and a second transistor device are arranged, a driver die attach pad where a driver semiconductor chip is arranged, a first driver lead electrically connected to the driver semiconductor chip, and a second driver lead arranged between the first driver lead and the at least one or more transistor die attach pads, a chip bonding wire electrically connecting the first transistor device with the driver semiconductor chip, a first transistor bonding wire electrically connecting the first driver lead with the second transistor device, and a first insulator arranged on the second driver lead to insulate the second driver lead and the first transistor bonding wire from each other. | 2015-11-19 |
20150332993 | PRINTED CIRCUIT BOARD HAVING TRACES AND BALL GRID ARRAY PACKAGE INCLUDING THE SAME - A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group. | 2015-11-19 |
20150332994 | 3D INTEGRATED CIRCUIT PACKAGE WITH WINDOW INTERPOSER - 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die. | 2015-11-19 |
20150332995 | ELECTRONIC DEVICE INCLUDING COMPONENTS IN COMPONENT RECEIVING CAVITY AND RELATED METHODS - An electronic device may include a surface mount integrated circuit (IC) package to be attached to a printed circuit board (PCB). The surface mount IC package may include at least one IC and an encapsulating material surrounding the at least one IC and having a component receiving cavity defined therein on a bottom surface thereof to be positioned adjacent the PCB. The surface mount IC package may also include electrical leads coupled to the at least one IC and extending outwardly from the encapsulating material to be coupled to the PCB. The electronic device may also include at least one electronic component carried within the component receiving cavity and that includes electrical contacts to be coupled to the PCB. | 2015-11-19 |
20150332996 | INTERPOSER AND METHOD OF FABRICATING THE SAME - The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically. | 2015-11-19 |
20150332997 | WIRELESS MODULE AND PRODUCTION METHOD FOR WIRELESS MODULE - Provided is a wireless module whose size can be made smaller. The wireless module includes: a first substrate on which an antenna is mounted; a second substrate which opposes the first substrate and on which an electronic component is mounted; and a plurality of electric conductors which connect the first substrate and the second substrate and which transmit a signal between the antenna and the electronic components, wherein the plurality of electric conductors are disposed between the first substrate and the second substrate in series in a substantially vertical direction with respect to mounting surfaces of the first substrate and the second substrate. | 2015-11-19 |
20150332998 | PACKAGING SUBSTRATE AND PACKAGE STRUCTURE - A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided. | 2015-11-19 |
20150332999 | SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides an interconnect structure, including a low k dielectric layer with an air gap region and a non-air gap region. A first conductive line is positioned in the air gap region, and a second conductive line is positioned in the non-air gap region of the low k dielectric layer. A height of the first conductive line is different from a height of the second conductive line. The present disclosure also provides a method for manufacturing a semiconductor interconnect structure, including forming a photoresist layer over a hard mask layer with openings exposing a low k dielectric layer; treating the low k dielectric layer to be more hydrophilic through the openings of the hard mask layer; and removing the treated low k dielectric region to form an air gap in the air gap region. | 2015-11-19 |
20150333000 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED USING THE SAME - A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to the embodiment, substrate with a dielectric layer formed thereon is provided. Plural trenches are defined in the dielectric layer, and the trenches are isolated by the dielectric layer. A first barrier layer is formed in the trenches as barrier liners of the trenches, followed by filling the trenches with a conductor. Then, the conductor in the trenches is partially removed to form a plurality of recesses, wherein remained conductor has a flat surface. Next, a second barrier layer is formed in the recesses as barrier caps of the trenches. | 2015-11-19 |
20150333001 | MULTIPLE DATA LINE MEMORY AND METHODS - Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described. | 2015-11-19 |
20150333002 | Conductive Line Patterning - A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive. | 2015-11-19 |
20150333003 | Voids in Interconnect Structures and Methods for Forming the Same - A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device. | 2015-11-19 |
20150333004 | SUBSTRATE AND METHOD OF FORMING THE SAME - Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask. | 2015-11-19 |
20150333005 | PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC - Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan. | 2015-11-19 |
20150333006 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device comprises releasing an oxidation source included in an interlayer dielectric film having an opening portion formed on a surface thereof and being present on the surface of the interlayer dielectric film at a first substrate temperature, forming a first layer containing Ti and N to contact with at least a part of the interlayer dielectric film at a second substrate temperature lower than the first substrate temperature, wherein a Ti content in the first layer is more than 50 at % in all components, provided that oxygen and precious metals are excluded from the all components, and forming a Cu metal layer above the first layer. | 2015-11-19 |
20150333007 | METAL PAD OFFSET FOR MULTI-LAYER METAL LAYOUT - A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold. | 2015-11-19 |
20150333008 | STANDARD CELL ARCHITECTURE WITH M1 LAYER UNIDIRECTIONAL ROUTING - A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. | 2015-11-19 |
20150333009 | ENHANCING BARRIER IN AIR GAP TECHNOLOGY - A method of forming a semiconductor structure including a barrier layer between a metal line and an air gap oxide layer. The barrier layer may be formed in-situ or by a thermal annealing process and may prevent diffusion or electrical conduction. | 2015-11-19 |
20150333010 | BOND PAD HAVING RUTHENIUM DIRECTLY ON PASSIVATION SIDEWALL - A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads. | 2015-11-19 |
20150333011 | SEMICONDUCTOR DEVICE HAVING AIR GAP STRUCTURES AND METHOD OF FABRICATING THEREOF - One method includes forming a conductive feature in a dielectric layer on a substrate. A first hard mask layer and an underlying second hard mask layer are formed on the substrate. The second hard mask layer has a higher etch selectivity to a plasma etch process than the first hard mask layer. The second hard mask layer may protect the dielectric layer during the formation of a masking element. The method continues to include performing plasma etch process to form a trench in the dielectric layer, which may also remove the first hard mask layer. A cap is then formed over the trench to form an air gap structure adjacent the conductive feature. | 2015-11-19 |
20150333012 | METHOD OF FORMING A COPPER LAYER USING PHYSICAL VAPOR DEPOSITION - A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1. | 2015-11-19 |
20150333013 | SEMICONDUCTOR DEVICES INCLUDING METAL-SILICON-NITRIDE PATTERNS - A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern. | 2015-11-19 |
20150333014 | SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT - Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device. | 2015-11-19 |
20150333015 | DESIGNING AND MANUFACTURING METHODS OF TFT LCD ARRAY POSITIONING MARK - The present invention relates to TFT LCD array positioning mark designing and manufacturing methods. The TFT LCD array positioning mark manufacturing method includes: (1) forming a passivation layer of TFT LCD array; (2) providing a mask corresponding to the passivation layer, the mask comprising a passivation layer positioning mark that corresponds to a metal positioning mark of the TFT LCD array; and (3) using the mask to form a corresponding passivation layer positioning mark on the passivation layer. The TFT LCD array positioning mark designing method includes: forming a passivation layer positioning mark on a passivation layer of an TFT LCD array to correspond to a metal positioning mark of the TFT LCD array. The present invention provides TFT LCD array positioning mark designing and manufacturing method, wherein a passivation layer positioning mark that is designed and manufactured with them shows a pattern that is more stable and is not susceptible to deformation so as to eliminate the problem of positioning failure of the metal positioning mark occurring in the cell and module processes. | 2015-11-19 |
20150333016 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 2015-11-19 |
20150333017 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - This invention provides a semiconductor package, including a substrate, a plurality of semiconductor elements disposed on the substrate, at least one shielding member disposed between at least two of the semiconductor elements, and an encapsulant encapsulating the semiconductor elements and shielding members. Through the shielding member, electromagnetic interference caused among semiconductor elements can be prevented. | 2015-11-19 |
20150333018 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package may include a package substrate, an MRAM chip, a first magnetic shielding film and a second magnetic shielding film. The MRAM chip may be arranged over the package substrate. The MRAM chip may be electrically connected with the package substrate. The first magnetic shielding film may attach the MRAM chip to the package substrate. The first magnetic shielding film may shield magnetic interference between the MRAM chip and the package substrate. The second magnetic shielding film may be arranged over the MRAM chip to shield magnetic interference at an upper region over the MRAM chip. Thus, the magnetic shielding layer may be arranged between the bonding pads of the MRAM chip so that magnetic interference between the bonding pads may be suppressed. | 2015-11-19 |
20150333019 | SEMICONDUCTOR DEVICE AND METHOD FABRICATING THE SAME - According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground. | 2015-11-19 |
20150333020 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided, and the display panel comprises a GOA circuit; a first conducting wire and a second conducting wire are disposed in a region outside the GOA circuit; an insulating layer is disposed between the first conducting wire and the second conducting wire; and the first conducting wire, the insulating layer and the second conducting wire form a first capacitor. The display panel can protect the internal signal lines of the GOA circuit and the display panel, and increase the antistatic ability of the display panel and the yield of products. | 2015-11-19 |
20150333021 | SEMICONDUCTOR STRUCTRURE WITH COMPOSITE BARRIER LAYER UNDER REDISTRIBUTION LAYER AND MANUFACTURING METHOD THEREOF - A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer. | 2015-11-19 |
20150333022 | CONTACT PADS FOR INTEGRATED CIRCUIT PACKAGES - Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed. | 2015-11-19 |
20150333023 | Semiconductor Device Having Solderable and Bondable Electrical Contact Pads - A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable. | 2015-11-19 |
20150333024 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In order to achieve both a reduction in thermal resistance and an improvement in thermal deformation absorbing property of a semiconductor device having a packaging structure in which a semiconductor chip | 2015-11-19 |
20150333025 | ORGANIC COATING TO INHIBIT SOLDER WETTING ON PILLAR SIDEWALLS - The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes. | 2015-11-19 |
20150333026 | INTERCONNECT STRUCTURE WITH IMPROVED CONDUCTIVE PROPERTIES AND ASSOCIATED SYSTEMS AND METHODS - Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member. | 2015-11-19 |
20150333027 | Method of Forming Solder Bump, and Solder Bump - A solder bump formed on an Ni electrode with the use of a solder ball containing Bi as a main component and Sn as a sub component. The solder ball contains Sn from 1.0 to 10.0 mass % and at most 1.0 mass % of at least one of Cu and Ag. A solder joint portion obtained by use of the solder bump has at least one of Sn and an SnBi eutectic alloy. | 2015-11-19 |
20150333028 | WAFER LEVEL PACAKGES HAVING NON-WETTABLE SOLDER COLLARS AND METHODS FOR THE FABRICATION THEREOF - Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings. | 2015-11-19 |
20150333029 | PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated. | 2015-11-19 |
20150333030 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured. | 2015-11-19 |
20150333031 | SEMICONDUCTOR DEVICE WITH MECHANICAL LOCK FEATURES BETWEEN A SEMICONDUCTOR DIE AND A SUBSTRATE - An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die. | 2015-11-19 |
20150333032 | BONDING TOOL COOLING APPARATUS AND METHOD FOR COOLING BONDING TOOL - A bonding tool cooling apparatus ( | 2015-11-19 |
20150333033 | Pick-and-Place Tool for Packaging Process - A method includes moving a first bond head along a first guide apparatus for a first loop. The first guide apparatus is configured in a ring shape. The method also includes picking up a first die using the first bond head during the first loop, and aligning the first die with a first package substrate. The aligning the first die with the first package substrate includes moving the first package substrate in a first direction and a second direction. The first direction and the second direction are contained in a first plane parallel to the first loop. The method further includes placing the first die over the first package substrate during the first loop. | 2015-11-19 |
20150333034 | SEMICONDUCTOR MODULE BONDING WIRE CONNECTION METHOD - A method includes providing a subassembly having a circuit carrier with a first metallic surface portion, a first joining partner, which is integrally connected to the first metallic surface portion by means of a first connecting layer, and a second metallic surface portion. In a heat treatment, the second metallic surface portion is held uninterruptedly at temperatures which are higher than a minimum heat-treatment temperature of at least 300° C. Moreover, a second joining partner is provided. A fixed connection is produced between the second joining partner and the subassembly in that the second joining partner is integrally connected to the subassembly following completion of the heat treatment on the second surface portion. | 2015-11-19 |
20150333035 | ARTICLES INCLUDING BONDED METAL STRUCTURES AND METHODS OF PREPARING THE SAME - Articles including bonded metal structures and methods of preparing the same are provided herein. In an embodiment, a method of preparing an article that includes bonded metal structures includes providing a first substrate. A first metal structure and a second metal structure are formed on the first substrate. The first metal structure and the second metal structure each include an exposed contact surface. A bond mask is formed over the contact surface of the first metal structure. A second substrate is bonded to the first substrate through the exposed contact surface of the second metal structure. The bond mask remains disposed over the exposed contact surface of the second metal structure during bonding of the second substrate to the first substrate. A wire is bonded to the exposed contact surface of the first metal structure. | 2015-11-19 |
20150333036 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment. | 2015-11-19 |
20150333037 | METHOD FOR PRODUCING IMAGE PICKUP APPARATUS, METHOD FOR PRODUCING SEMICONDUCTOR APPARATUS, AND JOINED WAFER - A method for producing an image pickup apparatus includes: a process of fabricating a plurality of image pickup chips by cutting an image pickup chip substrate where light receiving sections and electrode pads are formed; a process of fabricating a joined wafer by bonding the image pickup chips to a glass wafer; a process of filling a gap between the plurality of image pickup chips with a sealing member made of a BCB resin or polyimide; a process of machining the joined wafer to reduce a thickness; a process of forming through-hole vias; a process of forming an insulating layer that covers the image pickup chips; a process of forming through-hole interconnections; a process of forming external connection electrodes, each of which is connected to each of the through-hole interconnections; and a process of cutting the joined wafer. | 2015-11-19 |
20150333038 | SEMICONDUCTOR DEVICE INCLUDING FILLING MATERIAL PROVIDED IN SPACE DEFINED BY THREE SEMICONDUCTOR CHIPS - A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each other, a third semiconductor chip mounted on the first and second semiconductor chips, first and second adhesive layers that are provided between the first and second semiconductor chips and the wiring substrate so as to bond the first and second semiconductor chips to the wiring substrate, and a third adhesive layer that is provided between the third semiconductor chip and the first and second semiconductor chips so as to bond the third semiconductor chip to the first and second semiconductor chips, with its thickness being made thicker than that of the first and second adhesive layers, a sealing layer covering the wiring substrate, and a filling layer that is provided between the first and second semiconductor chips and is different from the sealing layer. | 2015-11-19 |
20150333039 | BONDING PAD ARRANGMENT DESIGN FOR MULTI-DIE SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads. | 2015-11-19 |