45th week of 2015 patent applcation highlights part 58 |
Patent application number | Title | Published |
20150318791 | MOTOR DRIVE WITH SILICON CARBIDE MOSFET SWITCHES - Motor drive power conversion systems are provided including a rectifier and a switching inverter, wherein the switching devices of the rectifier, the inverter and/or of a DC/DC converter are silicon carbide switches, such as silicon carbide MOSFETs. Driver circuits are provided for providing bipolar gate drive signals to the silicon carbide MOSFETs, including providing negative gate-source voltage for controlling the off state of enhancement mode low side drivers and positive gate-source voltage for controlling the off state of enhancement mode high side drivers. | 2015-11-05 |
20150318792 | METHOD FOR DRIVING INVERTERS, AND INVERTER ADAPTED TO REDUCE SWITCHING LOSSES - A method for controlling the switching of an inverter, a bridge of which is adapted to chop a voltage from a direct voltage source for feeding a chopped voltage to a primary of a transformer; the inverter comprises a diode rectifier circuit receiving the input voltage from the secondary of the transformer in order to achieve a voltage fed to a chopper which feeds a load. The method comprises: a step in which the switches of the bridge are driven so that the power source is disconnected from the primary, the terminals of which are connected to each other by at least two of the electronic switches and recirculation diodes of the bridge itself, so that the voltage present on the secondary of said transformer is null; a step in which the switching of at least one electronic switch of a chopper branch is achieved when the voltage on the secondary is substantially null in order to minimize switching losses due to the opening/closing of the electronic switch of the chopper. | 2015-11-05 |
20150318793 | CONVERTER APPARATUS - A converter apparatus is presented which includes a converter that includes a switching element and an inductor, a controller that sets a duty at a predetermined duty setting cycle, and executes an ON/OFF switching of the switching element of the converter at switching timing according to a relationship between the set duty and a carrier signal, the predetermined duty setting cycle corresponding to a half cycle of the carrier signal. The controller determines the duty to be set at this duty setting cycle such that sampling of a current value of a current flowing through the inductor and calculation of the duty to be set at the next duty setting cycle based on the sampled current value are completed before next duty setting timing. | 2015-11-05 |
20150318794 | AUXILIARY RESONANT COMMUTATED POLE CONVERTER WITH VOLTAGE BALANCING CIRCUIT - A resonant power converter is provided. The resonant power converter comprises a balancing circuit for balancing the voltage in a feeding connection. The balancing circuit comprises: a first positive control means in series with an inductor, wherein the first positive control means and the inductor is coupled between the positive DC conductor and the feeding connection, and a second negative control means in series with the inductor, wherein the second negative control means are coupled between the negative DC conductor and the feeding connection. The first positive and second negative control means are adapted to be alternatingly switched on and off for balancing the resonant power converter, such that the voltage in the feeding connection is substantially the mean voltage of the positive DC conductor and the negative DC conductor. | 2015-11-05 |
20150318795 | DRIVING CIRCUIT FOR GENERATING VOLTAGE CONTROL SIGNALS - A driving circuit includes an activating end, an operation switch, a voltage control end, and an output switch. The activating end selectively outputs a first voltage control signal and a second voltage control signal. The operation switch is turned off according to the first voltage control signal to generate a low voltage control signal or is turned on according to the second voltage control signal to generate a high voltage control signal. The voltage control end generates a low voltage according to the low voltage control signal or generates a bias voltage according to the high voltage control signal. The output switch is turned off according to the low voltage to determine that an output voltage is the same as the low voltage, or is turned on according to the bias voltage to determine that the output voltage is the same as the high voltage. | 2015-11-05 |
20150318796 | INVERTER INRUSH CURRENT LIMITING - A method and circuit arrangement is described for start-up and shut-down of high power DC to AC inverters which limits inrush current for capacitor charging, reduces input and output relay contact stress and discharges internal capacitors upon shut down. A preferred inrush limiting component has a higher resistance when hot than when cold, such as an incandescent filament lamp. | 2015-11-05 |
20150318797 | HALF BRIDGE CIRCUIT, FULL BRIDGE CIRCUIT CONSTRUCTED WITH HALF BRIDGE CIRCUIT, AND THREE-PHASE INVERTER CIRCUIT CONSTRUCTED WITH HALF BRIDGE CIRCUIT - In a half bridge circuit according to one aspect of the present disclosure, when a voltage between a first terminal and a third terminal or a voltage between the first terminal and the second terminal is greater than or equal to a threshold voltage, a current is passed from the second terminal to the third terminal or from the third terminal to the second terminal according to a polarity of the voltage between the second terminal and the third terminal. When the current is passed from the third terminal to the second terminal, the voltage between the second terminal and the third terminal changes with respect to the voltage applied between the first terminal and the third terminal within a range where the voltage between the first terminal and the third terminal is less than or equal to the threshold voltage. | 2015-11-05 |
20150318798 | ELECTRIC POWER CONVERTER WITH A VOLTAGE CONTROLLER AND A CURRENT CONTROLLER - An electric power converter for converting AC to DC power or DC to AC power is disclosed. The converter includes a circuit for controlling the voltage and the circuit for controlling the current separately. The voltage is controlled by the switching modules and the up-side controller using the calculated target voltage. The current is controlled by the current controller using the calculated target current. | 2015-11-05 |
20150318799 | ACTUATOR APPARATUS, ELECTRONIC DEVICE, AND CONTROL METHOD - An actuator apparatus includes a pair of substrates facing each other; a plurality of bias actuators that each vary a gap dimension of a gap between the pair of substrates; a gap detection portion that detects the gap dimension; and a voltage control unit that controls driving of each of the bias actuators on the basis of the detected gap dimension. The bias actuators are located asymmetric relative to a driving central axis and are mutually independently driven; and the voltage control unit derives driving parameters for use in driving the bias actuators, on the basis of voltages and gap dimensions obtained by sequentially switching and driving the bias actuators on by one. | 2015-11-05 |
20150318800 | VIBRATION GENERATOR AND STACKED-STRUCTURE GENERATOR - The disclosure discloses a vibration generator and a stacked-structure generator. The vibration generator includes an arched friction unit | 2015-11-05 |
20150318801 | PIEZOELECTRIC ACTUATOR AND ROBOT - A piezoelectric actuator includes a piezoelectric element, a vibrating plate configured to vibrate according to application of a signal to the piezoelectric element, and a driven body driven by the vibration of the vibrating plate. The vibrating plate vibrates in a first mode according to a signal having a first frequency, vibrates in a second mode according to a signal having a second frequency, and vibrates in a third mode according to a signal having a third frequency. The first frequency and the second frequency are different. The first frequency and the third frequency are different. | 2015-11-05 |
20150318802 | DRIVE DEVICE FOR A VEHICLE - A drive device for a vehicle, in particular a rail vehicle, includes a set of drive units each having at least one electric traction motor and a power generation unit which is provided for generating power for the traction motor, and a set of motor contactor units each being assigned to a traction motor. In order to provide a type of drive device which has a high availability in the event of a failure, has few structural elements and can be produced economically, at least one motor contactor unit includes at least one switching device which is connected between the power generation unit for the associated traction motor and a feed point. | 2015-11-05 |
20150318803 | HYBRID PULSE WIDTH MODULATION METHOD FOR VARIABLE SPEED DRIVE - A system or method controlling a variable speed drive based on PWM techniques, wherein a first PWM method is used when the input current is less than a predetermined threshold value, for higher efficiency and lower total harmonic distortion (THD); and a second PWM method comprising a discontinuous modulation signal is used when the input current is greater than the predetermined threshold value for higher efficiency. By doing so, the maximum efficiency of VSD within the whole operation range can be achieved. | 2015-11-05 |
20150318804 | MOTOR CONTROL APPARATUS FOR VECTOR-CONTROLLING SENSORLESS MOTOR - A motor control apparatus that vector-controls a sensorless motor, including: an estimating unit configured to obtain an estimated phase value by estimating a phase of a rotor in the sensorless motor; and a generating unit configured to generate, from the estimated phase value and a phase command value of the rotor, a phase conversion value that is a phase difference between a rotary coordinate system and a static coordinate system in the vector control. The generating unit is further configured to output the phase command value as the phase conversion value when the rotor is caused to start to rotate, and change the phase conversion value so that the phase conversion value approaches the estimated phase value from a predetermined timing after the rotor is caused to start to rotate. | 2015-11-05 |
20150318805 | MULTI-MOTOR DRIVING DEVICE AND APPARATUS AND METHOD OF DRIVING MOTOR FOR WASHING MACHINE USING SAME - A motor driving apparatus for a washing machine, in which a motor is a washing machine motor with a double stator and a double rotor respectively having first and second U-phase, V-phase, and W-phase stator coils, includes: a motor controller for generating a drive signal in accordance with a washing mode, a rinsing mode and a dewatering mode; an inverter for generating a three-phase alternating-current (AC) power, in which any one-phase AC power of the three-phase AC power is applied in common to any one-phase stator coil of the first and second U-phase, V-phase, and W-phase stator coils for the washing machine motor; and a switching unit for switching to apply the remaining two-phase AC power of the three-phase AC power to any two-phase stator coils of the remaining two-phase stator coils of the first and second U-phase, V-phase, and W-phase stator coils for the washing machine motor. | 2015-11-05 |
20150318806 | Current Profile Strategy for Minimizing Torque Ripple and Current - A method of controlling an electric motor may include determining a desired torque at the electric motor. A current at a first phase of the electric motor may be calculated at a controller. The calculated current may be a current that results in supplying the desired torque at the electric motor. The controller may compare the calculated current to a predetermined threshold current, and when the calculated current is greater than the predetermined threshold current, the controller may reduce the calculated current to the predetermined threshold current and adjust a current in a second phase adjacent to the first phase of the electric motor to continue to supply the desired torque at the electric motor. | 2015-11-05 |
20150318807 | DIRECT TORQUE CONTROL METHOD FOR INHIBITING TORQUE RIPPLES - The present invention relates to a direct torque control method for inhibiting torque ripples, mainly comprising the following steps: establishing an MC voltage vector switching table visually displaying degrees of change in torque and flux, and, proposing, on the basis of the MC voltage vector switching table visually displaying the degrees of change in torque and flux, an MC-DTC mark-to-space ratio computing policy for torque quantification control. The MC-DTC mark-to-space ratio computing policy allows for inhibition of torque ripples of a PMSM speed control system and for a constant switching frequency, uses the MC voltage vector switching table visually displaying the degrees of change in torque and flux, has a simple algorithm, does not reply on motor parameters, and obviates the need for rotational coordinate transformation. | 2015-11-05 |
20150318808 | BRUSHLESS MOTOR CONTROL METHOD AND BRUSHLESS MOTOR CONTROL DEVICE AND ELECTRIC POWER STEERING DEVICE - A control device | 2015-11-05 |
20150318809 | VEHICLE AND CONTROL METHOD FOR VEHICLE - An ECU executes a program including: a step of setting a threshold β as a shutdown threshold when, during a power supply operation, a duration of a power supply stoppage exceeds a first time; a step of stopping an operation of an engine or prohibiting the engine from operating; and a step of executing system shutdown processing when an SOC of a storage apparatus falls to or below the shutdown threshold or the duration of the power supply stoppage exceeds a second time. | 2015-11-05 |
20150318810 | POWER GENERATION SYSTEM AND POWER GENERATION METHOD - A power generation system includes a medium circuit through which a medium is circulated; a circulation pump; an evaporator configured to heat the pressurized medium using heat of an external source so as to evaporate the medium, wherein the external source that the heat quantity is capable of fluctuating; an expander configured to be driven using the medium evaporated by the evaporator; a generator configured to be driven using the expander to generate power; and a flow rate control device configured to control the flow rate of the medium flowing into the expander such that, even when the heat quantity of the external source has fluctuated, the number of rotations of the expander or the generator is within a region in which the number of rotations is preset. | 2015-11-05 |
20150318811 | ELECTRICALLY-DRIVEN VEHICLE - An electrically-driven vehicle includes: a battery; an induction motor connected to the battery; a synchronous motor connected to the battery that is connected to the induction motor; and at least one electronic control unit configured to change a slip frequency command of the induction motor based on a predetermined frequency of current fluctuation when a temperature of the battery is low such that an amplitude of the current fluctuation increases, the current fluctuation being any one of current fluctuation of a battery current or current fluctuation of a battery-related current that relates to the battery current. | 2015-11-05 |
20150318812 | ELECTRIC MACHINE - An electric machine has a primary mechanical output or input, a plurality of electric sub-machine rotors each having an output or input shaft, a plurality of electric sub-machine stator magnets proximate the rotors, a drive train connecting each of the output or input shafts of the plurality of electric sub-machine rotors to simultaneously drive, or be driven by, the primary output shaft. Each sub-machine is selectively engaged or disengage depending on machine power. | 2015-11-05 |
20150318813 | REFRIGERANT COMPRESSOR DRIVES OFFERING ENHANCED ROBUSTNESS, EFFICIENCY AND RATED VOLTAGE OPERABILITY - Apparatuses, methods, and systems offering enhanced robustness, efficiency and rated voltage operability for refrigerant compressor drives are disclosed. An exemplary embodiment is a method of operating a variable frequency drive. The method includes operating the drive over a first operating range to provide at least a desired operating speed and minimize d-axis current, operating the drive over a second operating range including injecting d-axis current to provide at least the desired operating speed, operating the drive over a third operating range at a de-rated speed less than the desired operating speed. In the first operating range the drive input voltage is greater than a first value. In the second operating range the drive input voltage is lower than the first value and greater than a second value. In the third operating range the drive input voltage is lower than the second value. | 2015-11-05 |
20150318814 | An Engine Furnished With a System of Solar Panels to Which the Light Produced by the Combustion for the Generation of Electric Current is Transmitted - An engine includes at least a cylinder that forms a combustion chamber. In accordance with the invention, at least a photovoltaic surface is arranged to become hit by the light produced as a consequence of a combustion that takes place in the combustion chamber. In one embodiment, at least an optical fiber passes through the combustion chamber in such a way as to become irradiated, in use, by the light emitted as a consequence of the combustion that takes place inside the chamber In this embodiment, the photovoltaic panel is arranged externally to the combustion chamber and becomes irradiated by the light transported by the optical fiber after exiting the cylinder. | 2015-11-05 |
20150318815 | COMBUSTION, HEAT-EXCHANGE AND EMITTER DEVICE - A combustion, heat-exchange and emitter device ( | 2015-11-05 |
20150318816 | ROOF INSTALLATION SUPPORT FIXING DEVICE AND ROOF INSTALLATION SYSTEM - A fastener for a roof installation support, in particular for a support of a solar technology system, having an at least sectionally flexible baseplate section and a substantially stiff profile section rising up from the baseplate section, which profile section is constructed to surround and positively fix a profile section of the roof installation support. | 2015-11-05 |
20150318817 | PHOTOVOLTAIC MODULE MOUNTING ASSEMBLY - A photovoltaic module mounting assembly ( | 2015-11-05 |
20150318818 | SOLAR ENERGY COLLECTION SYSTEM - A system for collecting solar energy using a plurality of energy collection elements arranged in a planar array within a stationary base structure, each comprising: an energy capture unit with optical means of focusing directional sunlight parallel to its axis onto one or more sunlight-to-electricity converters within itself, and means of sensing divergence of its axis from the sun's direction; and an angular positioning unit that orients said capture unit about two nested axes by slidably mounting two arcuate tracks in opposed and perpendicular arcuate slots, a convex track within said energy capture unit and a concave track within said base structure, each said slot equipped with a drive apparatus that engages its respective track and moves the positioner along it. The invention provides methods for determining the shapes and arrangement of such elements so as to maximize aperture efficiency while preventing collisions of adjacent elements. | 2015-11-05 |
20150318819 | SOLAR PANEL HOUSING - A housing for a solar panel is provided and is comprised of a glazed element and a tray. The tray includes a plate, a pair of side walls, a top end cap and a bottom end cap. The tray further includes a notch and a securement means configured to engage the notch and secure the housing to a base. The tray also includes a lip configured to seat the glazed element. Wherein the plate, the pair of side walls, the top end cap, the bottom end cap are formed of a single material and configured as a single integral component and wherein the plate, the pair of side walls, the top end cap and the bottom end cap are collectively configured to form a cavity. | 2015-11-05 |
20150318820 | Rotating Furling Catenary Solar Concentrator - The present invention relates to a rotating solar concentrating device wherein reflective sheets hung in a catenary trough shape capable of solar concentration may be protectively furled and balanced and rotated about a vertical axis. The reflective sheets may be furled to protect them from damage from wind, rain, and dust. In some embodiments, rotating parts of the device may be hung from supports above. In some embodiments, a furling mechanism may initiate protective furling in response to damaging environmental factors. Some embodiments may concentrate light on a photovoltaic cell wherein the photovoltaic cell is cooled by immersion in a heat pipe. In some embodiments, reflective surfaces may be supported by cables that are tensioned by a hanging, rotating ballast. In some embodiments, the device may be employed in a ganged array. In some embodiments, the invention may harvest wind energy as a vertical axis wind turbine (VAWT). | 2015-11-05 |
20150318821 | CONCENTRATOR PHOTOVOLTAIC ASSEMBLY - A concentrator photovoltaic module that has a secondary optical element that has alignment features that cooperate with alignment feature of a solar cell assembly to self-align the secondary optical element with the solar cell. The secondary optical element is secured directly to the backplate or to the solar cell assembly. The secondary optical element is spaced-apart from the solar cell, which avoids shear stress between the secondary optical element and the solar cell. | 2015-11-05 |
20150318822 | REDUCING UNEQUAL BIASING IN SOLAR CELL TESTING - A solar cell testing apparatus can include a first electrical probe configured to receive a first voltage at a first location of a solar cell. The solar cell testing apparatus can also include a second electrical probe configured to receive a second voltage at a second location of the solar cell, where the second location is of the same polarity as the first location. | 2015-11-05 |
20150318823 | DEMODULATION DEVICE, AND DEMODULATION INTEGRATED DEVICE AND MODULATION AND DEMODULATION INTEGRATED DEVICE USING THE SAME - A demodulation device according to the present invention includes a spin device configured to output an oscillation signal; a phase control unit configured to assign a predetermined phase locking characteristic to the spin device, thereby causing the oscillation signal to be tuned to a modulation signal that is input to the spin device; and a detector configured to demodulate the oscillation signal that is output by the spin device and tuned to the modulation signal, thereby restoring information carried on the oscillation signal. | 2015-11-05 |
20150318824 | Variable Duty-Cycle Multi-Standard Mixer - An adjustable mixer is disclosed that is capable of operating in different modes in order to satisfy the mixing requirement of multiple radio access technologies (RATs). The adjustable mixer includes a LO signal generating portion and a mixing portion. Depending on the mixing requirements of the RAT, the adjustable mixer can operate in any one of multiple modes, each mode having a specific configuration for the LO signal generating portion and the mixing portion. The LO signal generating portion generates a LO signal having a particular duty cycle, depending on the selected mode, for use by the mixing portion. The mixing portion has an adjustable circuit configuration that can be dynamically reconfigured based on the selected mode, and which allows the mixing portion to successfully mix received signals using the corresponding LO signals generated by the LO signal generating portion. | 2015-11-05 |
20150318825 | Harmonic Reject Receiver Architecture and Mixer - Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection. | 2015-11-05 |
20150318826 | Power supply stage - There is described a method of generating a power supply tracking a reference signal, comprising the steps of: filtering the reference signal; generating a first voltage in dependence on the filtered reference signal; generating a second voltage in dependence on the reference signal; and combining the first and second voltages to provide a power supply voltage. | 2015-11-05 |
20150318827 | POWER AMPLIFIER WITH ENVELOPE INJECTION - A device and a method for an amplifier having reduced intermodulation (IM) distortion output products are presented. An amplifier has an output, and at least one of a gate bias input and a drain supply input. The amplifier is configured to receive an input signal and output an amplified signal at the output of the amplified. An input is configured to receive an envelope signal. The input is connected to the at least one of the gate bias input and the drain supply input and the envelope signal is at least partially determined by an attribute of the input signal to the amplifier. A controller is configured to modify at least one of an amplitude and a phase of the envelope signal to reduce a magnitude of an intermodulation distortion product of the amplifier. | 2015-11-05 |
20150318828 | A QUASI-BROADBAND AMPLIFIER ACCORDING TO THE DOHERTY PRINCIPLE - An amplifier comprises a first amplifier circuit, a second amplifier circuit, a hybrid-coupler circuit and a termination. The hybrid-coupler circuit comprises an output port and an isolation port. The termination in this context is connected to the isolation port of the hybrid-coupler circuit. The termination comprises a first switch, a first capacitor and a first inductance. | 2015-11-05 |
20150318829 | LOW NOISE AMPLIFIER FOR MEMS CAPACITIVE TRANSDUCERS - This application relates to amplifier circuitry for amplifying a signal from a MEMS transducer. A super source follower circuit ( | 2015-11-05 |
20150318830 | HIGH FREQUENCY AMPLIFIER AND METHOD OF COMPENSATING FOR DISTORTION - Disclosed is a high frequency amplifier which can properly compensate for distortion generated in a power amplifier even when an observation band of a feedback signal is made narrow. The high frequency amplifier includes a data correction unit that corrects transmission data through a digital pre-distortion method, and the data correction unit includes an orthogonalizer that orthogonalizes and outputs respective order components of a polynomial model for the digital pre-distortion method, and a compensator that compensates for a memory effect of the power amplifier for an output of the orthogonalizer. | 2015-11-05 |
20150318831 | CURRENT-LIMITING IN AN AMPLIFIER SYSTEM - One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude. | 2015-11-05 |
20150318832 | CONFIGURABLE POWER AMPLIFIER AND RELATED CONSTRUCTION METHOD - A multiple-path, configurable, radio-frequency (RF) circuit is provided, including: a first amplifier path amplify a first RF signal to generate a first amplified signal; a second amplifier path configured to amplify a second RF signal to generate a second amplified signal; a corrective input matching circuit, configured to change first input-impedance-matching properties of the first amplifier path, and to change second input-impedance-matching properties of the second amplifier path; a first isolation element configured to selectively ground an input node of the second amplifier path; a second isolation element configured to selectively ground an output node of the second amplifier path; and a third isolation element connected between the first and second amplifier paths, configured to selectively isolate the corrective input matching circuit from first and second input nodes of the first and second amplifier paths, respectively, or connect the corrective input matching circuit to the first and second input nodes. | 2015-11-05 |
20150318833 | MEMS Microphone And Method Of Operating The MEMS Microphone - The present invention concerns a MEMS Microphone ( | 2015-11-05 |
20150318834 | COMMON MODE NOISE REDUCTION CIRCUIT - A common mode noise reduction circuit includes at least one first input end, at least one second input end, at least one first output end, and at least one second output end. The circuit is further provided with at least one resistor, at least one inductor, and at least one capacitor, symmetrically disposed within the circuit loop defined by the four ends. Common mode noise, after entering the circuit, is transformed into heat by the resistance of the circuit such that the common mode noise is suppressed. Differential mode signals, on the contrary, after entering the circuit, can pass through the circuit with minimum loss. | 2015-11-05 |
20150318835 | CIRCUIT SUBSTRATE AND BRANCH CIRCUIT - A circuit substrate includes a substrate body, an input signal line conductor with which the substrate body is provided and included in an input path, a first mounting portion provided on a main surface of the substrate body, included in a first output path and on which a high-pass filter including a lumped-parameter element is mounted, at least one first output signal line conductor with which the substrate body is provided and included in the first output path, and a second mounting portion provided on the main surface of the substrate body, included in a second output path and on which a low-pass filter including a lumped-parameter element is mounted. The first output signal line conductor provided farthest upstream in a signal propagation direction is connected to the input signal line conductor via a first lumped-parameter element mounted on the main surface of the substrate body. | 2015-11-05 |
20150318836 | SECOND-ORDER FILTER WITH NOTCH FOR USE IN RECEIVERS TO EFFECTIVELY SUPPRESS THE TRANSMITTER BLOCKERS - The disclosed invention relates to a transceiver system comprising a notch filter element configured to suppress transmitter blockers (i.e., transmitter interferer signals) within a reception path. In some embodiments, the transceiver front-end comprises a differential reception path, having a first differential branch and a second differential branch, configured to provide an RF differential input signal having a transmitter blocker to a transimpedance amplifier, comprising a first-order active filter and a notch filter element. The notch filter element comprises a stop band corresponding to a frequency of a transmitted signal, such that the notch filter element suppresses the transmitted blocker without degrading the signal quality of the received differential input signal. | 2015-11-05 |
20150318837 | ACOUSTIC RESONATOR DEVICE WITH AIR-RING AND TEMPERATURE COMPENSATING LAYER - A bulk acoustic wave (BAW) resonator device includes a substrate defining a cavity, a bottom electrode formed over the substrate and at least a portion of the cavity, a piezoelectric layer formed on the bottom electrode, and a top electrode formed on the piezoelectric layer. An air-wing and an air-bridge are formed between the piezoelectric layer and the top electrode, the air-wing having an inner edge that defines an outer boundary of an active region of the BAW resonator device. The BAW resonator device further includes a temperature compensation feature having positive temperature coefficient for offsetting at least a portion of a negative temperature coefficient of the piezoelectric layer. The temperature compensation feature extends outside the active region by a predetermined length. | 2015-11-05 |
20150318838 | ENHANCED MEMS VIBRATING DEVICE - A MEMS vibrating device includes a substrate, at least one anchor on a surface of the substrate, and a vibrating body suspended over the substrate by the at least one anchor. The vibrating body includes a first piezoelectric thin-film layer, a second piezoelectric thin-film layer over the first piezoelectric thin-film layer, and an inter-digital transducer embedded between the first piezoelectric thin-film layer and the second piezoelectric thin-film layer. Embedding the inter-digital transducer between the first piezoelectric thin-film layer and the second piezoelectric thin-film layer may result in enhanced vibrational characteristics of the MEMS vibrating device, thereby increasing the performance thereof. | 2015-11-05 |
20150318839 | SWITCHABLE FILTERS AND DESIGN STRUCTURES - Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode. | 2015-11-05 |
20150318840 | SEMICONDUCTOR DEVICE INCLUDING A DECIMATION FILTER THAT PERFORMS PREDETERMINED FILTERING - An electric-power meter device includes a sensor which detects an electric energy and which outputs an analog signal with 50 Hz to 60 Hz, and a microcomputer which includes an analog-to-digital converter which, based on a delta-sigma modulation scheme, converts the input analog signal provided from the sensor to a digital signal based on a required sampling rate to output the digital signal, a central processing unit that performs data processing based on the digital signal converted by the analog-to-digital converter, and a timer unit that outputs a trigger signal in a cycle corresponding to the required sampling rate. The analog-to-digital converter includes a delta-sigma modulator and a decimation filter. | 2015-11-05 |
20150318841 | METHOD OF IMPROVING NOISE IMMUNITY IN A SIGNAL PROCESSING APPARATUS, AND A SIGNAL PROCESSING APPARATUS HAVING IMPROVED NOISE IMMUNITY - A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period. | 2015-11-05 |
20150318842 | APPARATUS AND METHOD FOR PREVENTING MULTIPLE RESETS - Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level. | 2015-11-05 |
20150318843 | GATE CONTROL CIRCUIT - An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor. | 2015-11-05 |
20150318844 | SCHMITT TRIGGER WITH THRESHOLD VOLTAGE CLOSE TO RAIL VOLTAGE - Voltage level shifting in a switching output stage is presented. The circuit may include a switching output stage configured to receive an analog input signal and provide a responsive digital output signal, the switching output stage having a first switching device coupled to a first supply voltage and a second switching device coupled to a second supply voltage, the first switching device and the second switching device being coupled to a common output node. The apparatus may also include a voltage level shifter circuit coupled to a switching control node of the second switching device, the voltage level shifter configured to shift a voltage level at the switching control node of the second switching device relative to the analog input signal, wherein the digital output signal at the common output node transitions as the input signal reaches a predetermined threshold value. | 2015-11-05 |
20150318845 | Multi-Bit Standard Cells For Consolidating Transistors With Selective Sourcing - A method for designing a standard cell, e.g. a multi-bit flip-flop, can include identifying a first set of transistors. This first set functions to source power or ground to circuits of the standard cell. A second set of transistors can be determined and correlated. This second set forms at least part of the first set of transistors. Each correlated group in the second set of transistors receives identical signals, e.g. scan enable, reset, and/or set signals, and provides a same sourcing. A third set of transistors can then be created. This third set has fewer transistors than the second set. The second set of transistors can be deleted in the standard cell. The third set of transistors can be connected to the circuits of the standard cell. This method can significantly extend circuit consolidation to improve the area benefit of multi-bit standard cells. | 2015-11-05 |
20150318846 | HIGH VOLTAGE NANOSECOND PULSER WITH VARIABLE PULSE WIDTH AND PULSE REPETITION FREQUENCY - A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds. | 2015-11-05 |
20150318847 | VOLTAGE CONTROLLED SWITCHING ELEMENT GATE DRIVE CIRCUIT - A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors. | 2015-11-05 |
20150318848 | SEGMENTED DRIVER FOR A TRANSISTOR DEVICE - A segmented driver including at least one drive pin and a sense pin, a driver circuit, a comparator, and a controller. The driver circuit activates a selected drive level between the drive pins and a reference node. The comparator compares a voltage of the sense pin with a threshold voltage and provides a threshold indication when the voltage of the sense pin reaches the threshold voltage. The controller commands the driver circuit to activate a first drive level in response to an off indication, and commands the driver circuit to switch to a second, lower drive level in response to the threshold indication. The driver circuit may be implemented using low resistive current devices. Multiple drive pins may be included, each for selectively activating a corresponding drive path to adjust drive level. The threshold voltage may be set using a current source and resistor, and may be adjusted for temperature. | 2015-11-05 |
20150318849 | GATE DRIVING CIRCUIT AND DRIVING METHOD THEREOF - A gate driving circuit and a driving method thereof are provided. The gate driving circuit includes a control signal generator and at least one gate channel set, each of the at least one gate channel set includes a plurality of gate channels, and the plurality of gate channels share a level shifter. The driving method includes generating a plurality of first control signals and a plurality of second control signals according to a gate driver start pulse, and determining that one of the gate channels uses the level shifter during a time period according to the plurality of first control signals and the plurality of second control signals. Therefore, the number of the level shifters can be decreased. | 2015-11-05 |
20150318850 | SWITCHING ELEMENT DRIVE CIRCUIT, POWER MODULE, AND AUTOMOBILE - A switching element drive circuit of the present invention outputs a voltage to the switching element by use of a voltage output unit configured as an amplifier circuit having a voltage amplification factor of 1 to drive the switching element. When the switching element is turned on, a turn-on voltage having a value higher than a threshold voltage of the switching element and lower than a value of a voltage of a power supply of the switching element drive circuit is provided to the voltage output unit. After elapse of a turn-on voltage maintenance period, a voltage provided to the voltage output unit is switched by a voltage switching unit to the voltage of the power supply of the switching element drive circuit. | 2015-11-05 |
20150318851 | DEVICES AND SYSTEMS COMPRISING DRIVERS FOR POWER CONVERSION CIRCUITS - An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of V | 2015-11-05 |
20150318852 | RF SWITCH CIRCUIT - A RF switching arrangement ( | 2015-11-05 |
20150318853 | Gate Boosting Transmission Gate - A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold. | 2015-11-05 |
20150318854 | PROPORTIONAL FEEDBACK FOR REDUCED OVERSHOOT AND UNDERSTOOT IN A SWITCHED OUTPUT - Embodiments of apparatuses and methods for proportional feedback for reduced overshoot and undershoot in a switched output are described. An embodiment of an apparatus includes a switching output stage configured to receive an input signal and provide a responsive output signal. The apparatus may also include a pulling circuit coupled to one of the first switching device and the second switching device. The pulling circuit may pull a control voltage of power transistors in the switching output stage to reduce impedance of at least one of the transistors in response to a determination that the output signal at the common output node is outside of a predetermined range of a threshold value. Pulling strength may increase as a voltage difference between the output signal and one of the first supply voltage and the second supply voltage increases. | 2015-11-05 |
20150318855 | PULSE GENERATOR AND DRIVING CIRCUIT COMPRISING THE SAME - A pulse generator includes a first inverter configured to inverse an input pulse and output a result, a second inverter configured to inverse the output of the first inverter and output a result, a clamp inverter configured to generate a clamping voltage by clamping the output of the second inverter and generate an output pulse through a source follower which operates according to the clamping voltage, and a temperature compensator configured to compensate for variations in the clamping voltage caused by temperature change. | 2015-11-05 |
20150318856 | GRAPHENE-BASED NON-BOOLEAN LOGIC CIRCUITS - A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits. | 2015-11-05 |
20150318857 | SYNCHRONISED LOGIC CIRCUIT - Consistent with an example embodiment, the disclosed includes a synchronised logic circuit comprising: an input module; an output module; a decision logic module connected between the input and output modules and configured to provide a next output state to the output module dependent on a current input state provided from the input and output modules; a clock module connected to the input and output modules and configured to provide a clock signal for synchronising operation of the input and output modules; and an input detection module connected to the input module and configured to provide an enable signal to the clock module on detection of a change in an input provided to the input module, wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal from the input detection circuit. | 2015-11-05 |
20150318858 | Clock generation circuit and method thereof - This invention discloses a clock generation circuit and a clock generation method for generating a clock. The clock generation circuit includes a reference clock generation circuit, which is installed in a chip for independently generating a reference clock; a temperature sensor for sensing an ambient temperature to generate temperature information; a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient according to the temperature information; and a clock adjusting circuit, coupled to the clock generation circuit, for generating the clock according to the reference clock and the temperature compensation coefficient. The temperature compensation module generates the temperature compensation coefficient dynamically such that the frequency of the clock approaches a target frequency and does not substantially vary with the temperature. | 2015-11-05 |
20150318859 | CHARGE PUMP CIRCUIT USED FOR CHARGE PUMP PHASE-LOCKED LOOP - A charge pump circuit used for a charge pump phase-locked loop that includes a charging and discharging unit, two complementary circuit units, two operational amplifier units, an inverter unit, and a current mirror unit. The charge pump circuit resolves the matching problem of charging and discharging currents and the charge sharing problem in existing charge pump circuits. Both complementary circuit units positively and reversely compensate the charging and discharging unit to keep the charging and discharging currents of capacitors constant. Thus, the problem of the change of charging and discharging currents is resolved, the voltage linear variation of the charge pump capacitors is achieved, and the charging and discharging of the capacitors can be accurately controlled. The charge pump circuit is simple in structure, easy to integrate, high in the matching precision of the charging and discharging current sources, and suitable for low voltage and low power consumption applications. | 2015-11-05 |
20150318860 | LOW NOISE PHASE LOCKED LOOPS - Aspects of circuits and methods for generating an oscillating signal are disclosed. The circuit includes a phase detector configured to output first and second signals responsive to a phase difference between two input signals. The phase detector is further configured to disable the first signal when outputting the second signal and to disable the second signal when outputting the first signal. The circuit further includes a voltage controlled oscillator (VCO) configured to generate an oscillating signal having a tunable frequency responsive to the first and second signals. | 2015-11-05 |
20150318861 | SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE - A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle. | 2015-11-05 |
20150318862 | SYSTEMS AND METHODS FOR DATA CONVERSION - Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value. | 2015-11-05 |
20150318863 | RESIDUAL ERROR SAMPLING AND CORRECTION CIRCUITS IN INL DAC CALIBRATIONS - In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error. | 2015-11-05 |
20150318864 | CURRENT IMPULSE (CI) DIGITAL-TO-ANALOG CONVERTER (DAC) - A current impulse (CI) method is provided for converting digital data signals to analog values. First, digital data hits are converted into current impulses. Then, the current impulses are converted into analog currents representing the digital data hits. More typically, the method accepts a k-bit digital word, and converts the k-bit digital word into (k) corresponding current impulses. In one aspect, the method accepts (n) consecutive k-bit digital words. Then, for each bit position in the k-bit digital word, (n) consecutive bits are sampled using (n) consecutive phases of an n-phase clock, creating (n) interleaved current impulses. The (n) interleaved current impulses are converted into an analog current representing the (n) consecutive k-bit digital words. Alternatively, (n) consecutive hits are sampled using (n) consecutive phases of an n-phase clock for each bit position in the k-bit digital word, creating (n) summed current impulses. A CI digital-to-analog converter is also provided. | 2015-11-05 |
20150318865 | METHOD AND SYSTEM FOR CODING INFORMATION - A method and an apparatus are described for coding information, the method comprising obtaining a list of integers to be encoded; determining a hyper-pyramid having a dimension adapted to encode the list of integers, the hyper-pyramid having a plurality of vertices whose number is determined by the degree of the hyper-pyramid, which is equal to the sum of the integers of the list of integers and by the dimension of the hyper-pyramid which is equal to the number of integers of the list of integers minus one; indexing the list of integers in the hyper-pyramid using an indexing system; and providing an indication of the indexing of the list of integers in the hyper-pyramid. | 2015-11-05 |
20150318866 | MEASUREMENT METHOD, MEASUREMENT APPARATUS AND MEASUREMENT PROGRAM - [Problem] To shorten the measurement time, while maintaining the measurement precision, for a data converter of delta-sigma system. | 2015-11-05 |
20150318867 | HIGH PERFORMANCE CRC CALCULATION WITH SMALL FOOTPRINT - A cyclic redundancy check (CRC) can be determined with fewer resources within a communication system. A CRC interface component is configured to receive an array of bits as an input via an N-bit data pathway, and receive a CRC previous output from a feedback component coupled to a CRC output, in which N can comprise an integer greater than one. A parallel CRC component can be configured to generate a CRC current output from a plurality of parallel processing pipelines that are configured to concurrently process at least a part of the array of bits and the CRC previous output with a set of parallel CRC logic operations. The set of CRC logic operations can include a masking operation and a parity operation. | 2015-11-05 |
20150318868 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present technology relates to a data processing apparatus and a data processing method that are able to provide an LDPC code with a good error rate. | 2015-11-05 |
20150318869 | ENCODING AND SYNDROME COMPUTING CO-DESIGN CIRCUIT FOR BCH CODE AND METHOD FOR DECIDING THE SAME - An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of X | 2015-11-05 |
20150318870 | VARIABLE WIDTH ERROR CORRECTION - Variable width error correction is described. A memory controller can determine, from a memory address, what type of error correction is to be applied for the address region of that memory address and can generate commands for the memory device. An amount of error correction metadata associated with that address region may vary depending on the spatial location of the address region. In some cases, two translations may be performed: one by a processor using information set up by an operating system and another by the memory controller (or the memory device). In other cases, a single translation may be performed, for example by a processor using information set up by the operating system, which can determine the variable error correction during translation of a virtual address region to a real physical address region. | 2015-11-05 |
20150318871 | ERROR CORRECTION WITH SECONDARY MEMORY - A memory system includes a memory having a plurality of address locations, each address location configured to store data and one or more error correction bits corresponding to the data. A secondary memory includes a plurality of entries, and each entry configured to store an address value of an address location of the memory and one or more error correction bits corresponding to the data stored at the address location of the memory. The error correction bits in the secondary memory can be used to correct errors in a subset of the memory having a different number of storage bits than the error correction bits in the memory. | 2015-11-05 |
20150318872 | Adaptive Span Control - A method of transmitting data determines a measure of consecutive packet loss in a network; a ratio of a number of data packets and a number of error correction packets is selected in dependence on the measure. A stream of data packets is generated, and a stream of error correction packets is generated in dependence on the stream of data packets such that the proportion of error correction packets generated to the data packets generated is commensurate with the selected ratio. | 2015-11-05 |
20150318873 | ITERATIVE DECODER WITH CONFIGURABLE POOL OF DECODING STAGES - An apparatus includes a plurality of decoding stages, each configured to perform a decoding iteration of an Error Correction Code (ECC), and control circuitry. The control circuitry is configured to receive two or more input signals that carry data encoded with the ECC, to adaptively select an allocation that specifies a respective number of decoding iterations of the ECC to be performed on each of the input signals, to configure the decoding stages in the plurality in one or more cascades in accordance with the allocation, and to decode the input signals using the cascaded decoding stages. | 2015-11-05 |
20150318874 | PAIRING DEVICES USING ACOUSTIC SIGNALS - Techniques for pairing devices using acoustic signals are described. Disclosed are techniques for receiving an acoustic signal at a microphone coupled to a first device, the acoustic signal being encoded with data representing a first parameter associated with a second device, receiving an electromagnetic signal at an antenna coupled to the first device, the electromagnetic signal being encoded with data representing a second parameter associated with the second device, and determining a match between the first parameter and the second parameter. A pairing may then be generated between the first device and the second device. A pairing may include generating data representing a key, the key being configured to authenticate a pairing of the first device and the second device. A pairing may create a secure connection between the first device and the second device. | 2015-11-05 |
20150318875 | Data Processing in a Digital Subscriber Line Environment - A device is suggested comprising a first DSL system operating in a first frequency band, a second DSL system operating in a second frequency band and a filter unit connected to a line and to each of the first DSL system and the second DSL system. | 2015-11-05 |
20150318876 | Antenna Array With Integrated Filters - An exemplary antenna system has first and second antenna elements, where a diplexer is connected to each second element. First phase shifters are connected to the first elements and to the diplexers, and second phase shifters are connected to the diplexers, but not to the first elements. Either a different bandpass filter is connected to the first and second phase shifters or a single multiplexer is connected to all phase shifters. The antenna system can be used to support communications over first and second sub-bands with independent beam tilts and equivalent beamwidths, where all of the elements are used for the first sub-band, and the second elements, but not the first elements, are used for the second sub-band. Each first element is separated from an adjacent element by a first distance, and each second element is separated from an adjacent element by a second distance different from the first distance. | 2015-11-05 |
20150318877 | MODULATION METHOD FOR IMPROVING SIGNAL CONVERSION GAIN AND HIGH-GAIN MODULATOR THEREOF - A modulation method includes sampling the first input signal by using the first local oscillation signal and the second local oscillation signal to generate the first sampled signal, sampling the second input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the second sampled signal, sampling the second input signal by using the first local oscillation signal and the second local oscillation signal to generate the third sampled signal, sampling the first input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the fourth sampled signal, adding the first sampled signal and the second sampled signal to produce the first modulation signal, adding the third sampled signal and the fourth sampled signal to generate the second modulation signal, and adding the first modulation signal and the second modulation signal to generate an output signal. | 2015-11-05 |
20150318878 | AVOIDING SELF INTERFERENCE USING CHANNEL STATE INFORMATION FEEDBACK - Disclosed herein is a system, apparatus, and method for reducing self-interference within a wireless network device using channel state information feedback and beamforming techniques. The self-interference within a device may be reduced by first transmitting, by a first circuitry, a first set signals using a first radiation pattern through a first set of antennas coupled with the first circuitry. Then, based on feedback information associated with the first set of signals detected by a second circuitry of the device, a second radiation pattern to be used by the first circuitry and the first set of antennas that reduces receipt of signals by the second circuitry that are transmitted by the first set of antennas or leaked from the first circuitry may be determined. Thereafter, a second set of signals may be transmitted by the first set of antennas using the second radiation pattern. | 2015-11-05 |
20150318879 | METHOD FOR LOCATING DEFECTIVE POINTS IN A HIGH FREQUENCY (HF) SIGNAL TRANSMISSION PATH - A method for locating defects in a signal transmission path by generating an HF signal having a frequency f | 2015-11-05 |
20150318880 | Digital Pre-Distortion for High Bandwidth Signals - A digital pre-distortion arrangement is disclosed. The arrangement comprises a respective filter bank for each of two or more initial signals to be amplified simultaneously by a non-linear power amplifier, N combiners, N pre-distorters and a multiplexer. Each respective filter bank comprises N interrelated filters. Multiplexed impulse responses of the interrelated filters define an overall filter function comprising a pass band associated with a transmission frequency of the initial signal. Each respective filter bank is configured to filter the respective initial signal in each of the interrelated filters to produce N digital filtered signals. The initial signal and each of the digital filtered signals have sample rate R. Each of the combiners is configured to combine corresponding digital filtered signals of each of the two or more initial signals to produce a composite digital signal having sample rate R. Each of the pre-distorters is configured to apply digital pre-distortion at a processing rate R to a respective one of the composite digital signals to produce a pre-distorted composite digital signal having sample rate R. The multiplexer is configured to multiplex the N pre-distorted composite digital signals to produce a pre-distorted digital signal having a sample rate N times R, wherein the pre-distorted digital signal comprises a signal component of each of the two or more initial signals and N times R is greater or equal to a total bandwidth comprising the transmission frequencies of the two or more initial signals. Corresponding method, transmitter and wireless communication device are also disclosed. | 2015-11-05 |
20150318881 | COMMUNICATIONS SYSTEM - A communication method and system for communication utilizing modulation of digital signals, such as by targets and/or by use of low-complexity tags is presented. Targets may include any device or object that may alter signals, and tags can include a device with the ability to reflect and/or alter the properties of the signals and, in doing so, impose specific modulations on or alterations of such signals. Modulations can be sensed or detected using a receiver or receivers implementing processing algorithms derived from passive radar detection operations or other processes. | 2015-11-05 |
20150318882 | PASSIVE INTERMODULATION DETECTION - A method, apparatus and receiver for detecting intermodulation distortion (IMD) affecting a received signal in a wireless receiver are provided. One method includes determining a measurement indicative of IMD based on at least one transmit signal. When the measurement indicative of IMD exceeds a first pre-determined level, at least one sample of an amplitude of a signal output by the wireless receiver is collected in a first data set. When the measurement indicative of intermodulation distortion does not exceed a second pre-determined level, the second predetermined level being less than the first predetermined level, at least one sample of an amplitude of the signal output by the wireless receiver is collected in a second data set. A comparison is performed based on data of the first data set and on data of the second data set to determine a measure of IMD. | 2015-11-05 |
20150318883 | INTERFERENCE SUPPRESSION FOR CDMA SYSTEMS - Interference is cancelled from a baseband signal by synthesizing interference from estimated symbols in interfering subchannels. The estimated symbols are hard-coded, soft weighted, or zeroed, depending on the value of an estimated pre-processed signal-to-interference-and-noise ratio (SINR) in each subchannel in order to maximize a postprocessed SINR. The estimated pre-processed SINR is obtained from averages of estimated symbol energies and estimated noise variances, or from related statistical procedures. | 2015-11-05 |
20150318884 | RADIOFREQUENCY SIGNAL RECEIVER DESIGNED TO BE INSTALLED ON A SATELLITE - A receiver for radiofrequency signals designed to be installed on board a satellite comprises: a device for frequency controlling the receiver allowing the reception frequency of the receiver to be adjusted based on a frequency command; and a filtering assembly of the bandpass filter type having a passband, referred to as passband of the filtering assembly, having an adjustable passband width able to take a set of values, the filtering assembly allowing the bandwidth of a first signal representative of the input signal of the receiver to be limited to the passband of the filtering assembly; adjustment means allowing the width of the passband of the filtering assembly to be adjusted using a filtering passband control; power acquisition means allowing a measurement of the power of the first signal to be delivered at the output of the filtering assembly. | 2015-11-05 |
20150318885 | MOBILE ELECTRONIC DEVICE HOLDER - A mobile electronic device holder ( | 2015-11-05 |
20150318886 | Voice Agent - The invention relates to a mobile phone, and more particularly, a mobile phone with less RF radiation. | 2015-11-05 |
20150318887 | SYSTEM AND METHOD FOR PROVIDING ACTIVE RF SHIELDING - A system and method for removing radio frequency emissions from an electronic device. The system comprises collectors for collection of the radio frequency signals, combiners for combining the signals to produce a combined signal, fiber optic transmitter for up-converting the combined radio frequency signals to an optical wave length signal, optical fiber for directing the optical signal, and a heat sink for terminating the optical signal. | 2015-11-05 |
20150318888 | Protective case for portable electronic device - A protective case for a portable electronic device that is composed of two linked protective cover panels. The first panel is to carry the device and the second has an adjustable fastener on the internal side. The adjustable fastener consists of two parts which are connected to and can be parted from each other. | 2015-11-05 |
20150318889 | BYPASS PATH LOSS REDUCTION - Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced. | 2015-11-05 |
20150318890 | HIGH-FREQUENCY SWITCH MODULE - A high-frequency switch module includes a switch IC, a phase adjustment circuit, and a filter circuit. The phase adjustment circuit, which includes an inductor and capacitors, includes a π-type circuit in which the inductor is connected in series between an individual terminal and the filter circuit. The filter circuit is an LC parallel resonant circuit including a filter inductor and a filter capacitor. A distortion second harmonic signal from the individual terminal of the switch IC is reflected by the filter circuit through the phase adjustment circuit and returns to the switch IC through the phase adjustment circuit. This distortion second harmonic signal, whose phase is adjusted by the phase adjustment circuit, is cancelled out by a distortion second harmonic signal output to a common terminal of the switch IC. | 2015-11-05 |