45th week of 2015 patent applcation highlights part 53 |
Patent application number | Title | Published |
20150318291 | SEMICONDUCTOR MEMORY WITH U-SHAPED CHANNEL - A semiconductor memory with a U-shaped channel comprises: a U-shaped channel region arranged in a semiconductor substrate, a source region, a drain region, a first layer of insulation film arranged on the U-shaped channel region, a floating gate provided with a notch, a second layer of insulation film, a control gate, a p-n junction diode arranged between the floating gate and the drain region, and a gate controlled diode formed by the control gate, the second layer of insulation film, and the p-n junction diode and using the control gate as a gate. Under the precondition of not increasing the manufacturing cost and difficulty of the semiconductor memory with a U-shaped channel and not affecting the performance of the semiconductor memory with a U-shaped channel, the dimension of a semiconductor storage device is further reduced and the chip density is increased by arranging the notch in the floating gate. | 2015-11-05 |
20150318292 | Method of Forming an Embedded Memory Device - The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer. | 2015-11-05 |
20150318293 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided. | 2015-11-05 |
20150318294 | FLASH MEMORY DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate; and forming a first polysilicon layer. The method also includes forming a hard mask layer; and forming a plurality of first openings exposing the first polysilicon layer in the hard mask layer and the first polysilicon layer. Further, the method includes forming a plurality of grooves by etching the semiconductor substrate along the first openings; and forming liner oxide layers by oxidizing the first polysilicon layer. Further, the method also includes forming shallow trench isolation structures by filling the first openings; and forming second openings by removing the hard mask layer and the non oxidized first polysilicon layer. Further, the method also includes forming a tunnel oxide layer on a bottom of the second opening; and forming a floating gate on each of the tunnel oxide layers. | 2015-11-05 |
20150318295 | VERTICAL FLOATING GATE NAND WITH OFFSET DUAL CONTROL GATES - A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack. | 2015-11-05 |
20150318296 | NON-VOLATILE MEMORY DEVICES WITH VERTICALLY INTEGRATED CAPACITOR ELECTRODES - Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes. | 2015-11-05 |
20150318297 | METHOD OF SELECTIVE FILLING OF MEMORY OPENINGS - A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes providing an opening having a different sidewall material exposed on a sidewall of the opening than a bottom material exposed on a bottom of the opening, selectively forming a sacrificial material on the bottom of the opening but not on the sidewall of the opening, selectively forming a first layer on the sidewall of the opening but not on the sacrificial material located on the bottom of the opening, and selectively removing the sacrificial material to expose the bottom material on the bottom of the opening such that the first layer remains on the sidewall of the opening. | 2015-11-05 |
20150318298 | TRENCH VERTICAL NAND AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench. | 2015-11-05 |
20150318299 | SSL/GSL GATE OXIDE IN 3D VERTICAL CHANNEL NAND - A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips. | 2015-11-05 |
20150318300 | METHOD OF MAKING DAMASCENE SELECT GATE IN MEMORY DEVICE - A method of fabricating a memory device includes forming a mask over a top surface of a stack of alternating insulating material layers and control gate electrodes located over a substrate, wherein the stack has a memory opening extending vertically through the stack, a semiconductor channel extends vertically in the memory opening, and a memory film is located in the memory opening between the semiconductor channel and the plurality of control gate electrodes, and the mask covers a first portion of an upper insulating layer of the stack and exposes a second portion of the upper insulating layer adjacent to the memory opening, etching the upper insulating layer through the mask to provide a recess in the second portion of the upper insulating layer, and forming a conductive material within the recess to provide a select gate electrode adjacent to the semiconductor channel in the memory opening. | 2015-11-05 |
20150318301 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Semiconductor memory devices and methods of fabricating the same are provided. A semiconductor memory device includes stack gate structures that are spaced apart from each other in a first direction horizontal to a substrate. Each of the stack gate structures includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. Vertical channel structures penetrate the stack gate structures. A source plug line is provided between the stack gate structures. The source plug line is in contact with the substrate and extends in a second direction intersecting the first direction. The substrate being in contact with the source plug line includes a plurality of protruding regions formed along the second direction. Each of the protruding regions has a first width, and the protruding regions are spaced apart from each other by a first distance greater than the first width. | 2015-11-05 |
20150318302 | METHOD OF FABRICATING A THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure. | 2015-11-05 |
20150318303 | FIELD EFFECT TRANSISTORS INCLUDING CONTOURED CHANNELS AND PLANAR CHANNELS - Disposable gate structures and a planarization dielectric layer are formed over doped semiconductor material portions on a crystalline insulator layer. Gate cavities are formed by removing the disposable gate structures selective to the planarization dielectric layer. Doped semiconductor material portions are removed from underneath the gate cavities to provide pairs of source and drain regions separated by a gate cavity. Within a first gate cavity, a faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer, while a second gate is temporarily coated with an amorphous material layer. A contoured semiconductor region is epitaxially grown on the faceted crystalline dielectric material portion in the first gate cavity, while a planar semiconductor region is epitaxially grown in the second gate cavity. The semiconductor regions can provide at least one contoured channel region and at least one planar channel region. | 2015-11-05 |
20150318304 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product. | 2015-11-05 |
20150318305 | AN ARRAY SUBSTRATE AND A METHOD FOR MANUFACTURING THE SAME - An array substrate is disclosed. The array substrate comprises a base substrate ( | 2015-11-05 |
20150318306 | METHOD OF TRANSFERRING THIN FILM, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, METHOD OF FORMING PIXEL ELECTRODE OF LIQUID CRYSTAL DISPLAY DEVICE - A method of transferring a thin film is a method of transferring a thin film formed on a first substrate to a second substrate, the method including: allowing the first substrate to come into contact with a liquid to swell the first substrate; allowing the second substrate and the thin film to come into contact with each other via the liquid; and drying the liquid to allow the thin film to adhere to the second substrate. | 2015-11-05 |
20150318307 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 2015-11-05 |
20150318308 | LOW TEMPERATURE POLYCRYSTALLINE SILICON BACKPLANE WITH COATED APERTURE EDGES - This disclosure provides systems, methods, and apparatus for forming a display apparatus. In some implementations, a conductive material used for the formation of terminal contacts of a transistor can be also used to form a light absorbing coating over sidewalls of a plurality of apertures formed in an aperture layer of a display apparatus. In some implementations, the conductive material can be patterned such that the display apparatus also includes front facing light absorbing coating over the aperture layer. In some implementations, the front facing light absorbing coating can be electrically connected to a shutter assembly formed over the aperture layer. | 2015-11-05 |
20150318309 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND DEVICE COMPRISING THE SAME - A thin film transistor is provided. An active layer ( | 2015-11-05 |
20150318310 | Array Substrate and Method for Manufacturing the Same, and Display Device - Embodiments of the invention disclose an array substrate and a method for manufacturing the same, and a display device. The method for manufacturing an array substrate comprising: forming a gate metal layer, wherein the gate metal layer comprises gate lines; film-forming an active layer and film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after film-forming the active layer and before film-forming the signal line metal layer, the method further comprising: hollowing out a first region of the active layer through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines. | 2015-11-05 |
20150318311 | Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device - The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate includes a plurality of pixel units, each of which includes: a TFT area provided with a TFT including a gate, a gate insulation layer, an active area, a source and a drain; and a display area provided with a pixel electrode. | 2015-11-05 |
20150318312 | THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR - A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper. | 2015-11-05 |
20150318313 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE - An array substrate, comprising a display region and a GOA region. In the GOA region, a gate metal electrode, a gate insulating layer, an active layer, a transition layer, and a source-drain metal electrode are formed in sequence from bottom to top, and a via hole is provided penetrating the transition layer, the active layer and the gate insulating layer, the source-drain metal electrode is electrically connected to the gate metal electrode through the via hole; and at an edge of the via hole, there is formed an angle opening upward at edges of the transition layer and the active layer. There are further disclosed a manufacturing method of the array substrate and a display device provided with the array substrate. | 2015-11-05 |
20150318314 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer. | 2015-11-05 |
20150318315 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MAKING THE SAME - The present application provides a thin film transistor array substrate and a method for making the same. A technical solution of the present application is to divide a removable area from a planarization layer of a thin film transistor array substrate, all organic photoresist material in the removable area is entirely removed, and sealant is directly spread on the protection layer, which is easier to stick, to achieve better sealant adhesion effect. In this way, the whole structure of a TFT-LCD using the thin film transistor array substrate provided by the present application is adhered more firmly. Compared with the prior art, the method of the present application can improve the product pass rate effectively, and is simple and easy to execute. | 2015-11-05 |
20150318316 | DISPLAY SUBSTRATE AND FABRICATING METHOD THEREOF, MASK PLATE, AND MASK PLATE GROUP - The present disclosure provides a display substrate and a mask plate, the display substrate comprising a plurality of sub display substrates, each of the sub display substrates comprising a plurality of pixel units, each pixel unit comprising a pixel electrode, a common electrode and a source-drain channel, wherein, from the center of the display substrate to the edge of the display substrate, the plurality of sub display substrates are arranged from large to small according to the overlapping area of the pixel electrode and the common electrode and/or the plurality of sub display substrates are arranged from small to large according to the width to length ratio of the source-drain channel of the sub display substrate. The present disclosure can avoid electrical badness of the sub display substrates located at the edges. | 2015-11-05 |
20150318317 | THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR - A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper. | 2015-11-05 |
20150318318 | IMAGE SENSOR HAVING IMPROVED LIGHT UTILIZATION EFFICIENCY - An image sensor includes a first pixel row including a plurality of first pixels configured to sense first wavelength light, the first wavelength light having a first wavelength, a second pixel row adjacent to the first pixel row, the second pixel row including a plurality of second pixels configured to sense second wavelength light and a plurality of third pixels configured to sense third wavelength light, the plurality of second pixels and the plurality of third pixels being alternately arranged, the second wavelength light having a second wavelength and the third wavelength light having a third wavelength and a plurality of first color separation elements in the plurality of second pixels, respectively, the plurality of separation elements configured to change a spectrum distribution of incident light. | 2015-11-05 |
20150318319 | METHOD AND APPARATUS FOR REDUCING CROSSTALK IN CMOS IMAGE SENSOR - A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate having a front side and a back side, at least two pixels disposed in the first side, a shallow trench isolation disposed in the front side between the at least two pixels, and a crosstalk reduction element disposed in the back side at a location above the shallow trench isolation. The crosstalk reduction element reduces optical and electrical crosstalk and improves the image quality of the CMOS image sensor. | 2015-11-05 |
20150318320 | SOLID-STATE IMAGING DEVICES - A solid-state imaging device is provided. The solid-state imaging device includes a substrate containing a plurality of photoelectric conversion elements. A color filter layer is disposed above the photoelectric conversion elements. A light shielding layer is disposed between the color filter layer and substrate. The light-shielding layer has a plurality of first light shielding partitions extended along a first direction and a plurality of second light shielding partitions extended along a second direction perpendicular to the first direction. The first light shielding partitions have different dimensions along the second direction and the second light shielding partitions have different dimensions along the first direction. | 2015-11-05 |
20150318321 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member. | 2015-11-05 |
20150318322 | IMAGING CIRCUITRY WITH ROBUST SCRIBE LINE STRUCTURES - An image sensor wafer may be stacked on top of a digital signal processor (DSP) wafer. The image sensor wafer may include multiple image sensor dies, whereas the DSP wafer may include multiple DSP dies. The stacked wafers may be cut along scribe line regions to dice the wafers into individual components. Each image sensor die may include through-oxide vias (TOVs) that extend at least partially into a corresponding DSP die. Scribe line support structures may be formed surrounding the scribe line regions. The scribe line support structures and the TOVs may be formed during the same processing step. The TOVs can also be formed through deep trench isolation structures. | 2015-11-05 |
20150318323 | IMAGE SENSORS WITH REDUCED STACK HEIGHT - An imaging system may include an image sensor die stacked on top of a digital signal processor (DSP) die. The image sensor die may be a backside illuminated image sensor die. Through-oxide vias (TOVs) may be formed in the image sensor die and may extend at least partially into in the DSP die to facilitate communications between the image sensor die and the DSP die. Bond pad structures may be formed on the surface of the image sensor die and may be coupled to off-chip circuitry via bonding wires soldered to the bad pad structures. Color filter elements may be formed over active image sensor pixels on the image sensor die. Microlens structures may be formed over the color filter elements. An antireflective coating (ARC) liner may be simultaneously formed over the microlens structures and over the bond pad structures to passivate the bond pad structures. | 2015-11-05 |
20150318324 | SOLID-STATE IMAGING DEVICE AND CAMERA - A solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element. | 2015-11-05 |
20150318325 | System And Method For Black Coating Of Camera Cubes At Wafer Level - A method for black coating camera cubes at wafer level includes expanding the gap between individual diced camera cubes of the wafer by stretching tape securing the diced camera cubes. The method includes applying a black coating layer to the stretched camera cubes, laser trimming undesired portions of the black coating layer, and removing the undesired portions of the black coating layer. | 2015-11-05 |
20150318326 | Wafer-Level Bonding Method For Camera Fabrication - A wafer-level method for fabricating a plurality of cameras includes modifying an image sensor wafer to reduce risk of the image sensor wafer warping, and bonding the image sensor wafer to a lens wafer to form a composite wafer that includes the plurality of cameras. A wafer-level method for fabricating a plurality of cameras includes bonding an image sensor wafer to a lens wafer, using a pressure sensitive adhesive, to form a composite wafer that includes the plurality of cameras. | 2015-11-05 |
20150318327 | BACKSIDE ILLUMINATED COLOR IMAGE SENSORS AND METHODS FOR MANUFACTURING THE SAME - A method for manufacturing a backside illuminated color image sensor includes (a) modifying the frontside of an image sensor wafer, having pixel arrays, to produce electrical connections to the pixel arrays, wherein the electrical connections extend depth-wise into the image sensor wafer from the frontside, and (b) modifying the backside of the image sensor wafer to expose the electrical connections. | 2015-11-05 |
20150318328 | LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME - A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. | 2015-11-05 |
20150318329 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a word line region is formed, and a barrier metal layer arranged on the word line region and causing a Schottky junction. The barrier metal layer includes a first nitride material, in which a first material is nitrified, and a second nitride material, in which a second material is nitrified. The barrier metal layer is formed of a mixture of the first nitride material and the second nitride material. At least one of the first material or the second material is rich in a metal used to form the first nitride material or the second nitride material. | 2015-11-05 |
20150318330 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a word line region is formed, and a barrier metal layer arranged on the word line region and causing a Schottky junction. The barrier metal layer includes a first nitride material, in which a first material is nitrified, and a second nitride material, in which a second material is nitrified. The barrier metal layer is formed of a mixture of the first nitride material and the second nitride material. At least one of the first material or the second material is rich in a metal used to form the first nitride material or the second nitride material. | 2015-11-05 |
20150318331 | METHOD, SYSTEM AND DEVICE FOR RECESSED CONTACT IN MEMORY ARRAY - Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device. | 2015-11-05 |
20150318332 | MULTIFUNCTIONAL ZINC OXIDE NANO-STRUCTURE-BASED CIRCUIT BUILDING BLOCKS FOR RE-CONFIGURABLE ELECTRONICS AND OPTOELECTRONICS - A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed. | 2015-11-05 |
20150318333 | INTEGRATIVE RESISTIVE MEMORY IN BACKEND METAL LAYERS - Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries. | 2015-11-05 |
20150318334 | ORGANIC LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting device utilizing the micro-cavity effect in the RGB subpixel regions while suppressing the micro-cavity effect in the white subpixel region is provided. The organic light emitting device includes a lower substrate, an anode formed on the lower substrate, an organic emission layer formed on the anode, a cathode formed on the organic emission layer, and a reflection decreasing layer formed on at least a portion of the cathode for reducing reflection of the light emitted from the organic emission layer by the cathode to reduce the micro-cavity effect. Such a selective use of the micro-cavity effect in the organic light emitting device improves the color accuracy, the luminance efficiency and the lifespan of the top emission type organic light emitting device. | 2015-11-05 |
20150318335 | Light-Emitting Element, Light-Emitting Device, Lighting Device, and Electronic Appliance - An inverted-structure light-emitting element is provided. One embodiment of the invention disclosed in this specification is a light-emitting element including a cathode, a layer serving as a buffer over the cathode, an electron-injection layer over the layer serving as a buffer, a light-emitting layer over the electron-injection layer, and an anode over the light-emitting layer. The electron-injection layer includes an alkali metal or an alkaline earth metal. The layer serving as a buffer includes an electron-transport material. In the inverted-structure light-emitting element, contact of the alkali metal or alkaline earth metal included in a material of the electron-injection layer with the already formed cathode increases the driving voltage of an EL element and reduces emission efficiency. This problem becomes prominent particularly when the cathode includes an oxide conductive film. To prevent this, the layer serving as a buffer is provided between the cathode and the electron-injection layer. | 2015-11-05 |
20150318336 | DISPLAY MODULE - An organic display device includes a pixel driving circuit having a TFT connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the TFT. The first electrode is connected to the TFT through a contact hole in the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner wall having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over pixels. | 2015-11-05 |
20150318337 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display including: a substrate; a semiconductor layer disposed on the substrate and including a switching semiconductor layer and a driving semiconductor layer connected to the switching semiconductor layer; a first gate insulating layer disposed on the semiconductor layer; a switching gate electrode and a driving gate electrode disposed on the first gate insulating layer and respectively overlapping with the switching semiconductor layer and the driving semiconductor layer; a second gate insulating layer disposed on the switching gate electrode and the driving gate electrode; a driving voltage line configured to transmit a driving voltage and disposed on the second gate insulating layer; an interlayer insulating layer disposed on the driving voltage line and the second gate insulating layer; and a data line configured to transmit a data signal and disposed on the interlayer insulating layer. | 2015-11-05 |
20150318338 | METHOD OF MANUFACTURING CAPACITOR, METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE CAPACITOR, AND ORGANIC LIGHT EMITTING DISPLAY DEVICE MANUFACTURED BY USING THE METHOD - A method of manufacturing an organic light emitting display device includes: providing a capacitor on a substrate; providing a protection layer on the capacitor; providing an organic light emitting diode on the protection layer; and providing an encapsulation layer which encapsulates the organic light emitting diode. The providing the capacitor includes: providing a bottom electrode including an oxide semiconductor, on the substrate; providing an insulation layer on the substrate and overlapping the bottom electrode; annealing the bottom electrode to increase a carrier density of the bottom electrode; and providing an intermediate electrode on the insulation layer and overlapping the bottom electrode. | 2015-11-05 |
20150318339 | LIGHT-EMITTING DEVICE AND INPUT/OUTPUT DEVICE - To provide a light-emitting device or an input/output device with little unevenness in display luminance or high reliability and to provide an input/output device with high detection sensitivity, a light-emitting device is configured to include a first substrate, a light-emitting element over the first substrate, a first conductive layer over the light-emitting element, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, and a second substrate over the second conductive layer. The light-emitting element includes a first electrode over the first substrate, a layer containing a light-emitting organic compound over the first electrode, and a second electrode over the layer containing a light-emitting organic compound. The second electrode is electrically connected to the first and second conductive layers. The first conductive layer and the second electrode transmit light emitted from the light-emitting element. The resistance of the second conductive layer is lower than that of the second electrode. | 2015-11-05 |
20150318340 | INTEGRATED THINFILM RESISTOR AND MIM CAPACITOR WITH A LOW SERIAL RESISTANCE - An electronic device comprising a semiconductor structure having a back end capacitor and a back end thin film resistor and a method of manufacturing the same. The semiconductor structure includes a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. The bottom plate and the resistor body are laterally spaced apart portions of the same thin film layer. The bottom plate further includes a conductive layer overlying the thin film layer. A second dielectric layer is disposed on the conductive layer of the bottom plate of the capacitor. A top plate of the capacitor is disposed on the second dielectric layer. | 2015-11-05 |
20150318341 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 2015-11-05 |
20150318342 | HIGH BREAKDOWN VOLTAGE METAL-INSULATOR-METAL CAPACITOR - A high breakdown voltage metal-insulator-metal capacitor for compound semiconductor integrated circuit comprises a substrate, an isolation layer, a first metal layer, a dielectric layer, an adhesion layer and a second metal layer. The dielectric layer is formed by alternately stacking plural HfO | 2015-11-05 |
20150318343 | INSULATOR, CAPACITOR WITH THE SAME AND FABRICATION METHOD THEREOF, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a multilayer insulator, a metal-insulator-metal (MIM) capacitor with the same, and a fabricating method thereof. The capacitor includes: a first electrode; an insulator disposed on the first electrode, the insulator including: a laminate structure in which an aluminum oxide (Al | 2015-11-05 |
20150318344 | MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES - A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond. | 2015-11-05 |
20150318345 | SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING - In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting. | 2015-11-05 |
20150318346 | SEMICONDUCTOR DEVICE WITH VOLTAGE-SUSTAINING REGION CONSTRUCTED BY SEMICONDUCTOR AND INSULATOR CONTAINING CONDUCTIVE REGIONS - A semiconductor device has at least a cell between two opposite main surfaces. Each cell has a first device feature region contacted with the first main surface and a second device feature region contacted with the second main surface. There is a voltage-sustaining region between the first device feature region and the second device feature region, which includes at least a semiconductor region and an insulator region containing conductive region(s). The semiconductor region and the insulator region contact directly with each other. The structure of such voltage-sustaining region can not only be used to implement high-voltage devices, but further be used as a junction edge technique of high-voltage devices. | 2015-11-05 |
20150318347 | Semiconductor Device with a Field Ring Edge Termination Structure and a Separation Trench Arranged Between Different Field Rings - A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region. | 2015-11-05 |
20150318348 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers. | 2015-11-05 |
20150318349 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer. | 2015-11-05 |
20150318350 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern. | 2015-11-05 |
20150318351 | MULTIPLE EPITAXIAL HEAD RAISED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures. | 2015-11-05 |
20150318352 | NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS - A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing. | 2015-11-05 |
20150318353 | GALLIUM NITRIDE POWER DEVICES USING ISLAND TOPOGRAPHY - A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes. | 2015-11-05 |
20150318354 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin. | 2015-11-05 |
20150318355 | METHODS OF FORMING DEFECT-FREE SRB ONTO LATTICE-MISMATCHED SUBSTRATES AND DEFECT-FREE FINS ON INSULATORS - A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures. | 2015-11-05 |
20150318356 | METHOD AND ARRANGEMENT FOR REDUCING CONTACT RESISTANCE OF TWO-DIMENSIONAL CRYSTAL MATERIAL - A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing. | 2015-11-05 |
20150318357 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface of the silicon carbide semiconductor layer; a Schottky electrode formed on the surface of the silicon carbide semiconductor layer on an inner periphery side relative to the field insulating film, the Schottky electrode being formed to overlap onto the field insulating film; a front-surface electrode that covers the Schottky electrode and extends on the field insulating film beyond a peripheral edge of the Schottky electrode; and a terminal well region of a second conductivity type that is formed to be in contact with a part of the Schottky electrode in an upper part of the silicon carbide semiconductor layer and extends in the silicon carbide semiconductor layer on an outer periphery side relative to a peripheral edge of the front-surface electrode. | 2015-11-05 |
20150318358 | Semiconductor Devices Including Polar Insulation Layer Capped by Non-Polar Insulation Layer - Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer. | 2015-11-05 |
20150318359 | SEMICONDUCTOR FILM, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, MODULE, AND ELECTRONIC DEVICE - A semiconductor device with favorable electrical characteristics is provided. In an oxide semiconductor film, a plurality of electron diffraction patterns are observed in such a manner that a surface over which the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm while the position of the film and the position of the electron beam are relatively moved. The electron diffraction patterns include 50 or more electron diffraction patterns observed in different areas. The sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%. The first electron diffraction patterns account for 50% or more. The first electron diffraction pattern includes observation points that are not symmetry or observation points disposed in a circular pattern. The second electron diffraction pattern includes observation points corresponding to the vertices of a hexagon. | 2015-11-05 |
20150318360 | REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICES - A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals. | 2015-11-05 |
20150318361 | Method for Forming a Transistor Device having a Field Electrode - A method for forming a transistor device includes forming a field electrode arrangement by forming a trench in a first surface of a semiconductor body, forming a protection layer on sidewalls of the trench in an upper trench section, forming a dielectric layer on a bottom of the trench and on sidewall sections uncovered by the protection layer, and forming a field electrode at least on the dielectric layer. The method further includes forming a gate electrode and a gate electrode dielectric horizontally spaced apart from the field electrode arrangement with respect to the first surface, forming a body region adjacent the gate electrode and dielectrically insulated from the gate electrode by the gate dielectric, and forming a source region in the body region. | 2015-11-05 |
20150318362 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor and manufacturing method thereof, an array substrate ( | 2015-11-05 |
20150318363 | TRANSISTOR AND METHOD OF FABRICATING THE SAME - Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar. | 2015-11-05 |
20150318364 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - According to a semiconductor structure fabrication method, a semiconductor substrate having gate structures is provided. Sidewalls of the gate structures may be covered by a spacer layer. An epitaxy process is performed to form a semiconductor epitaxial material layer covering the gate structures, the spacer layer, and the semiconductor substrate. Then, an etching process is performed to form a first semiconductor epitaxial layer on the semiconductor substrate at the two sides of the gate structures. Further, a selective epitaxy process is performed by using a deposition gas and an etching gas, forming a second semiconductor epitaxial layer. The formed second semiconductor epitaxial layer may repair or compensate the first semiconductor epitaxial layer along the horizontal direction. The epitaxy process, the etching process, and the selective epitaxy process are repeated successively to form elevated source/drain regions. The formed elevated source/drain regions may have a flat top surface without any angles. | 2015-11-05 |
20150318365 | TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD - A transistor device may include a substrate that has a recess and a substrate surface, wherein the recess is recessed with respect to the substrate surface. The transistor device may further include a source and a drain that overlap the substrate. The transistor device may further include a gate structure that has a first gate structure portion and a second gate structure portion, wherein the first gate structure portion is positioned inside the recess, and wherein the second gate structure portion is connected to the first gate structure and is positioned outside the first recess. | 2015-11-05 |
20150318366 | FABRICATING METHOD OF TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate. | 2015-11-05 |
20150318367 | Controlling Gate Formation for High Density Cell Layout - Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions. | 2015-11-05 |
20150318368 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened. | 2015-11-05 |
20150318369 | CONDUCTIVE NANOPARTICLES - Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements. | 2015-11-05 |
20150318370 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer. | 2015-11-05 |
20150318371 | SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS - Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process. | 2015-11-05 |
20150318372 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film includes an AlON layer with a nitrogen composition of 5% to 40%. A semiconductor device is thereby provided with which electron trapping in the gate insulating film can be reduced and shifting of a threshold voltage V | 2015-11-05 |
20150318373 | CURRENT APERTURE DIODE AND METHOD OF FABRICATING THE SAME - A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25. | 2015-11-05 |
20150318374 | ENHANCEMENT MODE III-NITRIDE DEVICE AND METHOD FOR MANUFACTURING THEREOF - Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts. | 2015-11-05 |
20150318375 | SELF-ALIGNED STRUCTURES AND METHODS FOR ASYMMETRIC GAN TRANSISTORS & ENHANCEMENT MODE OPERATION - Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation. | 2015-11-05 |
20150318376 | SEMICONDUCTOR DEVICE HAVING IMPROVED HEAT DISSIPATION - A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias. | 2015-11-05 |
20150318377 | FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION - A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure. | 2015-11-05 |
20150318378 | LOW LEAKAGE, HIGH FREQUENCY DEVICES - Low leakage, high frequency devices and methods of manufacture are disclosed. The method of forming a device includes implanting a lateral diffusion drain implant in a substrate by a blanket implantation process. The method further includes forming a self-aligned tapered gate structure on the lateral diffusion drain implant. The method further includes forming a halo implant in the lateral diffusion drain implant, adjacent to the self-aligned tapered gate structure and at least partially under a source region of the self-aligned tapered gate structure. | 2015-11-05 |
20150318379 | SUPER-JUNCTION STRUCTURES HAVING IMPLANTED REGIONS SURROUNDING AN N EPITAXIAL LAYER IN DEEP TRENCH - A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier. | 2015-11-05 |
20150318380 | Thin Film Transistor - Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole. | 2015-11-05 |
20150318381 | Method for FinFET Device - Provided is a method of forming a fin field effect transistor (FinFET). The method includes forming a fin on a substrate, the fin having a channel region therein. The method further includes forming a gate structure engaging the fin adjacent to the channel region and forming a spacer on sidewalls of the gate structure. The method further includes forming two recesses in the fin adjacent to the spacer and on opposite sides of the gate structure and epitaxially growing a solid phase diffusion (SPD) layer in the two recesses, the SPD layer containing a high concentration of a dopant. The method further includes performing an annealing process thereby diffusing the dopant into the fin underneath the spacer and forming lightly doped source/drain (LDD) regions therein. The LDD regions have substantially uniform dopant concentration on top and sidewalls of the fin. | 2015-11-05 |
20150318382 | Methods for Forming Semiconductor Regions in Trenches - A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6. | 2015-11-05 |
20150318383 | AMORPHOUS OXIDE THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY PANEL - Embodiments of the disclosed technology provide an amorphous oxide thin film transistor (TFT), a method for preparing an amorphous oxide TFT, and a display panel. The amorphous oxide thin film transistor includes: a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode and a drain electrode. The semiconductor active layer comprises a channel layer and an ohmic contact layer, and the channel layer has a greater content of oxygen than the ohmic contact layer; the channel layer contacts the gate insulating layer, and the ohmic contact layer comprises two separated ohmic contact regions, one of which contacts the source electrode and the other of which contacts the drain electrode. | 2015-11-05 |
20150318384 | Bipolar Transistor - A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers. | 2015-11-05 |
20150318385 | SEMICONDUCTOR DEVICE - A first semiconductor device presented by the specification includes a semiconductor substrate that includes an anode region and a cathode region. The anode region includes a first conductivity type first region having a maximum impurity concentration of the first conductivity type at a position that is at a first depth from a surface of the semiconductor substrate and a first conductivity type second region having a maximum impurity concentration of the first conductivity type at a position that is at a second depth, and on a surface side of the semiconductor substrate than the first depth, and a third region provided between the first region and the second region, and having an impurity concentration of the first conductivity type that is equal to or less than 1/10 (one-tenth) of a impurity concentration of the surface of the semiconductor substrate. | 2015-11-05 |
20150318386 | SEMICONDUCTOR DEVICE - A semiconductor device includes stripe-shaped gate trench formed in one major surface of n-type drift layer, gate trench including gate polysilicon formed therein, and gate polysilicon being connected to a gate electrode; p-type base layer formed selectively in mesa region between adjacent gate trenches, p-type base layer including n-type emitter layer and connected to emitter electrode; one or more dummy trenches formed between p-type base layers adjoining to each other in the extending direction of gate trenches; and electrically conductive dummy polysilicon formed on an inner side wall of dummy trench with gate oxide film interposed between dummy polysilicon and dummy trench, dummy polysilicon being spaced apart from gate polysilicon. Dummy polysilicon may be connected to emitter electrode. The structure according to the invention facilitates providing an insulated-gate semiconductor device, the Miller capacitance of which is small, even when the voltage applied between the collector and emitter is low. | 2015-11-05 |
20150318387 | Sidewall Passivation for HEMT Devices - Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material. | 2015-11-05 |
20150318388 | DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate. | 2015-11-05 |
20150318389 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time. | 2015-11-05 |
20150318390 | FINFET AND METHOD OF MANUFACTURING THE SAME - A FinFET and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin. The method further includes forming a first region, the first region being one of a source region and a drain region. The method further includes forming a sacrificial spacer. The method further includes forming a second region with the sacrificial spacer as a mask, the second region being the other one of the source region and the drain region. The method further includes removing the sacrificial spacer. The method further includes replacing the sacrificial spacer with a gate stack comprising a gate conductor and a gate dielectric that separates the gate conductor from the semiconductor fin. | 2015-11-05 |