44th week of 2014 patent applcation highlights part 19 |
Patent application number | Title | Published |
20140319621 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 2014-10-30 |
20140319622 | SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME - A semiconductor device is disclosed. An isolation structure is formed in a substrate to define an active region of the substrate, wherein the active region has a field plate region. A gate dielectric layer is formed on the substrate outside of the field plate region. A step gate dielectric structure is formed on the substrate corresponding to the field plate region, wherein the step gate dielectric structure has a thickness greater than that of the gate dielectric layer and less than that of the isolation structure. A method for forming a semiconductor device is also disclosed. | 2014-10-30 |
20140319623 | METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS - Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode. | 2014-10-30 |
20140319624 | METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS - A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer. | 2014-10-30 |
20140319625 | TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The methods also includes forming a threshold-adjusting layer doped with a certain type of threshold-adjusting ions to adjust the threshold voltage of the transistor on the semiconductor substrate in the trench; and forming a carrier drifting layer on the threshold-adjusting layer. Further the method includes forming a gate structure on the carrier drifting layer corresponding to the trench. | 2014-10-30 |
20140319626 | Metal Gate Stack Having TiAlCN as Work Function Layer and/or Blocking/Wetting Layer - A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer. | 2014-10-30 |
20140319627 | CHIP PACKAGE AND A METHOD OF MANUFACTURING THE SAME - In various embodiments, a chip package is provided. The chip package may include at least one chip having a plurality of pressure sensor regions and encapsulation material encapsulating the chip. | 2014-10-30 |
20140319628 | PHYSICAL QUANTITY DETECTION DEVICE AND PHYSICAL QUANTITY DETECTOR - A physical quantity detection device includes a glass substrate, a substrate including a physical quantity detection part and bonded to a first surface of the glass substrate with a hermetically sealed space being formed inside the substrate, and a function membrane formed on a second surface of the glass substrate opposite to the first surface. The function membrane prevents the second surface of the glass substrate from coming into contact with moisture in the atmosphere. | 2014-10-30 |
20140319629 | COMPONENT HAVING A MICROMECHANICAL MICROPHONE PATTERN - Measures are provided for increasing the resistance to compression of a component having a micromechanical microphone pattern. In particular, the robustness of the microphone pattern to highly dynamic pressure fluctuations is to be increased, without the microphone sensitivity, i.e. the microphone performance, being impaired. The microphone pattern of such a component is implemented in a layer construction on a semiconductor substrate and includes at least one acoustically active diaphragm, which spans a sound hole on the substrate backside, and a stationary acoustically penetrable counterelement having through hole openings, which is situated above/below the diaphragm in the layer construction. At least one outflow channel is developed which makes possible a rapid pressure equalization between the two sides of the diaphragm. In addition, at least one controllable closing element is provided, with which the at least one outflow channel is optionally able to be opened or closed. | 2014-10-30 |
20140319630 | WAFER LEVEL ASSEMBLY OF A MEMS SENSOR DEVICE AND RELATED MEMS SENSOR DEVICE - An assembly of a MEMS sensor device envisages: a first die, integrating a micromechanical detection structure and having an external main face; a second die, integrating an electronic circuit operatively coupled to the micromechanical detection structure, electrically and mechanically coupled to the first die and having a respective external main face. Both of the external main faces of the first die and of the second die are set in direct contact with an environment external to the assembly, without interposition of a package. | 2014-10-30 |
20140319631 | MEMS Integrated Pressure Sensor Devices having Isotropic Cavities and Methods of Forming Same - A method embodiment includes providing a MEMS wafer comprising an oxide layer, a MEMS substrate, a polysilicon layer. A carrier wafer comprising a first cavity formed using isotropic etching is bonded to the MEMS, wherein the first cavity is aligned with an exposed first portion of the polysilicon layer. The MEMS substrate is patterned, and portions of the sacrificial oxide layer are removed to form a first and second MEMS structure. A cap wafer including a second cavity is bonded to the MEMS wafer, wherein the bonding creates a first sealed cavity including the second cavity aligned to the first MEMS structure, and wherein the second MEMS structure is disposed between a second portion of the polysilicon layer and the cap wafer. Portions of the carrier wafer are removed so that first cavity acts as a channel to ambient pressure for the first MEMS structure. | 2014-10-30 |
20140319632 | PERPENDICULAR STT-MRAM HAVING PERMEABLE DIELECTRIC LAYERS - A perpendicular STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having permeable dielectric layer. As an external perpendicular magnetic field exists, the permeable dielectric layers have capability to absorb and channel most magnetic flux surrounding the MTJ element instead of penetrate through the MTJ element. Thus, magnetization of a recording layer can be less affected by the stray field during either writing or reading, standby operation | 2014-10-30 |
20140319633 | MAGNETIC MEMORY ELEMENT AND MEMORY APPARATUS HAVING MULTIPLE MAGNETIZATION DIRECTIONS - A memory element includes a layered structure: a memory layer having a magnetization direction changed depending on information, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, including a first ferromagnetic layer having a magnetization direction that is inclined from a direction perpendicular to a film face, a bonding layer laminated on the first ferromagnetic layer, and a second ferromagnetic layer laminated on the bonding layer and bonded to the first ferromagnetic layer via the bonding layer, having a magnetization direction that is inclined from the direction perpendicular to the film face, a magnetization-fixed layer having a fixed magnetization direction, an intermediate layer that is provided between the memory layer and the magnetization-fixed layer, and is contacted with the first ferromagnetic layer, and a cap layer that is contacted with the second ferromagnetic layer. | 2014-10-30 |
20140319634 | High Density Nonvolatile Memory - One embodiment of a nonvolatile memory cell comprises a substrate having a surface, a bidirectional current switch comprising a first electrode, a second electrode, and a semiconductor layer disposed between the first and second electrodes, and a magnetoresistive element having a direct contact with the bidirectional current switch and comprising a free ferromagnetic layer having a reversible magnetization direction, a pinned ferromagnetic layer having a fixed magnetization direction, and a tunnel barrier layer disposed between the free and pinned ferromagnetic layers, wherein the magnetization direction of the free ferromagnetic layer is reversed by a bidirectional spin polarized current running through the magnetoresitive element in a direction perpendicular to the substrate surface, and wherein a magnitude of the spin polarized current is controlled by the bidirectional current switch. Other embodiments are described and shown. | 2014-10-30 |
20140319635 | SEMICONDUCTOR DETECTOR - The invention provides a semiconductor detector, and the semiconductor detector comprises a semiconductor crystal, a cathode, an anode and at least one ladder electrode; the semiconductor crystal comprises a top surface, a bottom surface and at least one side; the cathode, the anode and the ladder electrode are conductive thin films deposited on a surface of the semiconductor crystal; the cathode is disposed on the bottom surface of the semiconductor crystal, the anode is disposed on the top surface of the semiconductor crystal, the ladder electrode is disposed on the at least one side of the semiconductor crystal; and the ladder electrode comprises a plurality of sub-electrodes. As compared to the prior art, the semiconductor detector can improve the energy resolution. | 2014-10-30 |
20140319636 | Motion Sensing Device - A motion sensing device for sensing infrared rays includes a substrate; an optical module, including a first spacer layer, coupled to the substrate; a first glass layer, formed on the first spacer layer; a second spacer layer, formed on the first glass layer; a second glass layer, formed on the second spacer layer; a third spacer layer, formed on the second glass layer; a first lens, bonding on a first side of the second glass layer; and a second layer, bonding on a second side relative to the first side of the second glass layer; and a coating layer, covered on the optical layer for shielding the infrared rays, wherein the coating layer does not cover the first lens. | 2014-10-30 |
20140319637 | PHOTODETECTOR - A photodetector | 2014-10-30 |
20140319638 | AVALANCHE PHOTODIODE - According to one aspect, there is provided an avalanche photodiode comprising a first semiconductor layer that absorbs photons of a first wavelength range and having a first energy bandgap; a second semiconductor layer that absorbs photons of a second wavelength range and having a second energy bandgap, the second energy bandgap being different from the first energy bandgap; and a control layer between the first semiconductor layer and the second semiconductor layer, the control layer having a third energy bandgap engineered to suppress carriers created from dark current. | 2014-10-30 |
20140319639 | NEGATIVELY CHARGED LAYER TO REDUCE IMAGE MEMORY EFFECT - An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the first polarity charge layer. | 2014-10-30 |
20140319640 | Photodiode for Topside and Backside Illumination - A photodiode structure provides light sensitivity to both front side and backside illumination. The photodiode may include a deep N well (DNW) that extends over a Psub substrate. The DNW may be discontinuous, or may extend continuously over the Psub substrate. Additional DNW area under the diode area proportionally increases the sensitivity to backside illumination. In addition, the photodiode may use a lightly doped anode region to increase the depletion region between the anode region and the deep N well. The anode region may be lightly doped Psub, as opposed to Pwell, in order to increase the topside light sensitive area percentage of the total area. One highly sensitive implementation uses Psub doping in the anode region, and a deep N well under the entire diode. This provides maximum areal density of the diode intrinsic regions nearest the wafer backside. | 2014-10-30 |
20140319641 | Radiation Conversion Device and Method of Manufacturing a Radiation Conversion Device - A radiation conversion device such as a photovoltaic cell, a photodiode or a semiconductor radiation detection device, includes a semiconductor portion with first compensation zones of a first conductivity type and a base portion that separates the first compensation zones from each other. The first compensations zones are arranged in pillar structures. Each pillar structure includes spatially separated first compensation zones and extends in a vertical direction with respect to a main surface of the semiconductor portion. Between neighboring ones of the pillar structures the base portion includes second compensation zones of a second conductivity type, which is complementary to the first conductivity type. The radiation conversion device combines high radiation hardness with cost effective manufacturing. | 2014-10-30 |
20140319642 | Wavelength Sensitive Sensor Photodiodes - The present invention is directed toward a dual junction photodiode semiconductor devices with improved wavelength sensitivity. The photodiode employs a high quality n-type layer with relatively lower doping concentration and enables high minority carrier lifetime and high quantum efficiency with improved responsivity at multiple wavelengths. In one embodiment, the photodiode comprises a semiconductor substrate of a first conductivity type, a first impurity region of a second conductivity type formed epitaxially in the semiconductor substrate, a second impurity region of the first conductivity type shallowly formed in the epitaxially formed first impurity region, a first PN junction formed between the epitaxially formed first impurity region and the second impurity region, a second PN junction formed between the semiconductor substrate and the epitaxially formed first impurity region, and at least one passivated V-groove etched into the epitaxially formed first impurity region and the semiconductor substrate. | 2014-10-30 |
20140319643 | SEMICONDUCTOR DEVICE PROVIDED WITH PHOTODIODE, MANUFACTURING METHOD THEREOF, AND OPTICAL DISC DEVICE - A semiconductor device includes: a P-type semiconductor substrate; a first P-type semiconductor layer formed on the P-type semiconductor substrate; a second P-type semiconductor layer formed on the first P-type semiconductor layer and having a lower P-type impurity concentration than the first P-type semiconductor layer; an N-type semiconductor layer, which will form a cathode region, formed on the second P-type semiconductor layer; a first P-type diffusion layer formed by diffusing a P-type impurity in a partial region of the second P-type semiconductor layer; a second P-type diffusion layer formed by diffusing a P-type impurity in the second P-type semiconductor layer so as to be present adjacently beneath the first P-type diffusion layer at a lower P-type impurity concentration than the first P-type diffusion layer; and a photodiode formed in such a manner that the N-type semiconductor layer and the first P-type diffusion layer are isolated from each other. | 2014-10-30 |
20140319644 | SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE | 2014-10-30 |
20140319645 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure. | 2014-10-30 |
20140319646 | JUNCTION TERMINATION STRUCTURES INCLUDING GUARD RING EXTENSIONS AND METHODS OF FABRICATING ELECTRONIC DEVICES INCORPORATING SAME - An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed. | 2014-10-30 |
20140319647 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL AMPLIFIER AND METHOD OF ARRANGING THE SAME - A semiconductor integrated circuit comprises: a transistor region having a center line; a first block arranged in one side of the center line of the transistor region, and comprising a plurality of first and second groups each having a plurality of first and second segment transistors constituting first and second transistors of a differential amplifier; and a second block arranged in the other side of the center line, and having an arrangement corresponding to the arrangement of the first and second groups of the first block. | 2014-10-30 |
20140319648 | INTEGRATED CIRCUIT ON SOI COMPRISING A TRANSISTOR PROTECTING FROM ELECTROSTATIC DISCHARGES - An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well. | 2014-10-30 |
20140319649 | Lithium Battery, Method for Manufacturing a Lithium Battery, Integrated Circuit and Method of Manufacturing an Integrated Circuit - A lithium battery includes a cathode, an anode including a component made of silicon, a separator element disposed between the cathode and the anode, an electrolyte, and a substrate. The anode is disposed over the substrate or the anode is integrally formed with the substrate. | 2014-10-30 |
20140319650 | PROGRAMMABLE ELECTRICAL FUSE - An method and structure of forming an electronic fuse. The method including forming a first metal line and a second metal line in a first interconnect level, wherein the first metal line is electrically insulated form the second metal line, and forming a via in a second interconnect level above the first interconnect level, the via electrically and physically connecting the first metal line with the second metal line. The via may create a sub-lithographic contact with the underlying metal line, thus increasing current density and probability of failure at a specific location. | 2014-10-30 |
20140319651 | Electrical Fuse Structure and Method of Formation - A fuse device having contacts configured to reduce electro-migration is disclosed. In some exemplary embodiments, the fuse structure includes an anode disposed at a first end and a cathode disposed at a second end. A fuse link extends between and contacts the anode and the cathode. A boundary between the fuse link and the cathode has a center point, and each connector of a plurality of cathode connectors has a center point that is an equal distance from the center point of the boundary between the fuse link and the cathode. In some such embodiments, each connector of the plurality of cathode connectors is a different size than an anode connector, whereas in some such embodiments, each connector of the plurality of cathode connectors is substantially a same size as the anode connector along at least one axis. | 2014-10-30 |
20140319652 | HIGH QUALITY FACTOR FILTER IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) INTEGRATED DEVICE - Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die. | 2014-10-30 |
20140319653 | Integrated Switchable Capacitive Device - An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value. | 2014-10-30 |
20140319654 | FLEXIBLE AND ON WAFER HYBRID PLASMA-SEMICONDUCTOR TRANSISTORS - Preferred embodiment flexible and on wafer hybrid plasma semiconductor devices have at least one active solid state semiconductor region; and a plasma generated in proximity to the active solid state semiconductor region(s). A preferred device is a hybrid plasma semiconductor device having base, emitting and microcavity collector regions formed on a single side of a device layer. Visible or ultraviolet light is emitted during operation by plasma collectors in the array. In preferred embodiments, individual PBJTs in the array serve as sub-pixels of a full-color display. | 2014-10-30 |
20140319655 | METHOD FOR COUPLING A GRAPHENE LAYER AND A SUBSTRATE AND DEVICE COMPRISING THE GRAPHENE/SUBSTRATE STRUCTURE OBTAINED - The present disclosure regards a method for coupling a graphene layer to a substrate having at least one hydrophilic surface, the method comprising the steps of providing the substrate having at least one hydrophilic surface, depositing on the hydrophilic surface a layer of a solvent selected in the group constituted by acetone, ethyl lactate, isopropyl alcohol, methylethyl ketone and mixtures thereof and depositing on the solvent layer a graphene layer. It moreover regards an electronic device comprising the graphene/substrate structure obtained. | 2014-10-30 |
20140319656 | METHOD AND SYSTEM FOR HEIGHT REGISTRATION DURING CHIP BONDING - A method of fabricating a composite semiconductor structure is provided. Pedestals are formed in a recess of a first substrate. A second substrate is then placed within the recess in contact with the pedestals. The pedestals have a predetermined height so that a device layer within the second substrate aligns with a waveguide of the first substrate, where the waveguide extends from an inner wall of the recess. | 2014-10-30 |
20140319657 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate ( | 2014-10-30 |
20140319658 | CHARGE PUMP CAPACITOR ASSEMBLY WITH SILICON ETCHING - Charge pump capacitor assemblies and methods of manufacturing the same. One charge pump capacitor assembly includes a charge pump capacitor and a silicon substrate. The charge pump capacitor includes: a silicon-based charge pump capacitor oxide layer, a first terminal on a first side of the silicon-based charge pump layer, a second terminal on a second side of the silicon-based charge pump capacitor oxide layer opposite the first side, and a field oxide layer mounted adjacent the second terminal. The charge pump capacitor is coupled to the silicon substrate. The silicon substrate is etched to reduce contact between the silicon substrate and the field oxide layer. | 2014-10-30 |
20140319659 | RESIST UNDERLAYER COMPOSITION, METHOD OF FORMING PATTERNS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERNS - A resist underlayer composition, a method of forming patterns, and semiconductor integrated circuit device, the composition including a solvent; and a compound including a moiety represented by the following Chemical Formula 1: | 2014-10-30 |
20140319660 | SOLID-STATE ELECTRONIC DEVICE - A solid-state electronic device according to the present invention includes: an oxide layer (possibly containing inevitable impurities) that is formed by heating, in an atmosphere containing oxygen, a precursor layer obtained from a precursor solution as a start material including both a precursor containing bismuth (Bi) and a precursor containing niobium (Nb) as solutes, the oxide layer consisting of the bismuth (Bi) and the niobium (Nb); wherein the oxide layer is formed by heating at a heating temperature from 520° C. to 650° C. | 2014-10-30 |
20140319661 | Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer - A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure. | 2014-10-30 |
20140319662 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package which may include a package substrate which includes a power supply region and an interconnection region around the power supply region, a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate, and at least one semiconductor chip mounted on the package substrate, the semiconductor chip includes a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals. | 2014-10-30 |
20140319663 | LEAD FRAME, METHOD FOR MANUFACTURING LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region. | 2014-10-30 |
20140319664 | QUAD FLAT NO-LEAD (QFN) PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad. | 2014-10-30 |
20140319665 | Power Semiconductor Package - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 2014-10-30 |
20140319666 | LEAD FRAME AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THE SAME - The present invention provides a lead frame having excellent solder wettability and solderability, that is well-bonded to a copper wire, and manufactured with low cost, and a semiconductor package manufactured by using the same. The lead frame includes: a base material; a first metal layer formed on at least one surface of the base material, the first metal layer comprising nickel; a second metal layer formed on a surface of the first metal layer, the second metal layer comprising palladium; and a third metal layer formed on a surface of the second metal layer, the third metal layer comprising silver. | 2014-10-30 |
20140319667 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A semiconductor apparatus includes: a package substrate on which a semiconductor device is disposed; a mounting board over which the package substrate is mounted; a first restraint that penetrates through the mounting board and the package substrate, and restrains deformation of the mounting board and the package substrate in a direction in which the mounting board and the package substrate are separated from each other; and a second restraint that is disposed between the mounting board and the package substrate, and restrains deformation of the mounting board and the package substrate in a direction in which the mounting board and the package substrate are closer to each other. | 2014-10-30 |
20140319668 | HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE - A package on package (PoP) structure is disclosed. The PoP structure comprises a top package and a bottom package disposed thereunder. The top package comprises a first substrate and a first die mounted onto the first substrate. At least one electrically floating pad is disposed on a lower surface of the first substrate. The bottom package comprises a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with the electrically floating pad. | 2014-10-30 |
20140319669 | POWER MODULE - Provided is a power module. The power module includes a power semiconductor chip. The power module further includes a case that accommodates the power semiconductor chip. A silicone gel seals the power semiconductor chip within the case. The silicone gel including a heat-resistant silicone gel containing 20 to 100 mass ppm of a metal complex comprising a metal selected from a group consisting of iron and platinum. | 2014-10-30 |
20140319670 | IMAGE SENSOR PACKAGE WITH TRENCH INSULATOR AND FABRICATION METHOD THEREOF - The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; | 2014-10-30 |
20140319671 | SEMICONDUCTOR DEVICE AND GRINDING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, and a grinding-processed layer laminated on one surface of the semiconductor chip. Further, the semiconductor device includes a sealing resin that seals the semiconductor chip and the grinding-processed layer; and a metal remaining-thickness checking portion provided adjacent to the grinding-processed layer, sealed by the sealing resin, and having a inclined plane that is inclined with respect to a laminating direction of the grinding-processed layer. | 2014-10-30 |
20140319672 | FLOW CHANNEL MEMBER, HEAT EXCHANGER USING SAME, SEMICONDUCTOR DEVICE, AND DEVICE FOR MANUFACTURING SEMICONDUCTOR - Channel members | 2014-10-30 |
20140319673 | SEMICONDUCTOR DEVICE - In a semiconductor device in which a semiconductor chip is cooled by a cooler, an insulating member between a semiconductor chip and a cooler is omitted in order to simplify the configuration. A cooler ( | 2014-10-30 |
20140319674 | SEMICONDUCTOR COOLING DEVICE - A semiconductor cooling device includes: a cooling medium flow channel, through which a cooling medium for cooling a semiconductor chip flows; a laminar flow section which is provided in a region upstream of the cooling medium flow channel and allows the cooling medium to flow in the form of laminar flow; and a turbulent flow section which is provided in a region downstream of the laminar flow section in the cooling medium flow channel and allows the cooling medium, which flows in the form of laminar flow from the laminar flow section, to flow in the form of turbulent flow. | 2014-10-30 |
20140319675 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed. | 2014-10-30 |
20140319676 | ELECTRONIC COMPONENT MANUFACTURING METHOD AND ELECTRODE STRUCTURE - It is an object of the present invention to provide an electronic component manufacturing method, capable of suppressing reduction in a trench opening and suppressing diffusion of a metal film embedded in a trench. An embodiment of the present invention is an electronic component manufacturing method, including the steps of: forming a first electrode constituting layer (e.g., a TiAl film) in a recess (e.g., a trench) formed in a workpiece; forming an ultrathin barrier layer (e.g., a TiAlN film) by forming a nitride layer by plasma-nitriding a surface of the first electrode constituting layer; and forming a second electrode constituting layer (e.g., an Al wiring layer) on the ultrathin barrier layer. | 2014-10-30 |
20140319677 | SUBMOUNT FOR ELECTRONIC, OPTOELECTRONIC, OPTICAL, OR PHOTONIC COMPONENTS - One or more metal contacts are formed in a recessed area on a top surface of a submount; a pickup tool of a die bonder engages protruding peripheral regions of the submount so as not to damage the metal contacts or metal bumps in the recessed region. A semiconductor optical submount includes non-contiguous dielectric layers between metal contacts and the semiconductor material to reduce parasitic capacitance. | 2014-10-30 |
20140319678 | Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier - A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV. | 2014-10-30 |
20140319679 | Semiconductor Method and Device of Forming a Fan-Out POP Device with PWB Vertical Interconnect Units - A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. | 2014-10-30 |
20140319680 | Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer - A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad. | 2014-10-30 |
20140319681 | SEMICONDUCTOR PACKAGE INCLUDING SOLDER BALL - There is provided a semiconductor package comprising: a chip mounted on a substrate; and at least one solder ball formed under the substrate, wherein the solder ball comprises: a solder layer; a shell surrounded by the solder layer; and a phase change material contained in the shell. | 2014-10-30 |
20140319682 | MULTI-SOLDER TECHNIQUES AND CONFIGURATIONS FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY - Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed. | 2014-10-30 |
20140319683 | Packaged Semiconductor Devices and Packaging Devices and Methods - Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound. | 2014-10-30 |
20140319684 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - It is an object of the present invention to provide a wireless chip of which mechanical strength can be increased. Moreover, it is an object of the present invention to provide a wireless chip which can prevent an electric wave from being blocked. The invention is a wireless chip in which a layer having a thin film transistor is fixed to an antenna by an anisotropic conductive adhesive or a conductive layer, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer is sandwiched between the first conductive layer and the second conductive layer. The first conductive layer serves as a radiating electrode and the second conductive layer serves as a ground contact body. | 2014-10-30 |
20140319685 | Hybrid Graphene-Metal Interconnect Structures - Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene. | 2014-10-30 |
20140319686 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of silver. | 2014-10-30 |
20140319687 | SUBSTRATE WITH A FUNCTIONAL LAYER COMPRISING A SULPHUROUS COMPOUND - The invention relates to a substrate ( | 2014-10-30 |
20140319688 | Protection Layers for Conductive Pads and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line. | 2014-10-30 |
20140319689 | Contact Pads with Sidewall Spacers and Method of Making Contact Pads with Sidewall Spacers - A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls. | 2014-10-30 |
20140319690 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact. | 2014-10-30 |
20140319691 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a second spiral inductor formed in the multilayer interconnect. The first spiral inductor and the second spiral inductor collectively include a line, the line being spirally wound in a first direction in the first spiral inductor toward outside of the first spiral inductor, and being spirally wound in a second direction in the second spiral inductor toward inside of the second spiral inductor. The first direction and the second direction are opposite directions. | 2014-10-30 |
20140319692 | Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate - A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces. | 2014-10-30 |
20140319693 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias. | 2014-10-30 |
20140319694 | ANTICIPATORY IMPLANT FOR TSV - A method including implanting a region of a substrate with a dopant, and forming a through-substrate via in the substrate adjacent to a device, the through-substrate via passing through the region. | 2014-10-30 |
20140319695 | Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures - A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer. | 2014-10-30 |
20140319696 | 3D Packages and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device, a package, and methods of forming a semiconductor device and a package. An embodiment is a method including placing a plurality of dies over a passivation layer, the plurality of dies comprising at least one active device, molding the plurality of dies with a first molding material, and forming a plurality of through-package vias (TPVs) in the first molding material, first surfaces of the plurality of TPVs being substantially coplanar with a backside surfaces of the plurality of dies. The method further includes patterning the passivation layer to expose a portion of the first surfaces of the plurality of TPVs, and bonding a plurality of top packages to the first surfaces of the plurality of TPVs. | 2014-10-30 |
20140319697 | DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through | 2014-10-30 |
20140319698 | Redistribution Layer Contacting First Wafer through Second Wafer - A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer. | 2014-10-30 |
20140319699 | RELIABLE PACKAGING AND INTERCONNECT STRUCTURES - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 2014-10-30 |
20140319700 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a method of manufacturing a semiconductor device includes forming one or more first patterns and one or more second patterns adjacent to the first patterns on a substrate, each first pattern including a linear portion extending in a first direction, and each second pattern including first and second linear portions extending in the first direction and a connection portion connecting end portions of the first and second linear portions with each other. The method further includes forming a resist layer on the first and second patterns. The method further includes forming a resist opening in the resist layer so that at least a part of a contour line of the resist opening is a curved line and the curved line overlaps the second patterns. The method further includes dividing the second patterns into the first and second linear portions by etching using the resist layer. | 2014-10-30 |
20140319701 | SEMICONDUCTOR CHIP AND A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) STRUCTURE INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate. | 2014-10-30 |
20140319702 | Stackable Package by Using Internal Stacking Modules - A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate. | 2014-10-30 |
20140319703 | SELF-DEFINING, LOW CAPACITANCE WIRE BOND PAD - A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining flexibility of wire bond sites and ensuring mechanical integrity of the wire bonds. Embodiments provide, in a region that would be populated by a traditional bus bar bond pad, a small bus bar bond pad that is less than half the area of the region and populating at least a portion of the remaining area with metal tiles that are not electrically connected to the small bus bar bond pad or to each other. The metal tiles provide an attachment area for at least a portion of one or more wire bonds. Only those tiles involved in connection to a wire bond contribute to parasitic capacitance, along with the small bus bar pad. | 2014-10-30 |
20140319704 | STEAM VALVE APPARATUS - According to one embodiment, there is provided a steam valve apparatus including a main throttle valve, a steam control valve arranged on a downstream side of the main throttle valve, and an intermediate flow-channel part which connects the main throttle valve and the steam control valve. The intermediate flow-channel part is a circular pipe flow channel forming a circular arcuate shape so as to change a flow of steam, which has flowed out of the main throttle valve, from a perpendicular direction into a direction of flowing out into the inlet part. An outlet part is open upward, and a valve rod penetrates a lower part of a casing downward. | 2014-10-30 |
20140319705 | VAPOR CONCENTRATION CONTROL SYSTEM, VAPOR CONCENTRATION CONTROL DEVICE AND CONTROL PROGRAM - The present claimed invention includes a first flow channel where a carrier gas or a mixed gas flows, a switch valve that is for flowing the mixed gas or the carrier gas to the first flow channel selectively, a fluid adjusting valve that adjusts a concentration of a gas flowing in the first flow channel, and a control part that conducts a feedback control on an opening degree of the fluid adjusting valve, and is characterized such that the control part initiates the feedback control by the use of an opening degree of the fluid adjusting valve at a time just before the gas flowing in the first flow channel is switched from the mixed gas to the carrier gas as an initial opening degree of the fluid adjusting valve at a time when the gas flowing in the first flow channel is again switched to the mixed gas afterward. | 2014-10-30 |
20140319706 | SELECTIVE WATER VAPOUR TRANSPORT MEMBRANES COMPRISING A NANOFIBROUS LAYER AND METHODS FOR MAKING THE SAME - A water vapour transport membrane comprises a nanofibrous layer disposed on a macroporous support layer, the nanofibrous layer coated with a water permeable polymer. A method for making a water vapour transport membrane comprises forming a nanofibrous layer on a macroporous support layer and applying a water permeable polymer to the nanofibrous layer. The water permeable polymer can be applied for so that the nanofibrous layer is substantially or partially filled with the water permeable polymer, or so that the coating forms a substantially continuous layer on one surface of the nanofibrous layer. In some embodiments of the method, the nanofibrous layer is formed by electro-spinning at least one polymer on at least one side of the porous support layer. In some embodiments, the support layer is formable and the method further comprises forming a three-dimensional structure from the water vapour transport membrane, for example, by compression molding, pleating or corrugating. | 2014-10-30 |
20140319707 | MANUFACTURING METHOD OF OPTICAL DEVICE, AND OPTICAL DEVICE - In order to produce high-quality optical elements stably at all times without the flow of molten resin inside an injection molding cavity being hindered by the protrusion of the outer peripheral edge of a lens after compression molding, a cavity formed when a pair of molds for molding is closed is provided with: an optical-function-part molding cavity ( | 2014-10-30 |
20140319708 | INTERNAL OPTICAL ELEMENTS PRODUCED BY IRRADIATION-INDUCED REFRACTIVE INDEX CHANGES - Systems and methods are provided for forming an optical element within a transparent material using an irradiating optical beam, where the irradiating optical beam is employed to induce internal refractive index changes in the transparent substrate. Optical elements such as bulk and gradient index lenses may be formed in the transparent structure according various embodiments of the disclosure. An optical element may be formed by selecting a refractive index profile for the optical element, determining a corresponding suitable spatially dependent irradiation intensity profile for producing the selected refractive index profile, focusing an irradiating optical beam within the transparent structure, and controlling an intensity and position of the focused irradiating optical beam within the transparent structure according to the spatially dependent irradiation intensity profile. | 2014-10-30 |
20140319709 | LENS WITH LOW BIREFRINGENCE, METHOD OF FABRICATING THE LENS, AND LIGHT SCANNING UNIT INCLUDING THE LENS - There are provided a lens, a method of fabricating the lens, and a light scanning unit. The lens includes a lens portion having an effective optical surface, and a gate-side flange portion between the lens portion and a gate-side end of the lens. If the lens is disposed between two polarizers configured to polarize light linearly in perpendicular directions and is illuminated in an optical axis direction, interference fringes are generated on the lens, and peripheral interference fringes of the interference fringes extend continuously from the gate-side end and are longer than the gate-side flange portion. | 2014-10-30 |
20140319710 | METHOD OF MAKING LIGHT REDIRECTING FABRIC - A flexible sheet-form optical system, referenced to as a light redirecting fabric, which has a fabric-like behavior and light redirecting properties. The light redirecting fabric comprises a soft and flexible sheet of optically transmissive material, such as plasticized polyvinyl chloride. A surface of the flexible sheet includes a plurality of parallel slits having spaced-apart walls configured to reflect light by means of a total internal reflection. At least a portion of daylight incident onto the sheet is internally redirected at bend angles greater than the angle of incidence. Disclosed also are a method and apparatus for making the light redirecting fabric. The method includes steps of mechanical slitting of the flexible sheet with a blade, elastic stretch-elongation of the sheet along a direction perpendicular to the slits, and making at least a portion of the sheet elongation irreversible. | 2014-10-30 |
20140319711 | MULTI-WAVELENGTH COMPOSITE LIGHT-STORING POWDER AND METHOD OF MANUFACTURING AND APPLYING THE SAME - A multi-wavelength composite light-storing powder and method of manufacturing and applying the same. It utilizes organic compound having double-imide-bond steric structure, to produce high speed collisions with light-storing material containing rare earth elements in an environment of extremely low temperature, to make collision surface produce instantaneous high temperature, so that the organic compound is sputtered onto a surface of the light-storing material. The surface is cooled instantly due to extremely low temperature to produce the composite light-storing powder. The composite light-storing powder is apt to engage cross linked structure of thermoplastic polymer in a high temperature blending process. Then, through a filament process, to produce successfully light-storing fiber capable of emitting multi-wavelengths with high heat resistance and wash endurance. | 2014-10-30 |
20140319712 | PLASMA DEVICE FOR PRODUCTION OF METAL POWDER - A plasma device for production of metal powder includes a reaction vessel, a plasma torch, a carrier gas supply unit and a cooling tube. A metal starting material is supplied to the vessel. The torch produces plasma between the torch and the metal starting material to evaporate the metal starting material and produce a metal vapor. The supply unit supplies into the vessel a carrier gas for carrying the metal vapor. The cooling tube is provided with indirect and direct cooling sections and cools the metal vapor transferred from the vessel to produce the metal powder. The metal vapor and/or the metal powder are indirectly cooled in the indirect cooling section and directly cooled in the direct cooling section. A projection and/or a recess are disposed at least on a part of an inner wall of the indirect cooling section. | 2014-10-30 |
20140319713 | CASTING JIG INCLUDING ELONGATE HANDLE FOR CHAIR-SIDE MANUFACTURE OF CUSTOMIZABLE SCULPTABLE ANATOMICAL HEALING CAPS, AND METHOD FOR FORMING BIS-ACRYLIC CROWN - Casting jigs, methods, and kits that may be used in manufacture of anatomical healing caps. A casting jig may include a body having one or more wells within the body, each well being open at a proximal end thereof and having a negative shape corresponding to an anatomical healing cuff body of a given tooth position. The casting jig includes an opening through the bottom surface through which an elongate handle may be inserted, allowing a temporary abutment to be coupled into the distal end of the elongate handle, so that the abutment is disposed in the well, held in place by the handle, as it is used as a core about which the anatomical healing cuff body is formed. A crown forming jig for forming an inexpensive, chair-side prepared bis-acrylic temporary crown that may be easily and quickly installed over the anatomical healing cuff body is also disclosed. | 2014-10-30 |
20140319714 | GREEN HONEYCOMB MOLDING DEFECT EXAMINATION METHOD, GREEN HONEYCOMB STRUCTURE MANUFACTURING METHOD, AND GREEN HONEYCOMB MOLDING DEFECT EXAMINATION DEVICE - Disclosed is a method of examining defects in a green honeycomb molding having partition walls which form a plurality of flow channels extending in parallel with one another, and sealing portions which close the upper ends of some of the plurality of flow channels and the lower ends of the rest flow channels. The method includes a step of applying pressure to the lower ends of the plurality of flow channels using gas, and a step of visualizing the distribution of gas refractive indexes near the upper ends of the plurality of flow channels. | 2014-10-30 |
20140319715 | Method to Start-up a Process to Make Non-Expandable Vinyl Aromatic Polymers - A method for producing non-expandable pellets can include introducing a vinyl aromatic polymer to a pelletizer (L). The pelletizer (L) can have a die plate having a holes of large diameter. During the start-up of the production of the non-expandable pellets, pellets can be produced in the pelletizer (L). When the polymer flow rate is in the operating range of the pelletizer (S), the introduction of the vinyl aromatic polymer can be switched from the pelletizer (L) to the pelletizer (S). The pelletizer (S) can be operated at conditions effective to produce the non-expandable pellets. The pelletizer (S) can have a die plate having holes of small diameter. The non-expandable pellets can be recovered from the pelletizer (S), and the pellets can be recovered from the pelletizer (L). | 2014-10-30 |
20140319716 | RAPID PRODUCTION APPARATUS WITH PRODUCTION ORIENTATION DETERMINATION - A method of producing an object by sequentially printing layers of construction material one on top of the other, the method comprising: providing the construction material at a first lower temperature; flowing the construction material through a heated flow path in a flow structure to heat the construction material and delivering the heated construction material to a heated reservoir in a printing head; and dispensing the heated construction material from the reservoir to build the object layer by layer. | 2014-10-30 |
20140319717 | METHODS FOR PRODUCING BICYCLE SADDLES - A method for producing a bicycle saddle including a cover, a shell and a filler. The method is carried out by a mold including upper part with a male portion and a lower part with a female portion, which are pin-jointed together. The method comprises the steps of preheating the mold to a predetermined temperature; opening the mold; treating a layer of release agent onto the surfaces of the male portion and the female portion; spraying a first layer of a first plastic material onto the surface of the female portion treated with the layer of release agent to form a cover; coupling a shell to the male portion; pouring a second layer of a second plastic material onto the female portion; closing the mold and holding it in the closed position a period of time to form the filler; opening the mold to remove the finished saddle. | 2014-10-30 |
20140319718 | IMPRINTING DEVICE AND IMPRINTING METHOD - An imprinting device to transfer the mold pattern on a die to a molding target includes a casing forming a pressure-adjusting chamber, a stage supporting the die and the molding target, a frame encircling a circumference of the stage, first moving means moving the casing and the stage in a direction coming close to each other or becoming distant from each other, second moving means moving the casing and the frame in a direction coming close to each other or becoming distant from each other, pressure-adjusting means that adjusts the pressure of a fluid in the pressure-adjusting chamber, and decompression means which decompresses a decompression chamber formed by the stage, a frame, and the die or the molding target, and which eliminates a fluid present between the die and the molding target. | 2014-10-30 |
20140319719 | MOULDING DEVICE AND PRODUCTION PROCESS - A production process includes introducing the material to be moulded into a mould, placing the mould in an envelope comprising a vacuum port; creating a low pressure in the envelope by formation of a gas flow through the vacuum port; deforming the mould; stopping the gas flow; and applying pressure on at least a portion of the mould, optionally with interposition of the envelope, at least after the gas flow is stopped. | 2014-10-30 |
20140319720 | PHARMACEUTICAL COMPOSITIONS COMPRISING RIVAROXABAN - The invention relates to pharmaceutical compositions comprising rivaroxaban, suitable for immediate release, and processes of preparing such compositions, preferably by a melt-granulation process or by a specific direct-compression process. | 2014-10-30 |