44th week of 2008 patent applcation highlights part 71 |
Patent application number | Title | Published |
20080270747 | Method and Device for Switching Over Between Operating Modes of a Multi-Processor System Using at Least One External Signal - A method for a switchover in a computer system having at least two execution units, a switchover being performed between at least two operating modes, and a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, wherein the switchover is triggered by at least one signal, which is generated outside the computer system. | 2008-10-30 |
20080270748 | HARDWARE SIMULATION ACCELERATOR DESIGN AND METHOD THAT EXPLOITS A PARALLEL STRUCTURE OF USER MODELS TO SUPPORT A LARGER USER MODEL SIZE - A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs. | 2008-10-30 |
20080270749 | Instruction issue control within a multi-threaded in-order superscalar processor - A multi-threaded in-order superscalar processor | 2008-10-30 |
20080270750 | INSTRUCTION-PARALLEL PROCESSOR WITH ZERO-PERFORMANCE-OVERHEAD OPERAND COPY - A processor having a zero-overhead operand copy capability. The processor includes multiple execution units to execute instructions in parallel and multiple register files each associated with one or more of the execution units. The processor further includes circuitry to select either an instruction execution result from a first one of the execution units or content of a register within a first one of the register files associated with the first one of the execution units to be stored within a register within a second one of the register files. | 2008-10-30 |
20080270751 | SYSTEM AND METHOD FOR PROCESSING DATA IN A PIPELINE OF COMPUTERS - A series of computers to process data including a first and a last computer. Each of the computers except the first is preceded by a prior computer and each except the last is followed by a subsequent computer. A logic reads new data via a first data path and a logic writes old data via a second data path. A logic process the new data to produce the old data and, except for the last computer, a storage element stores the old data. The logic to write operates after the logic to read and the logic to write operates before the logic to process. | 2008-10-30 |
20080270752 | PROCESS ASSIGNMENT TO PHYSICAL PROCESSORS USING MINIMUM AND MAXIMUM PROCESSOR SHARES - A system and method is provided for assigning a plurality of executable processes to a plurality of physical processors in a multi-processor computer system using a minimum processor share and a maximum processor share defined for each executable process. In an embodiment, the method can include allocating shares of total processor time to each executable process in proportion to the minimum processor shares up to the maximum processor shares to form target share allocations. The target share allocations can be used to map processes to the physical processors. | 2008-10-30 |
20080270753 | IMAGE PROCESSING APPARATUS AND METHOD THEREOF - In a case that a precedent queue to supply data to be processed does not include data to be processed, a processor D switches its operation mode to an auxiliary mode to perform a part of processing assigned to a processor A, and issues a request for execution of the part of the processing assigned to the processor A, to the processor A. In response to the request, the processor A notifies the processor D of information to cause the processor D to perform the part of the processing assigned to the processor A, and the processor D performs the part of the processing assigned to the processor A in accordance with the notified information. | 2008-10-30 |
20080270754 | USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) TECHNOLOGY WITH A MICROPROCESSOR FOR RECONFIGURABLE, INSTRUCTION LEVEL HARDWARE ACCELERATION - A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well. | 2008-10-30 |
20080270755 | Reduced instruction set computer (RISC) processor based disk manager architecture for hard disk drive (HDD) controllers - Reduced instruction set computer (RISC) processor based disk manager architecture for HDD (Hard Disk Drive) controllers. A means is presented herein by which disk managers operations of a HDD are off-loaded from a main processor to a dedicated RISC processor. The main processor is operable to provide higher level instructions to the RISC processor, and the RISC processor is operable to translate those higher level instructions into bit level instructions that are subsequently provided to one or more control engines that is then operable to execute those bit level instructions to perform one or more channel interfacing protocol control functions that can include any one or more of low level timing for servo demodulation, timing for data formatting operations, media control operations, transfer control operations, and/or other disk manager related functions. | 2008-10-30 |
20080270756 | SHIFT SIGNIFICAND OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction. | 2008-10-30 |
20080270757 | Fetch and Dispatch Disassociation Apparatus for Multistreaming Processors - A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address. | 2008-10-30 |
20080270758 | Multiple thread instruction fetch from different cache levels - A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread. | 2008-10-30 |
20080270759 | Computer Having Dynamically-Changeable Instruction Set in Real Time - A computer allows dynamic change of an instruction set during a real-time execution. The computer includes a CPU (Central Processing Unit) having an instruction fetch unit for fetching an instruction from a memory, an instruction decoding unit for generating a predetermined control code corresponding to the instruction fetched by the instruction fetch unit, and an arithmetic logic unit operated by the control code. The instruction decoding unit includes a basic instruction decoding unit for generating a control code for a basic instruction set; and a dynamic instruction decoding unit for generating another control code different from the control code corresponding to an instruction of the basic instruction set, or generating a control code corresponding to an instruction not existing in the basic instruction set. An instruction stored in the dynamic instruction decoding unit or a corresponding control code is configured to be changeable during execution in real time. | 2008-10-30 |
20080270760 | DEBUG SUPPORT METHOD AND APPARATUS - According to the present invention, there is provided a debug support apparatus having, a decoder configured to receive an instruction output from a compiler which receives a source code, decode the instruction, and output a decoding result; and a display unit configured to receive debug information output from the compiler and the decoding result output from the decoder and display at least a correspondence between each decoded instruction and a position in the source code. | 2008-10-30 |
20080270761 | Techniques to generate event contexts for recurring events - Techniques to generate event contexts for recurring events are described. A computer system may comprise a context management module with an event detection module to detect a first occurrence of an event, a context recording module to record context information for the event, the event detection module to detect a second occurrence of the event, and a context generator module to create an event context for the event with the context information during the second occurrence of the event. Other embodiments are described and claimed. | 2008-10-30 |
20080270762 | Method, System and Computer Program Product for Register Management in a Simulation Enviroment - A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction. | 2008-10-30 |
20080270763 | Device and Method for Processing Instructions - A method and a device for processing instructions. The device includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is characterized by including a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. Whereas the second register group size information and the second register identification information define a second group of target registers associated with a second instruction. Whereas the second instruction is provided to the pipelined processor before the first instruction. | 2008-10-30 |
20080270764 | STATE MACHINE COMPRESSION - Compressing state transition instructions may achieve a reduction in the binary instruction footprint of a state machine. In certain embodiments, the compressed state transition instructions are used by state machine engines that use one or more caches in order to increase the speed at which the state machine engine can execute a state machine. In addition to reducing the instruction footprint, the use of compressed state transition instructions as discussed herein may also increase the cache hit rate of a cache-based state machine engine, resulting in an increase in performance. | 2008-10-30 |
20080270765 | DISPLAY INFORMATION VERIFICATION PROGRAM, METHOD AND APPARATUS - A display information verification method, when display data of financial data is generated from the financial data and scripts for the financial data, includes: searching the scripts for an arithmetic instruction to process a numeric value in the financial data or a conversion instruction to convert a character string included in the financial data; and judging whether or not the arithmetic instruction or the conversion instruction detected in the searching is an instruction considered to manipulate the financial data. Thus, it is possible to detect the instruction considered to manipulate data from the scripts, and to avoid display including the manipulation of the data. In addition, for example, by using information of the instruction, which is stored inside in advance and is allowed to be used, it is possible to detect only the arithmetic instruction or the conversion instruction, which is not allowed to be used. | 2008-10-30 |
20080270766 | Method To Reduce The Number Of Load Instructions Searched By Stores and Snoops In An Out-Of-Order Processor - A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the load instructions; checking load reorder queue (LRQ) entries; re-executing the load instruction of the matching LRQ entry; continuing execution; getting the load data; setting the load received data field; comparing a load sequence number (LSQN) of each load instruction to a snoop_safe register contents; ANDing all the load received data bits if the LSQN is greater in magnitude to the snoop_safe; setting the snoop_safe register to the LSQN of the load instruction; searching the LRQ entry; and setting a load_peril_snoop register to the LRQ index value where the first load instruction younger to the snoop_safe was found. | 2008-10-30 |
20080270767 | INFORMATION PROCESSING APPARATUS AND PROGRAM EXECUTION CONTROL METHOD - According to one embodiment, an information processing apparatus includes a first processor which has a first instruction set, a second processor which has a second instruction set, a storage unit which stores a program including a first program module which is described by using the second instruction set and causes the second processor to execute a first process including the arithmetic process, and a second program module which is described by using the first instruction set and causes the first processor to execute a process which is the same as the first process, and a control unit which switches a mode for executing the program between a first mode in which the first program module is assigned to the second processor and a second mode in which the second program module is assigned to the first processor. | 2008-10-30 |
20080270768 | Method and apparatus for SIMD complex Arithmetic - Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the real components of the second operand from the imaginary components of the first operand and to add the real components of the first operand to the imaginary components of the second operand. | 2008-10-30 |
20080270769 | PROCESS FOR RUNNING PROGRAMS ON PROCESSORS AND CORRESPONDING PROCESSOR SYSTEM - Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words. | 2008-10-30 |
20080270770 | Method for Optimising the Logging and Replay of Mulit-Task Applications in a Mono-Processor or Multi-Processor Computer System - This invention relates to a system and method for the management, more particularly by external, transparent and non-intrusive control, of the running of one or more software tasks within a multi-task application executed on a computer or a network of computers. This management comprises in particular a recording of the running of these tasks in the form of logging data, as well as a replay of this running from such logging data in order to present a behaviour and a result corresponding to those obtained while logging. | 2008-10-30 |
20080270771 | METHOD OF OPTIMIZING MULTI-SET CONTEXT SWITCH FOR EMBEDDED PROCESSORS - A method of optimizing multi-set context switch for embedded processors includes the steps of partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the registers, storing contents of first target registers according to live set information of a current task, wherein the first target registers are selected from the register sets, determining a next task by an operating system and updating the live set information according to the next task, and restoring contents of second target registers according to the updated live set information, wherein the second target registers are selected from the register sets. | 2008-10-30 |
20080270772 | Reduced data transfer during processor context switching - Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory. | 2008-10-30 |
20080270773 | Processing element having dual control stores to minimize branch latency - Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce or avoid branch penalties (zero penalty branches). | 2008-10-30 |
20080270774 | Universal branch identifier for invalidation of speculative instructions - A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path. | 2008-10-30 |
20080270775 | MANAGEMENT OF EXCEPTIONS AND HARDWARE INTERRUPTIONS BY AN EXCEPTION SIMULATOR - Exception handling is simulated. An exception simulator is employed to simulate exceptions generated from routines simulating operations. The exception simulator provides an indication of the exception and invokes an interruption, when appropriate. The exception simulator includes an instruction invoked to handle the exception and any interruption. | 2008-10-30 |
20080270776 | SYSTEM AND METHOD FOR PROTECTING MEMORY DURING SYSTEM INITIALIZATION - A system and method for protecting memory during system initialization is provided. A complex programmable logic device (CPLD) is operatively interconnected with a multiplexer to enable control of a memory to be switched between a memory controller and the CPLD in response to error conditions. If an error condition is identified, the CPLD assumes control of the memory and activates a battery subsystem to provide memory refreshes until system re-initialization. Upon system bring-up, interactions between the BIOS and CPLD assure that protected memory is fully recovered by the system. The contents of memory will remain protected from any further faults that may occur during the bring-up sequence. | 2008-10-30 |
20080270777 | SOFTWARE RECOVERY WITHOUT THE USE OF A KEYBOARD, MOUSE, TRACKBALL OR COMPUTER MONITOR - A NAS device comprises a user control and storage in which at least one of an operating system and system firmware is stored. Logic is also provided that is coupled to the user control and the storage. The logic causes a recovery to be performed of the operating system or system firmware upon user activation of the user control. The NAS device does not comprise any of a keyboard, mouse, trackball, and computer monitor. | 2008-10-30 |
20080270778 | UNIVERSAL MICROCODE IMAGE - Systems and methods for creating universal microcode images and for reconstructing a microcode image from a universal microcode image are described in the present disclosure. One method, among others, comprises receiving a plurality of microcode images each configured to initialize hardware within an electronic device before the electronic device is booted up. The method also includes separating each microcode image into sections and comparing the sections to determine whether or not two or more sections contain identical code. The method also includes creating a universal microcode image from the sections that are unique. | 2008-10-30 |
20080270779 | System management mode enhancements - Methods, systems, and computer program products are provided for making PEI phase implementation independent from DXE phase implementation in a computer system implementing the Extensible Firmware Interface standard. For example, one embodiment of the present invention uses a hand-off block to make SMBASE initialization in PEI independent form SMBASE initialization in DXE. In another embodiment of the present invention, PEI phase is entered in order to resume from an S3 standby state. | 2008-10-30 |
20080270780 | DESIGN STRUCTURE FOR DISABLING A UNIVERSAL SERIAL BUS PORT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is disclosed for disabling a Universal Serial Bus (‘USB’) port by identifying a USB port to be disabled, the USB port to be disabled controlled by a USB hub controller, and turning on an over current signal for the identified USB port. | 2008-10-30 |
20080270781 | Secure compter system update - In one embodiment a computer system, comprises a processor, a trusted platform module comprising at least one platform configuration register, a basic input/output system, and logic to unseal at least one current key in the trusted platform module, initiate an update to the basic input/output system, obtain, with the update, at least a component of one expected value for a platform configuration register in the trusted platform module, seal at least one key using the at least one expected value for a platform configuration register, and install the basic input/output system update. | 2008-10-30 |
20080270782 | BOOT PROCESS - When a secure boot operation fails, the operation of a mobile telecommunications terminal can be severely impacted. In order to lower the impact on the user, one example embodiment of the invention relates to a method for automatically implementing a “safe boot” mode, whereby code can be accessed solely for the purpose of handling failed operations and if necessary providing limited services from the failing terminal. | 2008-10-30 |
20080270783 | METHOD FOR DETERMINING A REBOOTING ACTION OF A COMPUTER SYSTEM AND RELATED COMPUTER SYSTEM - A method for determining a rebooting action of a computer system includes: a keyboard controller of the computer system detecting whether a signal representing a system stage transformation is transmitted from a south bridge chipset; determining whether a system status flag is set as “ON” when the signal representing the system stage transformation is received by the keyboard controller; setting a rebooting flag as “ON” and setting the system status flag as “OFF”; determining whether a system sleeping flag representing the computer system isn't activated is “ON” and determining whether the rebooting flag is set as “OFF” according to this determined result; detecting whether the signal representing the system stage transformation is transmitted from the south bridge chipset; determining whether the rebooting flag is set as “ON”; and determining whether the computer system executes the rebooting action according to a determined result of whether the rebooting flag is “ON”. | 2008-10-30 |
20080270784 | Display Configuration-Reconfiguration Method For a Set of Display Devices - The invention relates to systems provide with control devices comprising an important number of displaying devices for displaying an important number of parameters according to accurate configurations, as for example, a modern aircraft instrument panel provided with several displays. The inventive method for configuring or reconfiguring the totality of displaying devices consists in inducing said configuration or reconfiguration by an event. Each elementary configuration is substantially obtainable by means of a reconfiguration logic language and an interpreter algorithm, wherein said logic language substantially comprises a reconfiguration domain, properties, transition rules, and preferences and said interpreter algorithm makes it possible to convert each transition rule into a list of elementary reconfiguration. | 2008-10-30 |
20080270785 | Security approach for transport equipment - An apparatus comprising encryption logic that provides security for fiber-based communications may be implemented in accordance with an embodiment of the present invention. A data super frame is created by the encryption logic to comprise two or more data frames. Each of the data frames contains a payload portion. The encryption logic may receive one or more data payloads that are associated with a client signal. Using a single set of security control parameters, the encryption logic encrypts and stores a different encrypted payload in a payload portion of a different frame of the data frames in the data super frame. Instead of storing the set of security control parameters in a single data frame, the encryption logic stores the set of security control parameters in different sets of unused bytes associated with at least two different frames of the data frames. | 2008-10-30 |
20080270786 | APPARATUS AND METHOD FOR DIRECT ANONYMOUS ATTESTATION FROM BILINEAR MAPS - A method and apparatus for direct anonymous attestation from bilinear maps. In one embodiment, the method includes the creation of a public/private key pair for a trusted membership group defined by an issuer; and assigning a unique secret signature key to at least one member device of the trusted membership group defined by the issuer. In one embodiment, using the assigned signature key, a member may assign a message received as an authentication request to prove membership within a trusted membership group. In one embodiment, a group digital signature of the member is verified using a public key of the trusted membership group. Accordingly, a verifier of the digital signature is able to authenticate that the member is an actual member of the trusted membership group without requiring of the disclosure of a unique identification information of the member or a private member key to maintain anonymity of trusted member devices. Other embodiments are described and claimed. | 2008-10-30 |
20080270787 | BIOMETRIC IDENTIFICATION NETWORK SECURITY - Systems and methods for regulating user access in the context of a biometric security system are disclosed. One method disclosed includes receiving a remotely transmitted data packet containing an encryption key, utilizing a decryption component to decrypt the data packet, and utilizing the encryption component to encrypt biometric data. Another method disclosed includes utilizing a processor, within a client computing device, to perform an encryption function within a biometric security system, wherein the encryption function is incorporated into an authentication process that involves a transfer of biometric information between the client computing device and a remotely implemented server. | 2008-10-30 |
20080270788 | EXTENSION OF X.509 CERTIFICATES TO SIMULTANEOUSLY SUPPORT MULTIPLE CRYPTOGRAPHIC ALGORITHMS - A technique permitting an X.509 certificate to simultaneously support more than one cryptographic algorithm. An alterative public key and alternative signature are provided as extensions in the body of the certificate. These extensions define a second (or more) cryptographic algorithm which may be utilized to verify the certificate. These are not authenticated by the primary signature and signature algorithm in the primary cryptographic algorithm. These newly defined extensions are reviewed by a receiving entity if the entity does not support the cryptographic algorithm of the primary signature. | 2008-10-30 |
20080270789 | METHOD AND SYSTEM FOR MESSAGING SECURITY - An e-mail firewall applies policies to e-mail messages transmitted between a first site and a plurality of second sites. The e-mail firewall includes a plurality of mail transfer relay modules for transferring e-mail messages between the first site and one of the second sites. Policy managers are used to enforce and administer selectable policies. The policies are used to determine security procedures for the transmission and reception of e-mail messages. The e-mail firewall employs signature verification processes to verify signatures in received encrypted e-mail messages. The e-mail firewall is further adapted to employ external servers for verifying signatures. External servers are also used to retrieve data that is employed to encrypt and decrypt e-mail messages received and transmitted by the e-mail firewall, respectively. | 2008-10-30 |
20080270790 | APPARATUS AND METHOD FOR ENHANCED REVOCATION OF DIRECT PROOF AND DIRECT ANONYMOUS ATTESTATION - In some embodiments, a method and apparatus for enhanced revocation of direct proof and direct anonymous attestation are described. In one embodiment a trusted hardware device verifies that membership of the device within a trusted membership group is not revoked according to a revocation list received with a challenge request from a verifier. Once such verification is performed, the device convinces the verifier of possessing cryptographic information without revealing unique, device identification information of the trusted hardware device or the cryptographic information. In one embodiment, the trusted hardware device computes a digital signature on a message received with the challenge request to the verifier if membership of the anonymous hardware device within a trusted membership group is verified. In one embodiment, the verifier authenticates the digital signature according to a public key of the trusted membership group to enable a trusted member device to remain anonymous to the verifier. Other embodiments are described and claimed. | 2008-10-30 |
20080270791 | Method and Apparatus for Remote Administration of Cryptographic Devices - Techniques are disclosed for performing operations in an authentication token or other cryptographic device in a system comprising an authentication server. In one aspect, a code generated by the authentication server is received in the cryptographic device. The code may have associated therewith information specifying at least one operation to be performed by the cryptographic device. The cryptographic device authenticates the code, and responsive to authentication of the code, performs the specified operation. If the code is not authenticated, the operation is not performed. The code may be determined as a function of a one-time password generated by the authentication server. The function may also take as an input an identifier of the operation to be performed. | 2008-10-30 |
20080270792 | SYSTEM AND METHOD OF ENCRYPTING AND DECRYPTING DIGITAL FILES PRODUCED BY DIGITAL STILL DEVICES - An exemplary system of encrypting and decrypting a digital file in a digital device is disclosed. The digital file includes an encrypting module and a decrypting module. The encrypting module includes a file-choosing block choosing a digital file to be encrypted, a code-building block producing a code for the chosen digital file and an encrypting block rendering the code for storing in the EXIF of the chosen digital file. The decrypting module includes a file-selecting block selecting an encrypted digital file, a code-taking block receiving an input code, a code-checking block comparing the input code with the code stored in the EXIF, and a decrypting block decrypting the selected file when the input code is identical to the code stored in the EXIF. | 2008-10-30 |
20080270793 | Communication Protocol and Electronic Communication System, in Particular Authentication Control System, as Well as Corresponding Method - In order to provide a communication protocol for cryptographic authentication on the basis of at least one cryptographic algorithm, in particular according to the A[dvanced]E[ncryption]S[tandard], by
| 2008-10-30 |
20080270794 | Method and Server for Providing Mobility Key - After a radio link is established between a mobile subscriber terminal and an access network, to authenticate the subscriber an authentication proxy server of an intermediate network forwards at least one authentication message containing a subscriber identification between the access network and a home network of the subscriber. If authentication is given by an authentication server of the home network, the authentication proxy server of the intermediate network stores the subscriber identification. The home agent receives a registration request message originating from the subscriber terminal and containing a subscriber identification; the home agent transmits a key request message, containing the subscriber identification, for a mobile key to the relevant authentication proxy server. The authentication proxy server provides a mobile key for the home agent, if the subscriber identification contained in the key request message matches one of the subscriber identifications that has been stored by the authentication proxy server. | 2008-10-30 |
20080270795 | METHOD TO CREATE AN OSI NETWORK LAYER 3 VIRTUAL PRIVATE NETWORK (VPN) USING AN HTTP/S TUNNEL - A method of creating and using a virtual private network (VPN) client encrypts network communications to server/gateways using strong algorithms to ensure data integrity and privacy during transport. Transport uses standard HTTP packets. Encryption and integrity are provided by using Secure Socket Layer (SSL, sometimes referred to as TLS). This invention is compatible and portable to different computer operating systems and mobile devices, and is also lightweight, allowing for ‘clientless’ installation and removal or small-footprint (thin) client software installations. The invention can also secure mobile user communication links over public wireless hotspots or wired Internet links. | 2008-10-30 |
20080270796 | SYSTEM AND METHOD FOR PROVIDING PROGRAM INFORMATION, AND RECORDING MEDIUM USED THEREFOR - A system for providing program information has a user terminal, a recording medium capable of reading information therefrom and writing information thereto through a command issued by the user terminal, and a server connected to the user terminal via a network, and provides program information from the server to the recording medium. The recording medium has a first control unit that performs a first mutual authentication operation with a first storage unit capable of writing program information thereto and the user terminal, and that executes a command to write program information to the first storage unit only if the first mutual authentication operation is successful. The user terminal performs a second mutual authentication operation with the server, obtains program information transmitted from the server if the second mutual authentication operation is successful, and issues a command to write the program information to the first storage unit of the recording medium. | 2008-10-30 |
20080270797 | SYMBIOTIC STORAGE DEVICES - A system is provided, the system having a first storage device and a second storage device. A symbiotic relationship is established between the first and second storage devices to selectively store backup digital content for each other. | 2008-10-30 |
20080270798 | Anonymous Authentification Method - An authentication method based on an encryption algorithm with a secret key. According to the invention, the anonymity of the entity being authenticated is guaranteed, so that only a legitimate authentication entity may recognize the identity of the entity which is being authenticated. | 2008-10-30 |
20080270799 | Contents Generator and Method - Time stamped streams respectively generated by an AV stream generating means and data stream generating means are combined by a time-stamped contents generating means. Consequently, a time-stamped contents stream is generated which synchronizes the processing of an AV stream and multimedia data. | 2008-10-30 |
20080270800 | Adjustment of clock approximations - Techniques to adjust clock approximations are described, which may be used to synchronize content output at a client. In an implementation, timestamps derived from a universal time source are allocated to respective program clock reference (PCR) timestamps in content received by a network operator during an interval of time to form ordered pairs of timestamps. An approximation is computed of a plurality of the ordered pairs of timestamps for the interval and the approximation is adjusted using an ordered pair of timestamps taken from a previous approximation. | 2008-10-30 |
20080270801 | Watermarking a Media Signal by Adjusting Frequency Domain Values and Adapting to the Media Signal - A method of imperceptibly embedding a code signal in a media signal encodes auxiliary information in frequency components of the media signal. This method forms a code signal comprising a plurality of frequency components. The method embeds the code signal into the media signal by adjusting the frequency component relative to a neighboring component. The method changes selection of the plurality of frequency components corresponding to the codes signal for different instances of embedding the code signal in the media signal. The code signal may be used to encode a combination of fixed and variable message information in audio and image signals, including video. In one application, the attributes of the code signal are measured to determine broadcast signal quality. In another, the code signal robustly carries auxiliary information in distribution channels where distortion is common, such as compression, broadcast distortion, packet loss, digital to analog conversion, and ambient air transmission. | 2008-10-30 |
20080270802 | METHOD AND SYSTEM FOR PROTECTING PERSONALLY IDENTIFIABLE INFORMATION - The present invention provides a way to protect PII (or, more generally, any user “sensitive” information) throughout its life cycle in an organization. The techniques described herein ensure that a user's PII is protecting during storage, access or transfer of the data. Preferably, this objective is accomplished by associating given metadata with a given piece of PII and then storing the PII and metadata in a “privacy protecting envelope.” The given metadata includes, without limitation, the privacy policy that applies to the PII, as well as a set of one more purpose usages for the PII that the system has collected from an end user's user agent (e.g., a web browser), preferably in an automated manner. Preferably, the PII data, the privacy policy, and the user preferences (the purpose usages) are formatted in a structured document, such as XML. The information in the XML document (as well as the document itself) is then protected against misuse during storage, access or transfer using one or more of the following techniques: encryption, digital signatures, and digital rights management. | 2008-10-30 |
20080270803 | Biometric Encryption And Decryption - Cryptographic methods and systems are disclosed. The cryptographic methods provide transparent encryption and decryption of documents in an electronic document management system. The cryptographic system adds a software module to an electronic document management system which traps file I/O events and performs cryptographic functions on the relevant documents before passing control back to the electronic document management system. | 2008-10-30 |
20080270804 | COPY PROTECTED DIGITAL DATA - The present invention relates to digital data comprising a passive part ( | 2008-10-30 |
20080270805 | Method for Protecting Intellectual Property Cores on Field Programmable Gate Array - Techniques are used to protect intellectual property cores on field programmable gate arrays. An approach is to associate each field programmable gate array, or a limited number of field programmable gate arrays, with a secret key. Each field programmable gate array may only be properly configured or programmed by an appropriate encrypted bitstream (which includes one or more intellectual property cores). This encrypted bitstream has been encoded by or for the secret key associated with a particular FPGA. Other techniques are also presented in this application and include network-based, nonnetwork-based, software-based, layered, and other approaches. The techniques allow an intellectual property core vendor to charge a customer per-use or per-configuration of their intellectual property. This is because an encrypted bitstream is useable only in a limited number, possibly just one, of the integrated circuits. | 2008-10-30 |
20080270806 | Execution Device - An execution device executes an application program created in an object-oriented language. An application includes one or more classes that each have one or more methods, and confidentiality information that expresses whether or not confidentiality is necessary. The execution device determines whether or not encryption is necessary, with reference to the confidentiality information, and when the method is to be executed, records, in a memory, an object including data that the method manipulates. When it is determined that encryption is necessary, the object is recorded with the data encrypted. | 2008-10-30 |
20080270807 | Method for Selective Encryption Within Documents - The present invention allows the user (author or creator) of a document to specify that certain portions of a document be selected for encryption while other portions of the document remain displayed as created. In addition, each encrypted section could have multiple encryption keys such that some viewers can review certain parts of the document while other viewers will not have that same access. The user could employ a standard word processing editor technique to highlight (or swipe) portions of a document that the user desires to be encrypted. The highlighted portion would then be tagged with a surrounding attribute indicating to the word processor that this highlighted portion of the document is to be encrypted. The highlighted sections would also have encryption keys associated with the highlighted and encrypted section. Any one of the encryption keys for that section would decrypt that section. With proper authorization, any encrypted portion of a document would be displayed as part of the document. Without proper authorization, the display of the document would only contain the unencrypted portions of the document. | 2008-10-30 |
20080270808 | Electronic Device - An electronic device is disclosed herein. An embodiment of the electronic device comprises an electronic component, wherein the electronic component is operated by a DC voltage. The electronic component comprises an AC to DC converter that converts an AC voltage to the DC voltage, wherein the RMS value of the AC voltage is greater than the DC voltage. The electronic device further comprises a power supply comprising an input and an output. The input is connectable to a line voltage and the output is connected to the AC to DC converter of electronic component. The AC voltage is output by the output of the power supply. | 2008-10-30 |
20080270809 | I/O port power control system and method - An input/output (I/O) power control system comprises an electronic device having at least one I/O port and a controller, wherein the controller is configured to, while the electronic device is powered off, detect coupling of an external device to the at least one I/O port and, in response to detecting the coupling, provide power to the I/O port. | 2008-10-30 |
20080270810 | Electronic device with flexible processing system - An electronic device comprising a host module and a wireless module each comprising a processing unit, wherein the electronic device is configurable to be operated in a low processing mode by performing processing functions for the electronic device using the processing unit of the wireless module. | 2008-10-30 |
20080270811 | Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory - A personal computer motherboard has a main memory of phase-change-memory (PCM) chips in PCM memory modules. An operating system (OS) image is stored in the PCM memory modules and is retained during suspend since the PCM chips are non-volatile. The microprocessor can directly read the OS image retained in the PCM memory modules without copying an OS image from a hard disk to the main memory upon resume. Therefore a boot loader program in the boot ROM does not have to be fetched to the microprocessor for suspend/resume. The video memory can also be PCM, allowing the frame buffer to be retained during suspend/resume, yet be directly addressable by the microprocessor. The display is quickly activated since the frame buffer does not have to be re-constructed after suspend/resume. PCM cells use amorphous and crystalline states of a variable resistor to store data. | 2008-10-30 |
20080270812 | ASYNCHRONOUS WAKEUP MECHANISM - A system for asynchronous process sleep or wake management and corresponding methods thereof are described. The system comprises a sleep queue hash table, a process, and a first sleep object and a second sleep object. The first and second sleep objects each comprise a sleep queue and each of the first and second sleep objects are associated with the process. The system further comprises one or more kernel-space processes arranged to perform at least one of associating the first sleep object with the sleep queue hash table and designating the second sleep object to be used for sleeping the process. | 2008-10-30 |
20080270813 | Mother/daughter switch design with self power-up control - System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current. | 2008-10-30 |
20080270814 | Controlling power states of a peripheral device in response to user proximity - In a method of controlling the power state of a peripheral device, the peripheral is changed from a first power state to a second power state in response to communications across a network connected to the peripheral indicating that a user is proximately located to the peripheral. A user may be determined to be proximately located to the peripheral by monitoring communications across the network to detect traffic that is associated with a user logging onto a computer that can utilize the peripheral, by discovering a wireless terminal that is associated with a user and which is proximately located to the peripheral, by receiving information from a cellular communication network across the network that indicates that a user of the peripheral is proximately located to the peripheral, and/or in response to a time of day and/or day of week/month schedule. | 2008-10-30 |
20080270815 | DEVICE CONTROL APPARATUS AND DEVICE CONTROL METHOD - A device control apparatus includes: an interface connectable to at least one device having a power-saving function of stopping an action of a storage unit when a state that the storage unit is not accessed continues for more than a given time; a test data writing unit transmitting a writing command of test data to the storage unit through the interface in an interval shorter than the given time, when the device is connected to the interface; and a test data deleting unit transmitting to the device a deleting command to delete the test data in correspondence with a reception of a response to the writing command, the response being indicating writing completion and sent back from the device. | 2008-10-30 |
20080270816 | Portable data storage apparatus and synchronization method for the same - The present invention discloses a portable data storage apparatus for use with a host device, including an interface coupled to the host device for data transmission therebetween, a real time clock (RTC) for synchronizing the portable data storage apparatus with a clock time, and a memory module for storing data and a detection program for detecting time discrepancy between system time of the host device and the clock time of the RTC after the storage apparatus is loaded to the host device. | 2008-10-30 |
20080270817 | PRECISION OSCILLATOR FOR AN ASYNCHRONOUS TRANSMISSION SYSTEM - A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART is provided for digitally communicating with an off-chip UART, which off-chip UART has an independent time reference, which communication between the on-chip UART and the off-chip UART is effected without clock recovery. The on-chip UART has a time-base derived from the temperature compensated clock. The temperature compensated clock provides a time reference for both the processing circuitry and the on-chip UART. | 2008-10-30 |
20080270818 | Serial Communication Interface with Low Clock Skew - A communication interface for use in an integrated circuit comprises a clock root circuit ( | 2008-10-30 |
20080270819 | Uncorrelated actions using a distributed system - A distributed system that uses distributed synchronized time to perform uncorrelated actions. A distributed system according to the present teachings includes a set of nodes each having a synchronized real-time clock. The nodes use the synchronized real-time clocks to trigger a set of uncorrelated actions from the nodes. | 2008-10-30 |
20080270820 | Node management device and method - A device that is communicably connected to each of three or more nodes constituting a cluster system holds resource information, which is information relating to a resource used by an application, in relation to each of the three or more nodes. The device receives resource condition information indicating variation in the condition of the resource from each node, updates the resource information on the basis of the received resource condition information, determines a following active node on the basis of the updated resource information, and notifies at least one of the three or more nodes of the determined following active node. | 2008-10-30 |
20080270821 | RECOVERING FROM ERRORS IN A DATA PROCESSING SYSTEM - A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface. | 2008-10-30 |
20080270822 | DATA REPLICA SELECTOR - There is provided a method and system for replicating data at another location. The system includes a source node that contains data in a data storage area. The source node is coupled to a network of potential replication nodes. The processor determines at least two eligible nodes in the network of nodes and determines the communication cost associated with a each of the eligible nodes. The processor also determines a probability of a concurrent failure of the source node and each of eligible nodes, and selects at least one of the eligible nodes for replication of the data located on the source node. The selection is based on the determined communication costs and probability of concurrent failure. | 2008-10-30 |
20080270823 | FAST NODE FAILURE DETECTION VIA DISK BASED LAST GASP MECHANISM - A method for communicating node liveness in a multinode data processing system employs an operating system function that provides a degree of self-awareness in “sensing” an imminent but still pending failure as the basis for providing special flag signals over a channel which employs nonvolatile storage in a heartbeat signaling path. | 2008-10-30 |
20080270824 | PARALLEL INSTRUCTION PROCESSING AND OPERAND INTEGRITY VERIFICATION - A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error. | 2008-10-30 |
20080270825 | SYSTEM AND METHOD FOR FAILOVER OF GUEST OPERATING SYSTEMS IN A VIRTUAL MACHINE ENVIRONMENT - A system and method provides for failover of guest operating systems in a virtual machine environment. During initialization of a computer executing a virtual machine operating system, a first guest operating system allocates a first memory region within a first domain and notifies a second guest operating system operating in a second domain of the allocated first memory region. Similarly, the second guest operating system allocates a second region of memory within the second domain and notifies the first operating system of the allocated second memory region. In the event of a software failure affecting one of the guest operating systems, the surviving guest operating system assumes the identity of the failed operating system and utilizes data stored within the shared memory region to replay to storage devices to render them consistent. | 2008-10-30 |
20080270826 | REDUNDANT MEMORY TO MASK DRAM FAILURES - A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area. | 2008-10-30 |
20080270827 | RECOVERING DIAGNOSTIC DATA AFTER OUT-OF-BAND DATA CAPTURE FAILURE - Embodiments of the present invention address deficiencies of the art in respect to out-of-band management of system fault handling and provide a novel and non-obvious method, system and computer program product for recovering diagnostic data after out-of-band data capture failure. In an embodiment of the invention, a method for recovering diagnostic data after out-of-band data capture failure can include detecting an uncorrectable error in a coupled CPU. Thereafter, the coupled CPU can be placed in a quiesced state and the CPU can be warm reset. Error data can be retrieved from the CPU registers for the CPU and the CPU can be rebooted. Finally, the quiesced state of the CPU can be removed. | 2008-10-30 |
20080270828 | Memory Redundancy Method and Apparatus - Redundancy is provided in a memory device having a configurable data bus organization by associating a redundant memory location with a defective memory location and configuring a size of the redundant memory location based on the current data bus organization of the memory device. | 2008-10-30 |
20080270829 | CHECKPOINT OF APPLICATIONS USING UNIX® DOMAIN SOCKETS - A computer implemented method, apparatus, and computer program product for managing state data in a workload partitioned environment. Process state data for a process in a workload partition is saved. Process state data is used to restore the process to a given state. State data associated with open sockets and open files bound to the first process is saved. In response to a determination that the process is associated with a domain socket that is bound to a socket file, an absolute pathname for the socket file is saved. A domain socket associated with a connecting process in the workload partition uses the socket file to connect to a domain socket associated with a listening process in the same workload partition to enable the two processes to communicate with each other. | 2008-10-30 |
20080270830 | Data Processing System and Method for Operating a Data Processing System - To improve the availability of a data processing system despite possible memory errors, when reading a data word from a memory cell, the integrity of the data word is checked on the basis of redundant additional information, and if the data word turns out to be corrupted, an error correction procedure is performed in which the reliability performance of the memory cell is checked and, if the memory cell is found to be operational, its contents are restored. | 2008-10-30 |
20080270831 | Rollback method and information processing apparatus executing the same - It is determined that a write access is executed to a stack area of a main memory. It is then determined whether another write access to a corresponding access destination address in the stack area occurred in the past by referring to an access flag table. In contrast, it is determined that a write access is executed to a global area of the main memory. It is then determined whether another write access to a corresponding access destination address in the global area occurred in the past with referring to an access list. Such a configuration can efficiently provide individual advantages of the determination methods using both the access flag table and the address list. The presence or absence of the past saving execution can be efficiently determined at the time of write access. | 2008-10-30 |
20080270832 | Efficiently re-starting and recovering synchronization operations between a client and server - Systems, methods and computer program products for efficiently re-starting and/or recovering interrupted synchronizations between a client and a server are described herein. A server transmits sync data to a client during a synchronization operation. The sync is interrupted for some reason prior to the client receiving all of the sync data. The client sends to the server a request to re-start the synchronization operation. The request includes information that identifies a point in the sync data that was received by the client prior to interruption of the sync. Such information may include (a) information identifying the last data received by the client prior to interruption of the sync; and/or (b) information identifying the next data needed by the client upon re-start of the sync. Thereafter, the server re-starts the sync by transmitting to the client the sync data starting from said point in said sync data identified by said request. | 2008-10-30 |
20080270833 | SYSTEMS AND METHODS FOR REDUCING NETWORK PERFORMANCE DEGRADATION - Systems and methods for reducing network performance degradation by assigning caching priorities to one or more states of a state machine are disclosed herein. In one embodiment, the method comprises storing, in a memory, a state machine corresponding to one or more patterns to be detected in a data stream, wherein the state machine comprises a plurality of states, generating a test data stream based on the one or more patterns, traversing the state machine with the test data stream, determining a respective hit quantities associated with each of the plurality of states, the hit quantities each indicating a number of accesses to a corresponding state by the traversing, and associating a caching priority to at least some of the plurality of states based on the hit quantities of the respective states. | 2008-10-30 |
20080270834 | CONTROL METHOD FOR READ OPERATION OF MEMORY - Received read commands and address signals are respectively decoded into internal column strobe signals and internal address signals for reading data out of a data storage portion of a memory. A waiting interval during which a readout data becomes ready is simulated or a transmission path on which the readout data is transmitted is simulated. When the simulation result indicates the readout data is ready, an error check operation is performed on the readout data. The operation interval of the error check is simulated. When the simulation for the error check operation indicates that the error check is completed, an error check result is sent out of the memory. | 2008-10-30 |
20080270835 | Methods and Apparatus for Displaying Test Results and Alerts - In one embodiment, a sequence of test data items is parsed to identify test results, alerts, and context information that indicates how the test results and alerts correspond to a test execution sequence. The test results and at least some of the context information is displayed in a first display area of a graphical user interface (GUI); and the alerts and at least some of the context information is displayed in a second display area of the GUI. Other embodiments are also disclosed. | 2008-10-30 |
20080270836 | STATE DISCOVERY AUTOMATON FOR DYNAMIC WEB APPLICATIONS - An automaton that detects possible states and transitions that can possibly exist in a web based application is provided. The automaton may comprise a plugin system, an HTTP processor, an application handler, a page handler, an input handler, journals, a coverage analyzer, an expression language interpreter, and a data validator. | 2008-10-30 |
20080270837 | SYSTEM DIAGNOSTIC UTILITY - A computer implemented method, apparatus, and computer usable program code for performing diagnostic testing for an application executing on a computer. A diagnostic utility executes on the computer. The diagnostic utility includes a graphical user interface and a plurality of diagnostic functions. A selection of the application executing on the computer is received for diagnostic testing through the graphical user interface. Responsive to receiving the selection of the application, a set of diagnostic functions from the plurality of diagnostic functions is identified to test at least one of connectivity, operation of the application, and a presence of a set of needed files for the application to form a set of identified diagnostic functions. The set of identified diagnostic functions are identified using configuration information for the application. The set of identified diagnostic function are executed, wherein a result is generated. A result from executing the set of functions is presented using the graphical user interface. | 2008-10-30 |
20080270838 | DISTRIBUTED, FAULT-TOLERANT AND HIGHLY AVAILABLE COMPUTING SYSTEM - A method and system for achieving highly available, fault-tolerant execution of components in a distributed computing system, without requiring the writer of these components to explicitly write code (such as entity beans or database transactions) to make component state persistent. It is achieved by converting the intrinsically non-deterministic behavior of the distributed system to a deterministic behavior, thus enabling state recovery to be achieved by advantageously efficient checkpoint-replay techniques. The method comprises: adapting the execution environment for enabling message communication amongst and between the components; automatically associating a deterministic timestamp in conjunction with a message to be communicated from a sender component to a receiver component during program execution, the timestamp representative of estimated time of arrival of the message at a receiver component. At a component, tracking state of that component during program execution, and periodically checkpointing the state in a local storage device. Upon failure of a component, the component state is restored by recovering a recent stored checkpoint and re-executing the events occurring since the last checkpoint. The system is deterministic by repeating the execution of the receiving component by processing the messages in the same order as their associated timestamp. | 2008-10-30 |
20080270839 | Masked signal trap loop avoidance - An embodiment of the invention provides an apparatus and a method for avoidance of a masked signal trap loop. The apparatus and method perform acts including: terminating a process of an application and generating a core dump file, if parameters are set in an error detection engine and a signal is masked when a coding error is encountered in the application. | 2008-10-30 |
20080270840 | DEVICE AND METHOD FOR TESTING EMBEDDED SOFTWARE USING EMULATOR - Embodiments of the invention provide a device and a method for automatically testing embedded software, and more specifically for testing interfaces between layers of the embedded software. In one embodiment, the device includes: an emulator; a server including embedded software; an evaluation board configured to download the embedded software from the server and controlled by the emulator; and a host system configured to receive the embedded software from the server and automatically generate test cases for testing the embedded software using the emulator. | 2008-10-30 |
20080270841 | Test case manager - The test case manager interfaces with an application under test via an automation tool manager and is automation tool independent. Scripts are installed from a library based on the automation tool and the application type. The scripts perform the actions of learning the application objects, play back/validation, and automate test case creation. In a preferred embodiment, the test case manager drives the actions of the scripts. Scripts can be modified by customizing application specific actions and invoking them through the test case manager format. | 2008-10-30 |
20080270842 | COMPUTER OPERATING SYSTEM HANDLING OF SEVERE HARDWARE ERRORS - A system and method is provided for handling severe hardware errors communicated to a computer operating system as an abort indication. The method includes classifying the type of abort into a memory-related error or non-memory-related error. For memory-related errors, a debug file is written that includes error source information for an affected process without accessing the affected process memory. | 2008-10-30 |
20080270843 | CONVOLUTION-ENCODED DATA STORAGE ON A REDUNDANT ARRAY OF INDEPENDENT DEVICES - A method, system and article of manufacture for the storing convolution-encoded data on a redundant array of independent storage devices (RAID) is described. The convolution-encoded data comprises error correction coded data to eliminate the need for parity as used in conventional RAID data storage. The number of storage devices may vary to accommodate expansion of storage capacity and provide on demand storage. | 2008-10-30 |
20080270844 | SYSTEM AND METHOD FOR TRACING ACCELERATION IN AN EMBEDDED DEVICE - A system and method for tracing acceleration in an embedded device. Various embedded devices that generate debug trace output for which the usage of the processor can benefit from optimization include mobile phones, TV set-top-boxes, and networking equipment. Tracing acceleration is accomplished using a logic unit that is implemented in hardware, which thereby enables the processing of tracing data to be handled in parallel to the operation of the processor. | 2008-10-30 |
20080270845 | Methods and Apparatus That Enable a Viewer to Distinguish Different Test Data Entries and Test Data Items - In one embodiment, a plurality of test data entries are displayed via a graphical user interface (GUI). Each of the test data entries includes at least one dynamic data item that depends on an execution of at least one test for a device under test, and at least one contextual data item that provides a context for the at least one test. The dynamic data items of the test data entries are displayed using a first color scheme. The contextual data items of the test data entries are displayed using a second color scheme that differs from the first color scheme, thereby enabling a viewer to more easily distinguish the dynamic data items from the contextual data items. Other embodiments are also disclosed. | 2008-10-30 |
20080270846 | Methods and Apparatus for Compiling and Displaying Test Data Items - In one embodiment, different sets of test data items are serially compiled in, and serially read from, a data storage resource. Each of the sets of test data items corresponds to one of a plurality of defined groupings of devices under test. As the different sets of test data items are read from the data storage resource, at least a dynamically updated range of the test data items read from the data storage resource is displayed via a user interface. Before compiling a next set of test data items in the data storage resource, a previously compiled set of test data items is cleared from the data storage resource, thereby clearing any of the previously compiled set of test data items from the user interface. Other embodiments are also disclosed. | 2008-10-30 |