43rd week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110260249 | ORGANIC TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - An organic transistor includes an insulating substrate, a gate electrode on the substrate, a gate insulating layer disposed over the substrate and the gate electrode, a source and a drain electrode on the gate insulating layer, a nonpolar macromolecular insulating underlayer disposed on the gate insulating layer at least between the source electrode and the drain electrode, and an organic semiconductor layer disposed on the source electrode and the drain electrode and on the insulating underlayer between the source electrode and the drain electrode. | 2011-10-27 |
20110260250 | Method And Manufacturing Low Leakage Mosfets And FinFets - By aligning the primary flat of a wafer with a ( | 2011-10-27 |
20110260251 | Semiconductor Device and Method of Fabricating Same - A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated. | 2011-10-27 |
20110260252 | USE OF EPITAXIAL NI SILICIDE - An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures. | 2011-10-27 |
20110260253 | SEMICONDUCTOR DEVICE - A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET. | 2011-10-27 |
20110260254 | SEMICONDUCTOR DEVICES HAVING SLIT WELL TUB - An electrostatic discharge semiconductor device can include a first conductivity type substrate that includes inner first conductivity type wells therein and a plurality of gate electrodes that are on an active region of the substrate. A second conductivity type well can be located in the substrate beneath the plurality of gate electrodes including at least one slit therein providing electrical contact between the inner first conductivity type wells and a first conductivity type outer well outside the active region. | 2011-10-27 |
20110260255 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiO | 2011-10-27 |
20110260256 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced. | 2011-10-27 |
20110260257 | High Performance Non-Planar Semiconductor Devices with Metal Filled Inter-Fin Gaps - A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels. | 2011-10-27 |
20110260258 | FIELD EFFECT TRANSISTOR DEVICE WITH IMPROVED CARRIER MOBILITY AND METHOD OF MANUFACTURING THE SAME - The devices are manufactured by replacement gate process and replacement sidewall spacer process, and both tensile stress in the channel region of NMOS device and compressive stress in the channel region of PMOS device are increased by forming a first stress layer with compressive stress in the space within the first metal gate layer of NMOS and a second stress layer with tensile stress in the space within the second metal gate layer of PMOS, respectively. After formation of the stress layers, sidewall spacers of the gate stacks of PMOS and NMOS devices are removed so as to release stress in the channel regions. In particular, stress structure with opposite stress may be formed on sidewalls of the gate stacks of the NMOS device and PMOS device and on a portion of the source region and the drain region, in order to further increase both tensile stress of the NMOS device and compressive stress of the PMOS device. | 2011-10-27 |
20110260259 | SEMICONDUCTOR DEVICE - The CMOS inverter coupled circuit is composed of CMOS inverters using SGTs and series-connected in two or more stages. Multiple CMOS inverters share source diffusion layers on a substrate. The CMOS inverters different in the structure of a contact formed on gate wires are alternately arranged next to each other. The CMOS inverters are provided at the minimum intervals. The output terminal of a CMOS inverter is connected to the wiring layer of the next-stage CMOS inverter via the contact of the next-stage CMOS inverter. | 2011-10-27 |
20110260260 | SEMICONDUCTOR DEVICE HAVING AN ANNULAR GUARD RING - A semiconductor chip | 2011-10-27 |
20110260261 | CMOS Devices having Dual High-Mobility Channels - A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (MOS) device. The step of forming the first MOS device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric. The step of forming the second MOS device includes forming a second silicon germanium layer over the second region of the semiconductor substrate; forming a second gate dielectric layer over the second silicon germanium layer with no substantially pure silicon layer therebetween; and patterning the second gate dielectric layer to form a second gate dielectric. | 2011-10-27 |
20110260262 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices. | 2011-10-27 |
20110260263 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material. | 2011-10-27 |
20110260264 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation. According to the present invention, it is possible not only to reduce the gate resistance, but also to eliminate difficulties in forming contact holes by RIE at the gate and source/drain regions. | 2011-10-27 |
20110260265 | BONDED WAFER SUBSTRATE FOR USE IN MEMS STRUCTURES - A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate. A dielectric layer is formed on the first main surface of the semiconductor substrate and the second semiconductor substrate is disposed on the dielectric layer opposite to the first semiconductor substrate. The second main surface of the second semiconductor substrate contacts the dielectric layer. | 2011-10-27 |
20110260266 | SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGE PROCESS - A semiconductor package structure and a package process are provided, wherein a lower surface of a die pad of a leadframe is exposed by an encapsulant so as to improve the heat dissipation efficiency of the semiconductor package structure. In addition, two chips are disposed at the same sides of the leadframe and the end portion of each of leads bonding to the upper chip is encapsulated by the encapsulant such that the scratch on the lead tips in wire bonding and die attach steps can be prevented and thus the wire bondability can be enhanced. | 2011-10-27 |
20110260267 | MEMS DEVICES AND FABRICATION THEREOF - A MEMS device and method, comprising: a substrate; a beam; and a cavity located therebetween; the beam comprising a first beam layer and a second beam layer, the first beam layer being directly adjacent to the cavity, the second beam layer being directly adjacent to the first beam layer; the first beam layer comprising a metal or a metal alloy containing silicon; and the second beam layer comprising a metal or a metal alloy substantially not containing silicon. Preferably the second beam layer is thicker than the first beam layer e.g. at least five times thicker, and the first beam layer comprises a metal or alloy containing between 1% and 2% of silicon. The second beam layer provides desired mechanical and/or optical properties whilst the first beam layer prevents spiking. | 2011-10-27 |
20110260268 | Micro-Electro-Mechanical System Device and Method for Making Same - According to the present invention, a micro-electro-mechanical system (MEMS) device comprises: a thin film structure including at least a metal layer and a protection layer deposited in any order; and a protrusion connected under the thin film structure. A preferred thin film structure includes at least a lower protection layer, a metal layer and an upper protection layer. The MEMS device for example is a capacitive MEMS acoustical sensor. | 2011-10-27 |
20110260269 | PIEZORESISTIVE PRESSURE SENSOR - A piezoresistive pressure sensor is provided, which can prevent the occurrence of ESD breakdown due to the nearness of interconnection layers of a resistive element according to miniaturization thereof. The piezoresistive pressure sensor is so configured that respective semiconductor resistive layers on both sides of an arrangement are formed to be relatively longer than an adjacent semiconductor resistive layer, and thus a corner portion of a semiconductor connection layer that extends from the respective semiconductor resistive layers on both sides of the arrangement and a corner portion of the semiconductor interconnection layer that is nearest to the corner portion of the semiconductor connection layer, between which the ESD breakdown occurs easily, can be separated from each other. | 2011-10-27 |
20110260270 | MR enhancing layer (MREL) for spintronic devices - The performance of an MR device has been improved by inserting one or more Magneto-Resistance Enhancing Layers (MRELs) into approximately the center of one or more of the active layers (such as API, SIL, FGL, and Free layers). An MREL is a layer of a low band gap, high electron mobility semiconductor such as ZnO or a semimetal such as Bi. | 2011-10-27 |
20110260271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device causing less peeling between an insulating film having on the top surface thereof a strap line and a wiring formed on the bottom surface of the insulating film, and a manufacturing method of the semiconductor device. The semiconductor device according to the invention has a semiconductor substrate, first wiring layers formed over the semiconductor substrate and having a peripheral wiring and a first wiring, a second wiring layer formed over the first wiring layers and having a second wiring, and a third wiring layer formed over the second wiring layer and having a magnetic storage element. The diffusion preventive films formed over the first wiring are each comprised of a SiCN film or an SiC film and the diffusion preventive film formed over the second wiring is comprised of SiN. | 2011-10-27 |
20110260272 | Magnetic Memory Device - A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer. | 2011-10-27 |
20110260273 | MAGNETIC MEMORY DEVICE AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory cell is provided with a magnetization record layer and a magnetic tunnel junction section. The magnetization record layer is a ferromagnetic layer having a perpendicular magnetic anisotropy. The magnetic tunnel junction section is used to read data from the magnetization record layer. The magnetization record layer has a plurality of domain wall motion regions. | 2011-10-27 |
20110260274 | MAGNETIC STACK HAVING REFERENCE LAYERS WITH ORTHOGONAL MAGNETIZATION ORIENTATION DIRECTIONS - A magnetic cell includes a ferromagnetic free layer having a free magnetization orientation direction and a first ferromagnetic pinned reference layer having a first reference magnetization orientation direction that is parallel or anti-parallel to the free magnetization orientation direction. A first oxide barrier layer is between the ferromagnetic free layer and the first ferromagnetic pinned reference layer. The magnetic cell further includes a second ferromagnetic pinned reference layer having a second reference magnetization orientation direction that is orthogonal to the first reference magnetization orientation direction. The ferromagnetic free layer is between the first ferromagnetic pinned reference layer and the second ferromagnetic pinned reference layer. | 2011-10-27 |
20110260275 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are an electronic device package and a method of manufacturing the same. The electronic device package includes an electronic device including a polymer layer and a passivation layer configured to protect a device layer, a substrate assembly facing the electronic device, and a sealing ring formed in a closed loop between the electronic device and the substrate assembly and surrounding a sealing region. At least one side surface of the sealing ring contacts the polymer layer, and the sealing ring is disposed on the passivation layer. A polymer layer such as a microlens and a color filter is removed from a region provided with a sealing ring to form the sealing ring on a passivation layer, thereby making the sealing ring and joints the same height, thus preventing an electrical defect. | 2011-10-27 |
20110260276 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device in which a glass substrate is attached to a surface of a semiconductor die with an adhesive layer being interposed therebetween, it is an object to fill a recess portion of an insulation film formed on a photodiode with the adhesive layer without bubbles therein. In a semiconductor die in which an optical semiconductor integrated circuit including a photodiode having a recess portion of an interlayer insulation film in the upper portion, an NPN bipolar transistor, and so on are formed, generally, a light shield film covers a portion except the recess portion region on the photodiode and except a dicing region. In the invention, an opening slit is further formed in the light shield film, extending from the recess portion to the outside of the recess portion, so as to attain the object. | 2011-10-27 |
20110260277 | METHOD FOR MANUFACTURING A PHOTODIODE AND CORRESPONDING PHOTODIODE AND ELECTROMAGNETIC RADIATION DETECTOR - A photodiode capable of interacting with incident photons includes at least: a stack of three layers including an intermediate layer placed between a first semiconductor layer and a second semiconductor layer having a first conductivity type; and a region that is in contact with at least the intermediate layer and the second layer and extends transversely relative to the planes of the three layers, the region having a conductivity type that is opposite to the first conductivity type. The intermediate layer is made of a semiconductor material having a second conductivity type and is capable of having a conductivity type that is opposite to the second conductivity type so as to form a P-N junction with the region, inversion of the conductivity type of the intermediate layer being induced by dopants of the first conductivity type that are present in the first and second layers. | 2011-10-27 |
20110260278 | System and Method of Planar Processing of Semiconductors into Detector Arrays - An article of manufacture and a method of defining a photodetector element are provided. The article of manufacture includes a photodector element comprising a junction formed by a first III-V semiconductor layer having a first charge type and a second III-V semiconductor layer comprising a second dopant having a second charge type. The second III-V semiconductor layer is disposed between the first III-V semiconductor layer and a wafer. Patterned dopant regions having a third charge type, the third charge type being the same as the first charge type, are disposed in the first III-V semiconductor layer. | 2011-10-27 |
20110260279 | Semiconductor Device Connection - A method of bonding a semiconductor structure to a substrate to effect both a mechanical bond and a selectively patterned conductive bond, comprising the steps of mechanically bonding a semiconductor structure to a substrate by means of a bonding layer; providing gaps in the bonding layer generally corresponding to a desired conductive bond pattern; providing vias though the substrate generally positioned at the gaps in the bonding layer; causing electrically conductive material to contact the semiconductor structure exposed through the vias. A device made in accordance with the method is also described. | 2011-10-27 |
20110260280 | Back Side Defect Reduction For Back Side Illuminated Image Sensor - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystalized silicon layer is formed on the back side of the substrate. The recrystalized silicon layer has different photoluminescence intensity than the substrate. | 2011-10-27 |
20110260281 | SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES - Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band. | 2011-10-27 |
20110260282 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS - Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over fins and isolation materials and performing a multi-stage etching process to remove upper portions of the multi-layer structure and upper portions of isolation materials. Upper portions of the fins are exposed by removing the upper portions of the isolation materials via the multi-stage etching process. A stage of the multi-stage etching process removes an upper layer of the multi-layer structure and an upper portion of the isolation materials, and the stage can be terminated about at the same time when the upper surface of the underlying layer of the multi-layer structure is exposed. | 2011-10-27 |
20110260283 | DIELECTRIC COMPOSITION FOR THIN-FILM TRANSISTORS - An electronic device, such as a thin-film transistor, includes a substrate and a dielectric layer formed from a dielectric composition. The dielectric composition includes a dielectric material, a crosslinking agent, and an infrared absorbing agent. In particular embodiments, the dielectric material comprises a lower-k dielectric material and a higher-k dielectric polymer. When deposited, the lower-k dielectric material and the higher-k dielectric material form separate phases. The infrared absorbing agent allows the dielectric composition to attain a temperature that is significantly greater than the temperature attained by the substrate during curing. This difference in temperature allows the dielectric layer to be cured at relatively high temperatures and/or shorter time periods, permitting the selection of lower-cost substrate materials that would otherwise be deformed by the curing of the dielectric layer. | 2011-10-27 |
20110260284 | Method for Producing a Semiconductor Component, and Semiconductor Component - In the insulation layer ( | 2011-10-27 |
20110260285 | SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH | 2011-10-27 |
20110260286 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure. | 2011-10-27 |
20110260287 | STRUCTURE IN A HIGH VOLTAGE PATH OF AN ULTRA-HIGH VOLTAGE DEVICE FOR PROVIDING ESD PROTECTION - An ultra-high voltage device has a high voltage path established from a high voltage N-well through a first metal layer to a second metal layer, and a contact plug electrically connected between the high voltage N-well and the first metal layer. The contact plug has a distributed structure on a horizontal layout to improve the uniformity of the ultra-high voltage device such that the current in the high voltage path will be more uniform distributed so as to avoid the localized heat concentration caused by non-uniform current distribution that would damage the ultra-high voltage device. Multiple fuse apparatus are preferably connected to the first metal layer individually. Each the fuse apparatus includes a poly fuse to be burnt down when an over-load current flows therethrough. | 2011-10-27 |
20110260288 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method for manufacturing a semiconductor device comprising: a process of forming a first trench | 2011-10-27 |
20110260289 | Semiconductor device and bypass capacitor module - A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer. | 2011-10-27 |
20110260290 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided. | 2011-10-27 |
20110260291 | Semiconductor Structure - A semiconductor structure. The semiconductor comprises a substrate, a first deep well, a diode and a transistor. The first deep well is formed in the substrate. The diode is formed in the first deep well. The transistor is formed in the first deep well. The diode is connected to a first voltage, the transistor is connected to a second voltage, and the diode and the transistor are cascaded. | 2011-10-27 |
20110260292 | Bipolar Junction Transistor Having a Carrier Trapping Layer - A bipolar junction transistor having a carrier trapping layer, comprises a semi-conductor substrate including a well with a first type ions formed thereon; two impurity regions with a second type ions formed opposite with each other over the well; an insulation layer over the well, and edges extend over the second two impurity regions; and a carrier trapping layer formed over the insulation layer. | 2011-10-27 |
20110260293 | VARIABLE CAPACITANCE DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a variable capacitance device including a nanomaterial layer made of a plurality of kinds of nanomaterials having characteristics different from each other, a first conductive layer electrically connected to at least a part of the nanomaterial layer, and a second conductive layer facing the nanomaterial layer and the first conductive layer through an insulating film. | 2011-10-27 |
20110260294 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first well and a second well formed in a substrate and having a different impurity doping concentration; a first isolation layer and a second isolation layer formed in the first well and the second well, respectively, and having a different depth; and a third isolation layer formed in a boundary region in which the first well and the second well are in contact with each other, and having a combination type of the first isolation layer and the second isolation layer. | 2011-10-27 |
20110260295 | III-Nitride Crystal Substrate and III-Nitride Semiconductor Device - Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate ( | 2011-10-27 |
20110260296 | SEMICONDUCTOR WAFER AND METHOD FOR PRODUCING SAME - A semiconductor wafer ( | 2011-10-27 |
20110260297 | THROUGH-SUBSTRATE VIA AND FABRICATION METHOD THEREOF - A method for fabricating a through-substrate via structure. A semiconductor substrate is provided. A first via hole is etched into the semiconductor substrate. A spacer is formed on sidewall of the first via hole. The semiconductor substrate is etched through the first via hole to form a second via hole. The second via hole is wet etched to form a bottle-shaped via hole. An insulating layer is formed lining a lower portion of the bottle-shaped via hole. A first conductive layer is deposited within the bottle-shaped via hole, wherein the first conductive layer define a cavity. A bond pad is formed on a front side of the semiconductor substrate, wherein the bond pad is electrically connected with the first conductive layer. A back side of the semiconductor substrate is polished to reveal the cavity. The cavity is filled with a second conductive layer. | 2011-10-27 |
20110260298 | SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON AND METHOD OF FORMING SAME - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction. | 2011-10-27 |
20110260299 | METHOD FOR VIA PLATING IN ELECTRONIC PACKAGES CONTAINING FLUOROPOLYMER DIELECTRIC LAYERS - A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA. | 2011-10-27 |
20110260300 | Wafer-Bump Structure - A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer. | 2011-10-27 |
20110260301 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 2011-10-27 |
20110260302 | SHIELDING DEVICE - One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit. | 2011-10-27 |
20110260303 | Semiconductor Device and Method of Forming Openings in Thermally-Conductive Frame of FO-WLCSP to Dissipate Heat and Reduce Package Height - A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame. | 2011-10-27 |
20110260304 | LEADFRAME FOR ELECTRONIC COMPONENTS - The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe. | 2011-10-27 |
20110260305 | Power Semiconductor Device Packaging - A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity. | 2011-10-27 |
20110260306 | LEAD FRAME PACKAGE STRUCTURE FOR SIDE-BY-SIDE DISPOSED CHIPS - A lead frame package structure for side-by-side disposed chips including a lead frame, at least two chips, and a package material. The lead frame includes a plurality of inner leads; a plurality of outer leads; and at least two chip carrying areas having different horizontal levels. The chips are of different sizes and are respectively disposed on the chip carrying areas. The package material encapsulate the inner leads, the chip carrying areas and the chips, wherein the outer leads exposed out of the package material extend from the inner leads and have different horizontal levels. | 2011-10-27 |
20110260307 | INTEGRATED CIRCUIT INCLUDING BOND WIRE DIRECTLY BONDED TO PAD - An integrated circuit includes a chip including a copper bond pad metallization, and a copper bond wire including a copper ball. The copper ball is bonded directly to the copper bond pad. | 2011-10-27 |
20110260308 | CIRCUIT BOARD STRUCTURE, PACKAGING STRUCTURE AND METHOD FOR MAKING THE SAME - A circuit board structure, a packaging structure and a method for making the same are disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure. | 2011-10-27 |
20110260309 | SEMICONDUCTOR PACKAGE, TEST SOCKET AND RELATED METHODS - Provided are a socket, a semiconductor package, a test device and a method of manufacturing a semiconductor package. A socket to test a semiconductor package comprising a housing, a trench receiving a semiconductor package in the housing, at least one probe connected to the semiconductor package at a bottom of the trench, and at least one connector electrically connecting a plurality of contact points exposed at a side of the semiconductor package when the semiconductor package is inserted into the trench. A semiconductor package with contacts exposed from a side of a package substrate, and a method of manufacturing such a semiconductor package are also disclosed. | 2011-10-27 |
20110260310 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a quad flat non-leaded (QFN) package includes: forming die pads and bump solder pads by pressing a metal plate, wherein each of the die pads and the bump solder pads has at least a cross-sectional area greater than another located underneath along its thickness dimension, thereby enabling the die pads and the solder pads to be securely embedded in an encapsulant. The method further includes removing the metal plate after forming the encapsulant so as to prevent the encapsulant from overflowing onto the bottom surfaces of the bump solder pads. | 2011-10-27 |
20110260311 | RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame. | 2011-10-27 |
20110260312 | SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME - A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. | 2011-10-27 |
20110260313 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED ENCAPSULATION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a carrier; mounting an integrated circuit die on a top side of the carrier; connecting the integrated circuit die with the carrier; forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress; and forming a first external interconnect on the top side of the carrier adjacent to and separated from the encapsulation including forming a second external interconnect on a bottom side of the carrier opposite the first external interconnect. | 2011-10-27 |
20110260314 | DIE PACKAGE AND CORRESPONDING METHOD FOR REALIZING A DOUBLE SIDE COOLING OF A DIE PACKAGE - A die package is provided, including a die positioned on and in direct contact with a first heat sink element, and also including a package case and leads made of conductive material, protruding from the package case. The die package further includes a second heat sink element shaped as a spring element, in contact between the die and the leads, and emerging from a side of the package case opposite the first heat sink element. | 2011-10-27 |
20110260315 | POWER BLOCK AND POWER SEMICONDUCTOR MODULE USING SAME - A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern. | 2011-10-27 |
20110260316 | Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process - A semiconductor device has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer. | 2011-10-27 |
20110260317 | CU PILLAR BUMP WITH ELECTROLYTIC METAL SIDEWALL PROTECTION - A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer. | 2011-10-27 |
20110260318 | Integrated circuits with multiple I/O regions - Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages. | 2011-10-27 |
20110260319 | THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection. | 2011-10-27 |
20110260320 | METHOD OF MAKING A CONNECTION COMPONENT WITH POSTS AND PADS - A packaged microelectronic element includes connection component incorporating a dielectric layer ( | 2011-10-27 |
20110260321 | Flip Chip Interconnection Structure - A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock | 2011-10-27 |
20110260322 | "Semiconductor on semiconductor substrate multi-chip-scale package" - Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT. | 2011-10-27 |
20110260323 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 2011-10-27 |
20110260324 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE - A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers. | 2011-10-27 |
20110260325 | SEMICONDUCTOR DEVICE - To provide a semiconductor device including vertically formed nanowires in which parasitic capacitance is prevented from increasing and time constant associated with an operation speed is improved. Two different layers, which are a film thickness adjustment layer and a protective insulating layer, are provided as an interlayer insulating film between an electrode and a planar main surface of an electrically conductive substrate. This structural characteristic can reduce parasitic capacitance generated among the nanowires which electrically connect the planar main surface and the electrode to each other, the electrically conductive substrate, and the electrode, while controlling peel-off of a low dielectric film having a poor adhesion by separating the low dielectric film from the electrode with the protective insulating layer interposed therebetween. | 2011-10-27 |
20110260326 | STRUCTURES AND METHODS FOR AIR GAP INTEGRATION - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 2011-10-27 |
20110260327 | CHIP PACKAGE - A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided. | 2011-10-27 |
20110260328 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING USING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a plurality of bit lines having a uniform width on a semiconductor substrate, an active region obliquely arranged to have a predetermined angle with respect to the bit lines, a spacer arranged around the bit lines connected to a center part of the active region. A contact pad is connected to a lower part of the bit lines. The spacer is formed not only at an upper part of sidewalls of the contact pad but also at sidewalls of the bit lines. As a result, a CD of the bit line contact increases, so that a bit line contact patterning margin also increases. A bit line pattern having a uniform width is formed so that a patterning margin increases. A storage electrode contact self-alignment margin increases so that a line-type storage electrode contact margin increases. | 2011-10-27 |
20110260329 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a through-chip via passing through a semiconductor chip, and an insulator arranged inside the through-chip via to electrically divide the through-chip via. Here, the divided through-chip vias may transmit different signals. | 2011-10-27 |
20110260330 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a semiconductor chip. The semiconductor chip includes a well arranged to receive a first well bias voltage from a well biasing region, a through-chip-via arranged to penetrate the well, and a guard region disposed around the through-chip-via with space in-between and arranged to apply a second well bias voltage to the well. | 2011-10-27 |
20110260331 | STACKED SEMICONDUCTOR DEVICE - Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip. | 2011-10-27 |
20110260332 | MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME - A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via. | 2011-10-27 |
20110260333 | INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced. | 2011-10-27 |
20110260334 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer. | 2011-10-27 |
20110260335 | POWER SUPPLY INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT - A power supply interconnect structure of a semiconductor integrated circuit includes a single borderless stack via electrically connecting power supply interconnects of two different interconnect layers to form a connecting portion of the interconnects, and a multi-stack via functioning as another connecting portion of the interconnects, which electrically connect the power supply interconnects, and having a wide pad portion. The single borderless stack via is located in an interconnect region with high signal interconnect density. The multi-stack via is located in an interconnect region with low signal interconnect density. This increases interconnection efficiency in the region with the high signal interconnect density to improve interconnection characteristics. This enables reduction in an area of a chip and increases compatibility to an EDA tool, thereby improving IR-DROP characteristics. | 2011-10-27 |
20110260336 | WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized. | 2011-10-27 |
20110260337 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor chip | 2011-10-27 |
20110260338 | Semiconductor Device and Method of Forming Adjacent Channel and DAM Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material - A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel. | 2011-10-27 |
20110260339 | SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting board having a protection film thereon; a semiconductor chip provided on the supporting board; a first internal connecting terminal formed on the supporting board; a second internal connecting terminal formed on the semiconductor chip; a first insulation layer for covering an upper surface of the supporting board and upper and lateral surfaces of the semiconductor chip; a wiring pattern provided on the first insulation layer, the wiring pattern connecting the first and second internal connecting terminals; a solder resist layer provided on the first insulation layer and the wiring pattern, the solder resist layer having an opening part; an external connecting terminal provided so as to connect to the wiring pattern through the opening part; a groove part formed on outer peripheries of the supporting board, the protection film, and the first insulation layer; and a resin layer formed in the groove part. | 2011-10-27 |
20110260340 | CIRCUIT BOARD STRUCTURE, PACKAGING STRUCTURE AND METHOD FOR MAKING THE SAME - A method for making a circuit board structure is disclosed. First, a substrate is provided. The substrate includes a carrier, a copper film and a release film disposed between them. Next, the copper film is patterned to form a connecting pattern and a die pad. Later, a passivation layer is formed to cover the connecting pattern and the die pad. | 2011-10-27 |
20110260341 | Power switch component having improved temperature distribution - A power switch component having a semiconductor switch and a contacting applied to a contact zone of the semiconductor switch is introduced. The contact zone has a semiconductor layer and a metal plating applied to the semiconductor layer. The semiconductor layer has at least one conducting region and at least one non-conducting region situated directly under the metal plating. | 2011-10-27 |
20110260342 | RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Disclosed is a granular resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, satisfying the following requirements (a) to (c) on condition that ion viscosity is measured with a dielectric analyzer under a measurement temperature of 175° C. and a measurement frequency of 100 Hz:
| 2011-10-27 |
20110260343 | POLYMERIC COMPOSITIONS COMPRISING PER(PHENYLETHYNYL) ARENE DERIVATIVES - A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar | 2011-10-27 |
20110260344 | Liquid and Gas Mixing Cartridge - Embodiments of the invention provide a carbonation system or gas delivery system including a liquid inlet, a gas inlet, a mixture outlet, and a mixing cartridge or membrane module. The mixing cartridge or membrane module can enhance the simultaneous absorption of gas and the transfer of heat out of the liquid. | 2011-10-27 |
20110260345 | METHOD FOR FORMING IMAGE SENSING DEVICE - A method for forming an image sensing device is disclosed, including providing a molding apparatus, disposing a lens in the molding apparatus, injecting an injection material into a chamber of the molding apparatus to form a shell which is connected to the lens, opening the chamber of the molding apparatus to remove the lens and the shell connected to the lens, and assembling the shell with an image sensing element. | 2011-10-27 |
20110260346 | METHOD OF MANUFACTURING LIGHT GUIDE PLATE OF KEYPAD - A method of manufacturing a light guide plate containing a plurality of light-guiding micro structures comprises the steps of: preparing a mold that has a concave hole formed by a plurality of light-guiding micro structures; pouring a mixture of ultraviolet curable resins and glass microbeads into the mold; attaching a carrier onto the mixture; using a rolling tool to roll the surface of the carrier, such that the mold is filled up with the mixture uniformly, while the air among the mold, the carrier and the mixture is discharged; and finally projecting the ultraviolet light onto the ultraviolet curable resin, such that the ultraviolet curable resin can be cured at the carrier and removed from the mold, so as to form a light guide plate having a plurality of light-guiding micro structures. | 2011-10-27 |
20110260347 | METHOD FOR PRODUCING LIPOSOMAL DRUGS AND A DEVICE FOR PRODUCING A LIPOSOME - The essence of the invention is that an aqueous medium is mixed with a lipid component (lipid solution in an organic solvent) by the ejecting introduction (suction) of the lipid component (lipid solution in an organic solvent) into an ejector mixing chamber in the form of a de Laval nozzle by means of the energy from a pressurized jet of the aqueous medium flowing out of the inlet nozzle of the ejector, which jet creates a pressure drop in the convergent part (confuser) of the mixing chamber, wherein an aerosol stream of liposome is formed at the outlet of the divergent part (diffuser) of the mixing chamber. | 2011-10-27 |
20110260348 | METHOD FOR DRYING CELLULOSE NANOFIBRILS - A method of producing dried cellulose nanofibrils includes atomizing an aqueous suspension of cellulose nanofibrils and introducing the atomized aqueous suspension into a drying chamber of a drying apparatus. The aqueous suspension is then dried, thereby forming substantially non-agglomerated dried cellulose nanofibrils. | 2011-10-27 |