43rd week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140312346 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode. | 2014-10-23 |
20140312347 | SEMICONDUCTOR DEVICE - Adverse effects of variation in threshold voltage are reduced. In a semiconductor device, electric charge is accumulated in a capacitor provided between a gate and a source of a transistor, and then, the electric charge accumulated in the capacitor is discharged; thus, the threshold voltage of the transistor is obtained. After that, current flows to a load. In the semiconductor device, the potential of one terminal of the capacitor is set higher than the potential of a source line, and the potential of the source line is set lower than the potential of a power supply line and the cathode side potential of the load. | 2014-10-23 |
20140312348 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole. | 2014-10-23 |
20140312349 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF AND ARRAY SUBSTRATE INCLUDING THE THIN FILM TRANSISTOR - An embodiment of the present invention provides a thin film transistor and a manufacturing method thereof and an array substrate comprising the thin film transistor. The method comprises: depositing an amorphous layer on a substrate, and patterning the amorphous layer so as to form an active layer comprising a source region, a drain region and a channel region; forming a gate insulating layer and a gate electrode above the channel region; depositing an induction metal layer on the substrate on which the gate electrode is formed; doping impurity into the source region and the drain region by an ion implanting process and bombarding part of the induction metal into the source region and the drain region; removing the induction metal layer; performing a thermal treatment to the doped active layer so that the impurity is activated and the metal induced crystallization and the metal induced lateral crystallization occur in the active layer due to the induction metal, converting the amorphous silicon to polysilicon in the source region, the drain region and the channel region of the active layer; and forming a source electrode and a drain electrode. | 2014-10-23 |
20140312350 | Large Area Ultrasonic Receiver Array - Devices and methods of creating an image of a biological object are disclosed. In one embodiment of the invention there is a plane wave ultrasonic pulse generator, an ultrasonic wave manipulation device, an ultrasonic detector and an image generator. In a method according to the invention, a biological object is imaged by emitting an unfocussed ultrasonic energy wave front, reflecting at least a portion of the ultrasonic energy wave front from the object, altering a direction of the ultrasonic energy, detecting that energy, and using the detected energy to create an image of the object. | 2014-10-23 |
20140312351 | TFT SUBSTRATE AND METHOD FOR CORRECTING WIRING FAULT ON TFT SUBSTRATE - A TFT substrate is provided in which a wire defect can be easily solved. A method of solving a wire defect in the TFT substrate is also provided. In an embodiment, the TFT substrate is configured so that (i) a plurality of gate lines and a plurality of source lines are arranged in a matrix manner, (ii) a TFT is provided in at least one of intersection regions where the plurality of gate lines and the plurality of source lines intersect with each other, and (iii) the at least one of intersection regions is divided by a slit, which is formed in a corresponding one of the plurality of gate lines, so that the at least intersection region is divided into parts arranged along a longitudinal direction of the plurality of source lines. | 2014-10-23 |
20140312352 | SEMICONDUCTOR DEVICE, ELECTRO-OPTICAL DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - A lower insulation layer includes a concave portion that has a back surface on a first base member side, first to third surfaces which are opposed to the back surface, a fourth surface which is arranged between the first surface and the third surface, and a fifth surface which is arranged between the second surface and the third surface. A semiconductor layer is arranged on the first surface and the second surface. A gate electrode is arranged so as to be opposed to the semiconductor layer on at least the third surface, the fourth surface, and the fifth surface via a gate insulation layer. | 2014-10-23 |
20140312353 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material. | 2014-10-23 |
20140312354 | ACTIVE MATRIX SUBSTRATE - The lateral electric field liquid crystal display device ( | 2014-10-23 |
20140312355 | METHOD OF FABRICATING A MERGED P-N JUNCTION AND SCHOTTKY DIODE WITH REGROWN GALLIUM NITRIDE LAYER - A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer. | 2014-10-23 |
20140312356 | Semiconductor Device - A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base. | 2014-10-23 |
20140312357 | SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with a underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1>=7, where L=the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; d1 the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer. | 2014-10-23 |
20140312358 | NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES - A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride. | 2014-10-23 |
20140312359 | METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES - A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate. | 2014-10-23 |
20140312360 | Semiconductor Power Device Having a Heat Sink - A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block. | 2014-10-23 |
20140312361 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT - The semiconductor element has an electrode including: a Ni-inclusion metal layer containing nickel formed on a side of at least one surface of the semiconductor-element constituting part; a Ni-barrier metal layer formed outwardly on a side of the Ni-inclusion metal layer opposite to the side toward the semiconductor-element constituting part; and a surface metal layer outwardly formed on a side of the Ni-barrier metal layer opposite to the side toward the semiconductor-element constituting part, to be connected to the metal nanoparticles sintered layer; wherein the Ni-barrier metal layer contains a metal for suppressing diffusion of nickel toward the surface metal layer. | 2014-10-23 |
20140312362 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure of nitride over the substrate; a passivation film that covers the compound semiconductor stacked structure; a gate electrode, a source electrode, and a drain electrode at a level above the compound semiconductor stacked structure; and an Si—C bond containing film that contains an Si—C bond and includes a part between the source electrode and the drain electrode. The part contacts at least a part of an upper surface of the compound semiconductor stacked structure or at least a part of an upper surface of the passivation film. | 2014-10-23 |
20140312363 | FLAT PANEL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A flat panel display device and a manufacturing method thereof are provided. The flat panel display device includes: a display unit on a substrate; and a sealing structure on the substrate covering the display unit to seal the display unit, the sealing structure including at least one first layer including an inorganic material and at least one second layer including an organic material. The sealing structure includes at least one micro gap, and the micro gap includes an identification material including a fluorescent substance or a dye. | 2014-10-23 |
20140312364 | PACKAGE FOR LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE - A package for a light emitting device includes: a resin portion having a sidewall thereof; a first lead having a reflective layer containing silver, the first lead being embedded in the resin portion such that the reflective layer is exposed inside the sidewall; and a second lead having at least a part of a surface thereof exposed inside the sidewall, the second lead being embedded in the resin portion while being isolated from the first lead, wherein in the first lead, the reflective layer is provided spaced inward apart from a boundary between the first lead and the resin portion, and wherein a separating surface exposed between the boundary and the reflective layer is formed of a surface of metal containing silver in a smaller amount than that of the reflective layer. | 2014-10-23 |
20140312365 | ALTERNATING CURRENT LIGHT-EMITTING DEVICE - The alternating current light-emitting device includes: a light-emitting module having a substantially-transparent molded piece, three or more LEDs disposed so as to be linearly lined up on the substantially-transparent molded piece with a lead frame interposed therebetween and connected in series, and a resin member formed so as to cover each of the LEDs in a direction in which the LEDs are lined up; a main substrate including the light-emitting module disposed on a front surface thereof; and a rectifier element and a current-limiting element provided on the main substrate. | 2014-10-23 |
20140312366 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR FABRICATING THE SAME - An LED package allows a fluorescent material to be uniformly distributed around an LED chip on a base when a filling space inside a transparent wall surrounding the LED chip is filled with the fluorescent material. The LED package includes a base, at least one LED chip mounted on the base, a transparent wall formed on the base and having a filling space around the LED chip, and a fluorescent material, with which the filling space is filled to cover the LED chip. | 2014-10-23 |
20140312367 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING SAME - A Light Emitting Diode (LED) package comprises a Printed Circuit Board (PCB), an LED mounted on the PCB, a pillar placed higher than the LED around the LED on the PCB, a transparent plate disposed on the pillar, spaced apart from the LED, and configured to transmit light emitted from the LED, and a fluorescent layer formed on a surface of the transparent plate, facing the LED, and conformably coated with a substance for converting a wavelength of the light emitted from the LED, wherein an electrical pad of the LED and an electrical pad of the PCB are electrically connected to each other, and the LED and the fluorescent layer are spaced apart from each other. | 2014-10-23 |
20140312368 | LED DISPLAY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a LED display is provided. A temporary substrate is provided, wherein the temporary substrate has a first adhesive layer and a plurality of first, second and third LED chips mounted on the first adhesive layer. A first transparent substrate is provided, the transparent substrate has a plurality of pixels disposed thereon, and each of the pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel respectively surrounded by a light-insulating structure. Then, the temporary substrate and the first transparent substrate are bonded together, such that each of the first, second and third LED chips is correspondingly mounted in each of the first sub-pixels, the second sub-pixels and the third sub-pixels. After that, the temporary substrate is removed. A LED display manufactured by said method is also provided. | 2014-10-23 |
20140312369 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a first electrode connected to the first conductivity type semiconductor layer; a second electrode including a contact layer connected to the second conductivity type semiconductor layer, a capping layer disposed on the contact layer, and a metal buffer layer disposed on the capping layer, the metal buffer layer encompasses an upper and lateral surface of the capping layer; a first insulating layer disposed on the light emitting structure such that the first and second electrodes are exposed; and a second insulating layer disposed on the first insulating layer such that at least a portion of the first electrode and at least a portion of the metal buffer layer are exposed. | 2014-10-23 |
20140312370 | OPTOELECTRONIC DEVICE - An optoelectronic device comprising a first semiconductor layer having a first lattice constant; a second semiconductor layer having a second lattice constant, wherein the second lattice constant is smaller than the first lattice constant; and a first buffer layer formed between the first semiconductor layer and the second semiconductor layer, wherein a lattice constant of one side of the first buffer layer near the second semiconductor layer is smaller than the second lattice constant. | 2014-10-23 |
20140312371 | HYBRID REFLECTOR CUP - A package for a light source and methods of manufacturing the same are disclosed. In particular, a light source package is disclosed with an outer component and an interchangeable inner component. The inner component can be modular and replaceable with other inner components having different properties, thereby enabling a flexible design of a light source package to accommodate different lighting conditions and desired lighting effects. | 2014-10-23 |
20140312372 | SEMICONDUCTOR OPTICAL EMITTING DEVICE WITH GROOVED SUBSTRATE PROVIDING MULTIPLE ANGLED LIGHT EMISSION PATHS - A semiconductor optical emitting device comprises an at least partially transparent substrate and an active semiconductor structure arranged on a first side of the substrate. A first portion of light generated by the active semiconductor structure is emitted through the substrate from the first side of the substrate to a second side of the substrate along a primary light emission path. The second side of the substrate has a groove formed therein with at least first and second surfaces configured to reflect respective additional portions of the light generated by the active semiconductor structure along respective first and second angled light emission paths. The first and second angled light emission paths may be in opposite directions to one another and substantially perpendicular to the primary light emission path, although numerous other light emission path arrangements are possible. | 2014-10-23 |
20140312373 | LIGHT EMITTING DIODES HAVING GROUP III NITRIDE SURFACE FEATURES DEFINED BY A MASK AND CRYSTAL PLANES - An LED includes a mesa having a Group III Nitride mesa face and a mesa sidewall, on an underlying LED structure. The mesa face includes Group III Nitride surface features having tops that are defined by mask features, having bottoms, and having sides that extend along crystal planes of the Group III Nitride. The mask features may include a two-dimensional array of dots that are spaced apart from one another. Related fabrication methods are also disclosed. | 2014-10-23 |
20140312374 | Method for Forming Projections and Depressions, Sealing Structure, and Light-Emitting Device - A novel method for forming projections and depressions is provided. A novel sealing structure is provided. A novel light-emitting device is provided. A first step of forming a film containing at least two kinds of metals having different etching rates over a surface; a second step of heating the film so that the metal having a lower etching rate segregates; a third step of selectively etching the metal having a higher etching rate; and a fourth step of selectively etching the surface using a residue containing the metal having a lower etching rate are included. | 2014-10-23 |
20140312375 | Method for producing an optoelectronic assembly and optoelectronic assembly - A method for producing an optoelectronic assembly ( | 2014-10-23 |
20140312376 | Semiconductor Light Emitting Devices Including Red Phosphors that Exhibit Good Color Rendering Properties and Related Red Phosphors - A light emitting device includes a light emitting diode (“LED”) that emits light having a dominant wavelength in the blue color range, and a recipient luminophoric medium that is configured to down-convert at least some of the light emitted by the LED. The recipient luminophoric medium includes a green phosphor that down-converts the radiation emitted by the LED to radiation having a peak wavelength that is between about | 2014-10-23 |
20140312377 | OPTOELECTRONIC APPARATUSES WITH POST-MOLDED REFLECTOR CUPS - An optoelectronic apparatus includes one or more packaged optoelectronic semiconductor devices (POSDs), each including one or more optoelectronic elements encapsulated by a light transmissive molding compound. Each POSD includes a top surface formed by a top surface of the light transmissive molding compound that encapsulates the one or more optoelectronic elements of the POSD. Each POSD also includes a bottom surface including electrical contacts for the one or more optoelectronic elements of the POSD. A peripheral surface extends between the top and bottom surfaces. A light reflective molding compound surrounds the peripheral surface of each POSD and forms a reflector cup for each POSD. The electrical contacts on the bottom surface of each POSD are exposed, and thus, are accessible for electrical connections to other circuitry. Where the optoelectronic apparatus includes a plurality of POSDs, the light reflective molding compound also connects neighboring POSDs to one another. | 2014-10-23 |
20140312378 | LED module packaging structure with an IC chip - An improved LED module packaging structure with an IC chip includes a power input end in a packaging groove of a carrier stand connected to a zener diode and a power input port of the IC chip acquiring an operating power from the zener diode, so that the LED module applied to a full-color or self-color illuminant of central control utilizes the zener diode connected to the power input end within the packaging groove of the carrier stand to lower or modulate the voltage of an external power. While the IC chip receives a data signal from the data signal input end, the IC chip receives a matched operating voltage via the zener diode to drive the LED chip to shine, thereby attaining a long transmission of the central control easily. | 2014-10-23 |
20140312379 | LIGHT-EMITTING DIODE WITH SIDE-WALL BUMP STRUCTURE AND MOUNTING STRUCTURE HAVING THE SAME - A light-emitting diode (LED) with a bump structure on a sidewall is provided. The LED comprises a substrate, an epitaxial structure, a first conductive bump, a second conductive bump, a first extended electrode and a second extended electrode. The substrate has a top surface, a first side surface and an inclined surface between the top surface and the first side surface. The epitaxial structure is disposed on the top surface of the substrate, and comprises a N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a transparent conductive layer, a P-electrode and a N-electrode. The first extended electrode and the second extended electrode connect the P-electrode and the N-electrode, extend through the inclined surface, and are electrically connected to the first and the second conductive bumps, respectively. A mounting structure comprises said LED, a sub-mount and a connector mounting the LED onto the sub-mount. | 2014-10-23 |
20140312380 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes. | 2014-10-23 |
20140312381 | NANOELECTRONIC STRUCTURE AND METHOD OF PRODUCING SUCH - The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact. | 2014-10-23 |
20140312382 | POWER DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a power device having an improved field stop layer and a method of manufacturing the same. The power device includes: a first field stop layer formed of a semiconductor substrate and of a first conductive type; a second field stop layer formed on the first field stop layer and of the first conductive type, the second field stop layer having a region with an impurity concentration higher than the first field stop layer; a drift region formed on the second field stop layer and of the first conductive type, the drift region having an impurity concentration lower than the first field stop layer; a plurality of power device cells formed on the drift region; and a collector region formed below the first field stop layer, wherein the second field stop layer includes a first region having a first impurity concentration and a second region having a second impurity concentration higher than the first impurity concentration. | 2014-10-23 |
20140312383 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench. | 2014-10-23 |
20140312384 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first base layer of a first conductivity type formed on a semiconductor layer, a second base layer of a second conductivity type formed on a first surface of the first base layer, an emitter layer formed on the second base layer, a collector layer of the second conductivity type formed above the first base layer, and a barrier layer of the first conductivity type formed between the first base layer and the second base layer. The barrier layer has a depth from the first surface that is shallower than a depth of the second base layer from the first surface and a dopant concentration that is higher than a dopant concentration of the first base layer. The semiconductor device further includes an insulating film formed on the second base layer and a gate electrode formed on the insulating film. | 2014-10-23 |
20140312385 | ELECTRONIC ELEMENTS BASED ON QUASITWO-DIMENSIONAL ELECTRON/HOLE GAS AT CHARGED DOMAIN WALLS IN FERROELECTRICS - The present invention relates to a device including a ferroic material having a ferroelectric order parameter and including at least two domains, as well as a first and second electrode in electrical contact with the ferroic material. The device is configured to form a head-to-head polarization orientation or a tail-to-tail polarization orientation at an interface between the two domains to form a charged domain wall at said interface and between the first and second electrodes. The present invention relates to a corresponding method for operating such a device. | 2014-10-23 |
20140312386 | OPTOELECTRONIC DEVICE HAVING PHOTODIODES FOR DIFFERENT WAVELENGTHS AND PROCESS FOR MAKING SAME - An optoelectronic device includes: a substrate made of a first material; a region in the substrate, the region being made of a second material different from the first material; an N-well in the region made of the second material; and a photo diode formed in the region by ion implantation. The second material for example is silicon germanium (Si | 2014-10-23 |
20140312387 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a base layer of a group III-V compound, a channel layer disposed on the base layer and including a group IV element, a nitride layer disposed on the channel layer, a gate insulation layer disposed on the nitride layer and a gate electrode disposed on the gate insulation layer. The concentration of nitrogen atoms existing at a first interface between the nitride layer and the gate insulation layer is higher than that existing at a second interface between the nitride layer and the channel layer. | 2014-10-23 |
20140312388 | Apparatus and Method for Forming Semiconductor Contacts - A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure. | 2014-10-23 |
20140312389 | Reacted Conductive Gate Electrodes and Methods of Making the Same - A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material. | 2014-10-23 |
20140312390 | Layout Structure of Heterojunction Bipolar Transistors - A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved. | 2014-10-23 |
20140312391 | IMAGE SENSOR - An image sensor includes a first sub-gate in a recessed region in a substrate; a second sub-gate on the first sub-gate in contact with an upper surface of the substrate; and an element isolation region in the substrate spaced apart from the first sub-gate. A lower surface of the second sub-gate is wider than an upper surface of the first sub-gate, and a portion of the element isolation region is spaced apart from the second sub-gate by a first distance in a first direction. | 2014-10-23 |
20140312392 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, METHOD OF DRIVING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of pixels, each of which includes a photoelectric converter section formed on a first substrate to generate and accumulate signal charges corresponding to incident light, a charge accumulation capacitor section formed on the first substrate or a second substrate to temporarily hold the signal charges transferred from the photoelectric converter section, and a plurality of MOS transistors formed on the second substrate to transfer the signal charges accumulated in the charge accumulation capacitor section, connection electrodes formed on the first substrate, and connection electrodes formed on the second substrate and electrically connected to the connection electrodes formed on the first substrate. | 2014-10-23 |
20140312393 | FIN-FET TRANSISTOR WITH PUNCHTHROUGH BARRIER AND LEAKAGE PROTECTION REGIONS - A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate and gate sidewall spacers on the fin defining preliminary source and drain regions of the fin on opposite sides of the dummy gate, removing the preliminary source and drain regions of the fin, implanting second conductivity type dopant atoms into exposed portions of the substrate and the punchthrough region, and forming source and drain regions having the second conductivity type on opposite sides of the dummy gate and the gate sidewall spacers. | 2014-10-23 |
20140312394 | Semiconductor Device Including a Material to Absorb Thermal Energy - A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules. | 2014-10-23 |
20140312395 | SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT - A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening. | 2014-10-23 |
20140312396 | SPLIT MULTI-GATE FIELD-EFFECT TRANSISTOR - A semiconductor device based on split multi-gate field-effect transistor radio frequency devices is provided. The semiconductor device includes a substrate and a gate structure above the substrate and orthogonal to a channel axis. The semiconductor device also includes a semiconductor fin structure above the substrate along the channel axis. The semiconductor also includes a gate oxide region beneath the gate structure and in contact with the gate structure and the semiconductor fin structure. The gate oxide region has a first region with a first thickness and a first length. The gate oxide region also has a second region with a second thickness and a second length. The first thickness is greater than the second thickness. The first region and the second region are formed side-by-side along the channel axis. | 2014-10-23 |
20140312397 | SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT - A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening. | 2014-10-23 |
20140312398 | RECESSING STI TO INCREASE FIN HEIGHT IN FIN-FIRST PROCESS - A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack. | 2014-10-23 |
20140312399 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength. This problem is solved by specifying the sizes of the asperities of both interfaces of the gate insulating film. | 2014-10-23 |
20140312400 | INTEGRATED NON-VOLATILE MEMORY ELEMENTS, DESIGN AND USE - Various embodiments describe an integrated non-volatile component. The component may include a surface contact with associated mating contact wherein a ferroelectric layer is used as a conductive channel having variable conductivity and the surface contact and/or the associated mating contact are/is embodied as a rectifying contact and, as a result of an applied voltage between the surface contact and the associated mating contact, a non-volatile space charge zone forms in the surface contact terminal region and/or mating contact terminal region in the ferroelectric layer. | 2014-10-23 |
20140312401 | MEMORY CELL HAVING A RECESSED GATE AND MANUFACTURING METHOD THEREOF - A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate. | 2014-10-23 |
20140312402 | SEMICONDUCTOR MEMORY DEVICE - In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring. | 2014-10-23 |
20140312403 | Memory Cell Floating Gate Replacement - A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type. | 2014-10-23 |
20140312404 | NON-VOLATILE MEMORY DEVICE INTEGRATED WITH CMOS SOI FET ON A SINGLE CHIP - A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region. | 2014-10-23 |
20140312405 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a multi-finger type control gate formed over a substrate, a multi-finger type floating gate formed over the substrate and disposed close to the control gate with gaps defined therebetween, and spacers formed on sidewalls of the control gate and the floating gate, and filling the gaps. | 2014-10-23 |
20140312406 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film ( | 2014-10-23 |
20140312407 | NONVOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF - A nonvolatile memory device comprises a substrate, a gate electrode, a single charge trapping sidewall and a source/drain region. The gate electrode is disposed on and electrically isolated from the substrate. The single charge trapping sidewall is disposed adjacent to a sidewall of the gate electrode and electrically isolated from the substrate and the gate electrode, so as to form a non-straight angle between the substrate and the single charge trapping sidewall. The source/drain region is disposed in the substrate and adjacent to the gate electrode. | 2014-10-23 |
20140312408 | CHARGE-TRAP NOR WITH SILICON-RICH NITRIDE AS A CHARGE TRAP LAYER - A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT-NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device. | 2014-10-23 |
20140312409 | SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY - A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process. | 2014-10-23 |
20140312410 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device having a plurality of unit cells, each of the plurality of unit cells includes a first transistor suitable for having a fixed threshold voltage, and a second transistor suitable for coupling to the first transistor in parallel and having a variable threshold voltage. | 2014-10-23 |
20140312411 | SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION METAL OXIDE SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally. | 2014-10-23 |
20140312412 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer. | 2014-10-23 |
20140312413 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer. | 2014-10-23 |
20140312414 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method of forming a manufacture includes forming a trench in a doped layer. The trench has an upper portion and a lower portion, and a width of the upper portion is greater than that of the lower portion. A first insulating layer is formed along sidewalls of the lower portion of the trench and a bottom surface of the trench. A gate dielectric layer is formed along sidewalls of the upper portion of the trench. A first conductive feature is formed along sidewalls of the gate dielectric layer. A second insulating layer covering the first conductive feature and the first insulating layer is formed, and a second conductive feature is formed along sidewalls of the second insulating layer and a bottom surface of the second insulating layer. | 2014-10-23 |
20140312415 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes: a semiconductor substrate including a first surface; a body region positioned in the semiconductor substrate and positioned to be in contact with the first surface; a gate insulating film positioned to be in contact with the body region on the first surface; a gate electrode positioned on the gate insulating film; a first insulator film covering at least a portion of a side surface of the gate electrode; a contact region positioned to be in contact with the first surface at a position different from that of the gate electrode, in a plan view relative to the first surface, in the body region; and a second insulator film including a material different from that of the first insulator film, positioned on the body region, the gate electrode, and the first insulator film, and including a contact hole on the contact region. | 2014-10-23 |
20140312416 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes, in a cell region thereof: a low resistance semiconductor layer; a drift layer; a base region; a high-concentration semiconductor region; and a gate electrode layer. The semiconductor device includes, in a peripheral region thereof: the low resistance semiconductor layer; the drift layer; which is formed over the low resistance semiconductor layer; a gate lead line; a gate finger; and a gate pad. The gate electrode layer and the gate lead line are electrically connected with each other by way of a resistor made of polysilicon containing an impurity, and an impurity concentration in polysilicon which forms the resistor is lower than an impurity concentration in polysilicon which forms the gate electrode layer. | 2014-10-23 |
20140312417 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench. The semiconductor device further includes a source region and a drain region, and a body region and a drift region disposed between the source region and the drain region. The semiconductor device additionally includes a gate electrode adjacent to at least a portion of the body region and a field plate adjacent to at least a portion of the drift region. A field dielectric layer is disposed between the drift region and the field plate. A top surface of the field dielectric layer is disposed at a greater height measured from a first main surface of the semiconductor substrate than a top surface of the lateral isolation layer. | 2014-10-23 |
20140312418 | SEMICONDUCTOR DEVICE - In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region. | 2014-10-23 |
20140312419 | FINFET DEVICES CONTAINING MERGED EPITAXIAL FIN-CONTAINING CONTACT REGIONS - A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers. | 2014-10-23 |
20140312420 | FINFET DEVICES CONTAINING MERGED EPITAXIAL FIN-CONTAINING CONTACT REGIONS - A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers. | 2014-10-23 |
20140312421 | Vapor-Trapping Growth of Single-Crystalline Graphene Flowers - A method for growing a graphene layer on a metal foil includes placing a vessel into a chemical vapor deposition chamber, the vessel having a metal foil positioned therein. The method includes evacuating the chemical vapor deposition chamber, introducing hydrogen gas into the chamber to achieve a first pressure less than atmospheric pressure, heating the atmosphere in the chamber to anneal the metal foil, introducing methane and hydrogen into the chamber to achieve a second pressure less than atmospheric pressure. | 2014-10-23 |
20140312422 | Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink-Harmonic Wrinkle Reduction - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 2014-10-23 |
20140312423 | SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS - A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. | 2014-10-23 |
20140312424 | METHOD OF PRODUCING A SILICON-ON-INSULATOR ARTICLE - A method of producing a silicon-on-insulator article, the method including: forming a first aluminium nitride layer thermally coupled to a first silicon substrate; forming a second aluminium nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminium nitride layers of the first and second substrates together so that the first and second aluminium nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminium nitride layers. | 2014-10-23 |
20140312425 | FINFET WITH CRYSTALLINE INSULATOR - FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region. | 2014-10-23 |
20140312426 | 6T SRAM ARCHITECTURE FOR GATE-ALL-AROUND NANOWIRE DEVICES - A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around (GAA) semiconductor nanowires. First, second, and third field effect transistors (FETs) are formed by the first plurality of semiconductor nanowires. The memory device also includes a second plurality of semiconductor nanowires tethered between landing pads and suspended over the substrate. A second gate electrode surrounds each of the second plurality of semiconductor nanowires, making them GAA semiconductor nanowires. Fourth, fifth, and sixth FETs are formed by the second plurality of semiconductor nanowires. The first gate electrode is aligned with and cross-coupled to a landing pad of the second plurality of semiconductor nanowires, and the second gate electrode is aligned with and cross-coupled to a landing pad of the first plurality of semiconductor nanowires. | 2014-10-23 |
20140312427 | Semiconductor Devices Having Fin Shaped Channels - Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin. The first field dielectric film includes a first part below a top surface of the first fin and a second part protruding from the first part and above a top surface of the first fin that makes contact with the first elevated source and/or drain. | 2014-10-23 |
20140312428 | EPITAXIAL REPLACEMENT OF A RAISED SOURCE/DRAIN - Disclosed is a semiconductor article which includes a semiconductor substrate; a plurality of gate structures having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to each of the gate structures, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. At least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET. | 2014-10-23 |
20140312429 | Power Semiconductor Device with Oscillation Prevention - There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000. | 2014-10-23 |
20140312430 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 2014-10-23 |
20140312431 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs. | 2014-10-23 |
20140312432 | SEMICONDUCTOR ARRANGEMENT WITH SUBSTRATE ISOLATION - One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance. | 2014-10-23 |
20140312433 | CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion. | 2014-10-23 |
20140312434 | FINFET DEVICE WITH A GRAPHENE GATE ELECTRODE AND METHODS OF FORMING SAME - One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode. | 2014-10-23 |
20140312435 | MEMS DEVICE WITH STRESS ISOLATION AND METHOD OF FABRICATION - A MEMS device ( | 2014-10-23 |
20140312436 | METHOD OF FABRICATING MEMS DEVICE HAVING RELEASE ETCH STOP LAYER - A method of fabricating a microelectromechanical (MEMS) device includes bonding a transducer wafer to a substrate wafer along a bond interface. An unpatterned transducer layer included within the transducer wafer is patterned. A release etch process is then performed during which a sacrificial layer is exposed to a selected release etchant to remove at a least a portion of the sacrificial layer through the openings in the patterned transducer layer. A release etch stop layer is formed between the sacrificial layer and the bond interface prior to exposing the sacrificial layer to the release etchant. The release etch stop layer prevents the ingress of the selected release etchant into the region of the MEMS device containing the bond interface during the release etch process. | 2014-10-23 |
20140312437 | ELECTRONIC DEVICE, INTEGRATED CIRCUIT, ELECTRONIC APPARATUS, AND MOVING OBJECT - An electronic device includes a vibrating element that detects a predetermined physical quantity, an integrated circuit that is electrically connected to the vibrating element, and a ceramic package. The ceramic package is provided with a first external terminal and a second external terminal to which a constant potential is supplied. The first external terminal is electrically connected to the second external terminal in a first mode, and is electrically connected to an internal node of the integrated circuit in a second mode. | 2014-10-23 |
20140312438 | PHYSICAL QUANTITY SENSOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - A physical quantity sensor includes a sensor element, an integrated circuit that is electrically connected to the sensor element, and a ceramic package (base body) on which the integrated circuit is mounted. A first conductor pattern (interconnection pattern) for electrical connection with the outside is provided on one surface of the ceramic package. A second conductor pattern is provided to be electrically connected to the interconnection pattern. The second conductor pattern includes an interconnection pattern that passes through the inside of the ceramic package, and a metallized region that is exposed on the other surface of the ceramic package. The interconnection pattern is longer than a distance between the one surface and the other surface of the ceramic package. | 2014-10-23 |
20140312439 | Microphone Module and Method of Manufacturing Thereof - A microphone module includes a package including a semiconductor chip and having a recess on an upper surface and a micro-electro-mechanical microphone being electrically connected to the package. Further, the micro-electro-mechanical microphone is arranged on the upper surface of the package. The recess forms an acoustic back volume of the micro-electro-mechanical microphone. | 2014-10-23 |
20140312440 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer. | 2014-10-23 |
20140312441 | NOVEL SPIN HALL EFFECT MAGNETIC-RAM - A spin Hall effect magnetoresistive memory comprises apparatus of a three terminal magnetoresistive memory cell having an MTJ stack, a functional magnetic layer having a magnetization anti-parallel or parallel coupled with a recording layer magnetization in the MTJ stack, and a SHE-metal base layer. The control circuitry coupled through the bit line and the two select transistors to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two bottom electrodes and to supply a bi-directional spin Hall effect recording current, and accordingly to directly switch the magnetization of the functional magnetic coupling layer and indirectly switching the magnetization of the recording layer through the coupling between the functional magnetic coupling layer and the recording layer. | 2014-10-23 |
20140312442 | RADIATION DETECTING ELEMENT AND RADIATION DETECTING DEVICE - There has been such a problem that radiation detecting elements using semiconductor elements have a low radiation detection efficiency, since the radiation detecting elements easily transmit radiation, even though the radiation detecting elements have merits, such as small dimensions and light weight. Disclosed are a radiation detecting element and a radiation detecting device, wherein a film formed of a metal, such as tungsten, is formed on the radiation incident surface of the radiation detecting element, and the incident energy of the radiation is attenuated. The efficiency of generating carriers by way of radiation incidence is improved by attenuating the incident energy, the thickness of the metal film is optimized, and the radiation detection efficiency is improved. | 2014-10-23 |
20140312443 | BUTT-COUPLED BURIED WAVEGUIDE PHOTODETECTOR - A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolates the first and second silicon-on-insulator region. Within the STI region, a germanium material is deposited adjacent an end facet of the semiconductor optical waveguide. The germanium material forms an active region that receives propagating optical signals from the end facet of the semiconductor optical waveguide. | 2014-10-23 |
20140312444 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD OF THE SAME, AND IMAGING APPARATUS - A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate. | 2014-10-23 |
20140312445 | LIGHT RECEIVING ELEMENT WITH OFFSET ABSORBING LAYER - A light receiving element includes a core configured to propagate a signal light, a first semiconductor layer having a first conductivity type, the first semiconductor layer being configured to receive the signal light from the core along a first direction in which the core extends, an absorbing layer configured to absorb the signal light received by the first semiconductor layer, and a second semiconductor layer having a second conductivity type opposite to the first conductivity type. | 2014-10-23 |