40th week of 2013 patent applcation highlights part 56 |
Patent application number | Title | Published |
20130260468 | METHODS FOR THE ANALYSIS OF LIQUID HALOSILANES - Methods for the direct analysis of liquid halosilanes. In particular, methods for using graphite furnace atomic absorption (GFAA) spectrometric analysis to evaluate the purity of liquid halosilanes by identifying and quantitatively measuring trace elements or impurities, such as, but not limited to metal species that may be present in liquid halosilanes. | 2013-10-03 |
20130260469 | DIFFERENTIAL ULTRASONIC WAVEGUIDE CURE MONITORING PROBE - The present invention is seen to provide a new methodology, testing system designs and concept to enable in situ real time monitoring of the cure process. Apparatus, system, and method for the non-destructive, in situ monitoring of the time dependent curing of advanced materials using one or more differential ultrasonic waveguide cure monitoring probes. A differential ultrasonic waveguide cure monitoring probe in direct contact with the material to be cured and providing in situ monitoring of the cure process to enable assessment of the degree of cure or cure level in a non-cure related signal variances (e.g., temperature) independent calibrated response manner. A differential ultrasonic waveguide cure monitoring probe including a transducer coupled to a waveguide and incorporating correction and calibration methodology to accurately and reproducibly monitor the cure process and enable assessment of cure level via ultrasonic reflection measurements. The amplitude of the corrected interface response signal reflected from the probe-resin interface indicating changes in the modulus of the material during the cure. | 2013-10-03 |
20130260470 | In-Situ Reagent For Detection Of Proteins - The present invention relates to a stable protein and/or amino acid detecting composition that can be used as a reagent for in situ detection, such as on surfaces. The invention also relates to a method for detecting protein and/or amino acid on surfaces using the composition and kits comprising the composition. | 2013-10-03 |
20130260471 | USE OF CYCLIC AZABORONATES AS SENSITIVE MATERIALS IN SENSORS FOR DETECTING THE PRESENCE OF PEROXIDES IN A GASEOUS ENVIRONMENT - The invention concerns the use of cyclic azaboronates as sensitive materials in sensors for the detection of the presence of peroxides, in particular hydrogen peroxide, in a gaseous environment. | 2013-10-03 |
20130260472 | APPARATUS AND METHOD FOR MOLECULAR SEPARATION, PURIFICATION, AND SENSING - Described are devices and methods for forming one or more nanomembranes including electroactive nanomembranes within a nanowell or nanotube, or combinations thereof, in a support material. Nanopores/nanochannels can be formed by the electroactive nanomembrane within corresponding nanowells. The electroactive nanomembrane is capable of controllably altering a dimension, a composition, and/or a variety of properties in response to electrical stimuli. Various embodiments also include devices/systems and methods for using the nanomembrane-containing devices for molecular separation, purification, sensing, etc. | 2013-10-03 |
20130260473 | IONISATION METHOD FOR A UNIVERSAL GAS ANALYZER - The invention provides a method and system for analyzing a gas for the presence of a reactant compound via reaction of primary ions of a specific type. A source gas is introduced to a reaction chamber and ionized in this chamber. The pressure in the reaction chamber is adjusted to avoid the formation of protonated species and other impurities. The primary ions generated in the reaction chamber are transferred to a drift tube. The gas to be analyzed is diluted with a carrier gas and the resulting mixture is introduced into the drift tube. The ionization energy of the carrier gas is equal to or higher than the ionization energy of the primary ions. The product ions resulting in the drift tube from a reaction of the primary ions with the reactant present in the gas to be analyzed are then detected, for example using a mass spectrometer. Preferably, an existing PTR-MS setup is used to perform the method of the present invention. | 2013-10-03 |
20130260474 | Microfluidic passive mixing chip - An improved device and method for passive mixing of fluids is described, and the use of the device in clinical diagnostic procedures. The mixer provides thorough mixing of a sample of blood or other fluid with an assay material, such as a diluent or a component of an assay system, in a closed system with a low and limited pressure drop. Sample size is small, typically 5 to 300 microliters. Mixing is accomplished by a combination of rotational vortex mixing due to a fluid stream coming tangent to a drain, and either or both of a second vortex mixer of opposite handedness, and a Dean mixer. Combinations of these techniques reliably provide complete mixing at low pressure drop. In a preferred usage, the microfluidic system can run a diluent continuously and inject samples at intervals, to facilitate automatic data processing of optical or other signatures of the well-mixed stream. | 2013-10-03 |
20130260475 | METHOD OF APPLYING A BIOLOGICAL SPECIMEN TO AN ANALYTIC PLATE - A method of applying a biological specimen to an analytic plate by using an applicator device to apply a coating to the analytic plate and adhering the biological sample to the plate. The coating is substantially transparent, translucent or invisible, and is substantially flush with the surface of the analytic plate. The coating is preferably comprised of a polysiloxane, siloxane, silicone, a silane, a silicon fluid, or a combination thereof and optionally an acid. | 2013-10-03 |
20130260476 | FECAL SAMPLING DEVICE AND METHOD - A collection device for use in connection with off-device testing of collected samples. The device includes a first panel having one or more apertures for receiving samples, a second panel opposite the first panel, and a removable tab having a first portion and a second portion. The first portion is aligned with at least one of apertures on the first panel and constructed such that depositing the sample through the at least one aperture causes the sample to be directly deposited on the first portion of the tab, and the second portion includes a sample-free grasping area accessible from an exterior of the device for removing the tab. A method of obtaining a sample is also disclosed. | 2013-10-03 |
20130260477 | BIOLOGICAL SAMPLE STORAGE DEVICE - Embodiments of the invention relate to methods of assembling an apparatus for holding biological samples. Conventionally, storage media are encased in a relatively thin flexible cardboard frame. Such constructions are vulnerable to damage from moisture and mechanical forces; these defects may subsequently cause problems for automated handling systems. In an embodiment, these defects are prevented by providing a pair of rigid frames, each frame comprising an aperture; placing a biological sample storage medium between the two frames so that the biological sample storage medium at least partly overlaps each of the apertures in the frames; and joining the two frames to fix the biological sample storage medium in place while allowing access to the biological sample storage medium via each of the apertures. Thus, in embodiments of the present invention, the frames can be rigid and waterproof, and provide a robust storage media for biological samples. At least one pre-defined area of weakness can be provided in the frames, to allow removal of a portion of the frames. | 2013-10-03 |
20130260478 | SYSTEM AND PROCESS FOR SELECTIVE DETECTION OF VAPOR-PHASE ANALYTES - A system and method are disclosed that provide selective detection of gas-phase target analytes at concentrations below 1 part-per-trillion including explosives, explosives compounds, and other threat agents involving chemical adduct ions between reactant ions and the target analytes for detection of the target analytes. | 2013-10-03 |
20130260479 | DEVICE AND METHOD FOR DETECTING EXISTENCE OF TARGET BIOMOLECULES IN A SPECIMEN - A detecting device is used for detecting existence of target biomolecules in a specimen with use of antibody complexes labeled with fluorescent molecules. The detecting device includes a capture member coated with capture antibodies for immobilizing the antibody complexes on the capture member when the target biomolecules exist in the specimen, a light emitting unit emitting a beam for exciting the fluorescence molecules to generate a fluorescence signal, and a signal processing unit for receiving the fluorescence signal and determining existence of the target biomolecules in the specimen based upon receipt of the fluorescence signal. | 2013-10-03 |
20130260480 | DIAGNOSTIC METHODS USING BNP - The present invent ion provides a new method and kit tor determining the overload or atrium or ventricle in a subject, comprising at least a step of measuring levels of proBNP-108 in a sample from the subject. The disclosed methods and kits are useful, for example, in the diagnosis, prevention and/or treatment of cardiac diseases, particularly heart failure, aortic stenosis, aortic regurgitation, mitral stenosis, mitral regurgitation, and atrial fibrillation. | 2013-10-03 |
20130260481 | ANALYSIS DEVICE AND ANALYSIS METHOD - To provide an analysis device capable of quantitatively measuring the concentration of a substance without diluting a sample containing the substance to be analyzed, detection portions ( | 2013-10-03 |
20130260482 | METHOD OF MANUFACTURING FERROELECTRIC THIN FILM - A method of manufacturing a ferroelectric thin film on a lower electrode by electrostatically spraying a ferroelectric thin film-forming electrostatic spray solution so as to coat the electrostatic spray solution on the lower electrode and form a coated film, drying, calcining, and then firing the coated film so as to crystallize the coated film. In this method, the electrostatic spray solution is a mixed solution in which a ferroelectric thin film-forming sol-gel solution and powder having the same composition as the solid content of the sol-gel solution and having a particle diameter that can be ejected from the spout are uniformly mixed, and, when the metallic compound-converted mass of a metallic compound dissolved in the sol-gel solution is represented by A and the mass of the powder is represented by B, a ratio of B with respect to (A+B) is in a range of 5% to 40%. | 2013-10-03 |
20130260483 | Integrated Circuits With Magnetic Core Inductors And Methods of Fabrications Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil. | 2013-10-03 |
20130260484 | OPTIMIZING LIGHT EXTRACTION EFFICIENCY FOR AN LED WAFER - The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters. | 2013-10-03 |
20130260485 | EDGE TRIGGERED CALIBRATION - Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system. | 2013-10-03 |
20130260486 | MOS Varactor Structure and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 2013-10-03 |
20130260487 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making light emitting diode, the method includes the following steps. First, a substrate having an epitaxial growth surface is provided. Second, a carbon nanotube layer is suspended above the epitaxial growth surface. Third, a first semiconductor layer, an active layer and a second semiconductor layer are grown on the epitaxial growth surface in that order, wherein the first semiconductor layer includes a buffer layer, an intrinsic semiconductor layer, and a doped semiconductor layer stacked in that order. Fourth, the doped semiconductor layer is exposed by removing the substrate, the buffer layer, and the intrinsic semiconductor layer. Fifth, a first electrode is prepared on the first semiconductor layer and a second electrode is prepared on the second semiconductor layer. | 2013-10-03 |
20130260488 | CHEMICAL VAPOR DEPOSITION APPARATUS AND METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICES USING SAME - Provided are a CVD apparatus and a method of manufacturing a light emitting device using the same. The CVD apparatus includes a chamber body including a susceptor having at least one pocket part having a wafer stably mounted therein; a chamber cover provided with the chamber body to open or close the chamber body and having a reaction space between the susceptor and the chamber cover; a reactive gas supplier supplying the reactive gas into the reaction space to allow the reactive gas to flow across a surface of the susceptor; and a non-reactive gas supplier supplying a non-reactive gas into the reaction space to allow the non-reactive gas to flow across a surface of the chamber cover between the susceptor and the chamber cover so as to prevent the reactive gas from contacting the surface of the chamber cover. | 2013-10-03 |
20130260489 | UNIFORM COATING METHOD FOR LIGHT EMITTING DIODE - A method of coating a light emitting diode (LED) is provided. The method includes preparing a substrate in which a plurality of LEDs are arranged, applying a curable liquid containing a fluorescent material to the substrate and the plurality of LEDs, and selectively applying energy to the substrate to which the curable liquid is applied, to thereby pattern the curable liquid, wherein the application of the energy includes applying the energy to both surfaces of the substrate. | 2013-10-03 |
20130260490 | Light Emitting Device Substrate with Inclined Sidewalls - A light emitting device having improved light extraction is provided. The light emitting device can be formed by epitaxially growing a light emitting structure on a surface of a substrate. The substrate can be scribed to form a set of angled side surfaces on the substrate. For each angled side surface in the set of angled side surfaces, a surface tangent vector to at least a portion of each angled side surface in the set of angled side surfaces forms an angle between approximately ten and approximately eighty degrees with a negative of a normal vector of the surface of the substrate. The substrate can be cleaned to clean debris from the angled side surfaces. | 2013-10-03 |
20130260491 | METHOD FOR MAKING LIGHT EMITTING DIODES - A method for making a LED comprises following steps. A substrate having a first surface and a second surface is provided. A patterned mask layer is applied on a first surface. A number of three-dimensional nano-structures are formed on the first surface and the patterned mask layer is removed. A first semiconductor layer, an active layer and a second semiconductor layer are formed on the second surface. A first electrode and a second electrode are formed to electrically connect with the first semiconductor layer and the second semiconductor pre-layer respectively. | 2013-10-03 |
20130260492 | METHOD FOR MAKING LIGHT EMITTING DIODES - A method for making a LED comprises following steps. A substrate having a surface is provided. A first semiconductor layer, an active layer and a second semiconductor pre-layer is formed on the surface of the substrate. A patterned mask layer is applied on a surface of the second semiconductor pre-layer. A number of three-dimensional nano-structures is formed on the second semiconductor pre-layer and the patterned mask layer is removed. The substrate is removed and a first electrode is formed on a surface of the first semiconductor layer away from the active layer. A second electrode is formed to electrically connect with the second semiconductor pre-layer. | 2013-10-03 |
20130260493 | METHODS FOR MAKING LIGHT EMITTING DIODES AND OPTICAL ELEMENTS - A method for making a LED comprises following steps. A substrate having a surface is provided. A first semiconductor layer, an active layer and a second semiconductor pre-layer is formed on the surface of the substrate. A first electrode and a second electrode are formed to electrically connect with the first semiconductor layer and the second semiconductor pre-layer respectively. A patterned mask layer is applied on a surface of the second semiconductor pre-layer. A number of three-dimensional nano-structures are formed on the second semiconductor pre-layer and the patterned mask layer is removed. A method for making an optical element is also provided. | 2013-10-03 |
20130260494 | METHOD FOR FABRICATING LIGHT EMITTING DIODE (LED) DICE WITH WAVELENGTH CONVERSION LAYERS - A method for fabricating light emitting diode (LED) dice includes the steps of mixing wavelength conversion particles in a base material to a first weight percentage, mixing reflective particles in the base material to a second weight percentage, curing the base material to form a wavelength conversion layer having a selected thickness, and attaching the wavelength conversion layer to a die. | 2013-10-03 |
20130260495 | LIGHT EMITTING DEVICES AND METHODS OF MANUFACTURING THE SAME - Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned dispersion Bragg reflection (DBR) layer on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR layer and regions between patterns of the DBR layer. | 2013-10-03 |
20130260496 | TFT-LCD ARRAY SUBSTRATE MANUFACTURING METHOD - A method of manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate including a gate line and a data line that define a pixel region, wherein the pixel region is provided with a thin film transistor, a pixel electrode formed on the array substrate, and a storage electrode of transparent structure that overlaps with the pixel electrode and, together with the pixel electrode, constitutes a storage capacitor. | 2013-10-03 |
20130260497 | METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL - A method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes, forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate, first heat treating the substrate comprising the oxide semiconductor layer, forming a source electrode and a drain electrode on the oxide semiconductor layer, the source and drain electrodes facing each other, and forming a passivation layer on the source electrode and the drain electrode. The first heat treating is performed at more than 1 atmosphere and at most 50 or less atmospheres. | 2013-10-03 |
20130260498 | THIN FILM TRANSISTOR HAVING SEMICONDUCTOR WITH DIFFERENT CRYSTALLINITIES AND MANUFACTURING METHOD THEREOF - A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity. | 2013-10-03 |
20130260499 | VAPOR DEPOSITION APPARATUS, VAPOR DEPOSITION METHOD, AND METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - A vapor deposition device ( | 2013-10-03 |
20130260500 | Method For Manufacturing A Light Emitting Diode - This invention is about a method to be used in the fabrication of an electroluminescent diode and a diode fabricated with this method. The temperatures needed for the crystalline LEDs produced presently under specified temperatures in a furnace, will be provided within the semiconductor by the Joule effect. As an alternative to the commercial LEDs, whose costs are suitable only when they are produced in the order of centimeters, our process renders the fabrication of LEDs over very large surfaces of the order of meters, with the temperature raised by applying electric current without any requirements of high temperature furnace treatments. The effects of the chemical processes experienced during the Joule heating are permanent and the diode is able to luminesce. | 2013-10-03 |
20130260501 | VAPOR DEPOSITION DEVICE, VAPOR DEPOSITION METHOD, AND METHOD OF MANUFACTURING ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - A vapor deposition device ( | 2013-10-03 |
20130260502 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making a light emitting diode includes the following steps. A substrate having a first epitaxial growth surface is provided. A carbon nanotube layer is placed on the first epitaxial growth surface of the substrate. A surface of the first semiconductor layer is exposed by removing the substrate and the carbon nanotube layer. The surface of the first semiconductor layer is defined as a second epitaxial growth surface. An active layer and a second semiconductor layer are grown on the second epitaxial growth surface in that order. A surface of the active layer contacted the first semiconductor layer engages with the second epitaxial growth surface. A part of the first semiconductor layer is exposed by etching a part of the active layer and the second semiconductor layer. A first electrode is applied on the first semiconductor layer and a second electrode is applied on the second semiconductor layer. | 2013-10-03 |
20130260503 | Methods and Apparatuses for Integrated Packaging of Microelectromechanical Devices - Microelectromechanical systems (MEMS) packages, packaged MEMS devices, and methods for making the same are disclosed. The method may include forming a chamber sacrificial layer above an insulating layer that is coupled to a wafer. The method further may include forming a packaging layer above the chamber sacrificial layer. The method additionally may include forming one or more openings through the packaging layer. The method also may include removing the chamber sacrificial layer through the one or more openings. The method may include forming a sealing layer above the packaging layer such that the sealing layer substantially seals the one or more openings to form a hermetic cavity. | 2013-10-03 |
20130260504 | METHOD FOR FABRICATING MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) DEVICE - Method is to fabricate a MEMS device with a substrate. The substrate has through holes in the substrate within a diaphragm region and optionally an indent space from the second surface at the diaphragm region. A first dielectric structural layer is then disposed over the substrate from the first surface, wherein the first dielectric structural layer has a plurality of openings corresponding to the through holes, wherein each of the through holes remains exposed by the first dielectric structural layer. A second dielectric structural layer with a chamber is disposed over the first dielectric structural layer, wherein the chamber exposes the openings of the first dielectric structural layer and the through holes of the substrate to connect to the indent space. A MEMS diaphragm is embedded in the second dielectric structural layer above the chamber, wherein an air gap is formed between the substrate and the MEMS diaphragm. | 2013-10-03 |
20130260505 | SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE - A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. | 2013-10-03 |
20130260506 | METHOD FOR MAKING SOLAR CELLS - A method for making a solar cell includes the following steps. A silicon plate having a first surface and a second surface is provided. A patterned mask layer is formed on the second surface to expose a portion of the second surface. A number of three-dimensional nano-structures are formed by etching the exposed portion of the second surface and the mask layer is removed. A doped silicon layer is formed on surfaces of the three-dimensional nano-structures. An upper electrode is applied to contact with the doped silicon layer. A back electrode is placed on the first surface. | 2013-10-03 |
20130260507 | Method for Forming a Fibrous Layer - The present invention relates to a method for forming, on the surface of one of the sides of a silicon substrate, a fibrous layer having a mean lattice pitch of no more than 2 μm, without requiring soaking. | 2013-10-03 |
20130260508 | Methods for forming resistive switching memory elements - Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication. | 2013-10-03 |
20130260509 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode. | 2013-10-03 |
20130260510 | 3-D Integrated Circuits and Methods of Forming Thereof - In one embodiment, a method of forming a semiconductor device includes stacking a second wafer with a first wafer and forming a through via extending through the second wafer while the second wafer is stacked with the first wafer. In another embodiment, a method of forming a semiconductor device includes singulating a first wafer into a first plurality of dies and attaching the first plurality of dies over a second wafer having a second plurality of dies. The method further includes forming a through via extending through a die of the first plurality of dies after attaching the first plurality of dies over the second wafer. | 2013-10-03 |
20130260511 | LID ATTACH PROCESS AND APPARATUS FOR FABRICATION OF SEMICONDUCTOR PACKAGES - A semiconductor package assembly process that includes attaching one or more dies to a substrate; applying an adhesive material on a periphery of the substrate by an adhesive dispenser having a stamp-type dispensing head; applying a thermal interface material (TIM) on a top surface of the die by a TIM dispenser having a stamp-type dispensing head; and positioning a lid over the one or more dies and placing the lid on top of the adhesive material and the TIM by a lid carrier to encapsulate the one or more dies. | 2013-10-03 |
20130260512 | METHOD OF MANUFACTURING PACKAGE STRUCTURE - A manufacturing method of a package structure is provided. A seed layer is formed on a upper surface of a metal substrate. A patterned dry film layer is formed on a lower surface of the metal substrate and the seed layer. A portion of the seed layer is exposed by the patterned dry film layer. The patterned dry film layer is used as an electroplating mask to electroplate a circuit layer on the portion of the seed layer exposed by the patterned dry film layer. A chip is bonded to and electrically connected to the circuit layer. A molding compound is formed on the metal substrate. The molding compound encapsulates the chip, the circuit layer and the portion of the seed layer. A portion of the metal substrate and a portion of the seed layer are removed so as to expose a portion of the molding compound. | 2013-10-03 |
20130260513 | MICROELECTRONIC PACKAGE WITH TERMINALS ON DIELECTRIC MASS - A package for a microelectronic element | 2013-10-03 |
20130260514 | System of Dynamic and End-User Configurable Electrical Interconnects - A dynamic and end-user configurable controlled impedance interconnect line includes a plurality of conductive pixels, a plurality of thin-film transition material interconnects to electrically connect adjacent conductive pixels in the plurality of conductive pixels, and a plurality of addressable pixel interconnect actuators to selectively heat a respective plurality of the thin-film transition material interconnects. The plurality of addressable pixel interconnect actuators is operable to selectively heat a respective plurality of the thin-film transition material interconnects to form an interconnect line. | 2013-10-03 |
20130260515 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing an RC-IGBT provided with an IGBT and an FWD on the same substrate is provided. First, top surface device structures of an IGBT and an FWD are formed on the top surface of a semiconductor substrate. Then, with the side of an IGBT region on the top surface of the semiconductor substrate shielded by a first shielding mask, only an FWD region is irradiated with light ions. Next, with the side of the FWD region on the bottom surface of the semiconductor substrate shielded by a second shielding mask, only the IGBT region is irradiated with light ions. With this, a first lifetime control region | 2013-10-03 |
20130260516 | Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure - Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided. | 2013-10-03 |
20130260517 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a first film on a nitride semiconductor layer so as to contact the nitride semiconductor layer and have a thickness equal to or larger than 1 nm and equal to or smaller than 5 nm, the first film being made of silicon nitride having a composition ratio of silicon to nitrogen larger than 0.75, silicon oxide having a composition ratio of silicon to oxygen larger than 0.5, or aluminum; and forming a source electrode, a gate electrode and a drain electrode on the nitride semiconductor layer. | 2013-10-03 |
20130260518 | PROCESS TO IMPROVE TRANSISTOR DRIVE CURRENT THROUGH THE USE OF STRAIN - The present invention provides, in one embodiment, a P-type Metal Oxide Semiconductor (PMOS) device ( | 2013-10-03 |
20130260519 | STRAINED STRUCTURE OF SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate. | 2013-10-03 |
20130260520 | LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR - A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode. | 2013-10-03 |
20130260521 | MEMORY ARRAY WITH AN AIR GAP BETWEEN MEMORY CELLS AND THE FORMATION THEREOF - A method of forming a memory array includes forming a dielectric over a semiconductor, forming a charge-storage structure over the dielectric, forming an isolation region through the dielectric and the charge-storage structure and extending into the semiconductor, recessing the isolation region to a level below a level of an upper surface of the dielectric and at or above a level of an upper surface of the semiconductor, forming an access line over the charge-storage structure and the recessed isolation region, and forming an air gap over the recessed isolation region so that the air gap passes through the charge-storage structure, so that the air gap extends to and terminates at a bottom surface of the access line, and so that the entire air gap is between the bottom surface of the access line and the upper surface of the semiconductor. | 2013-10-03 |
20130260522 | STAGGERED COLUMN SUPERJUNCTION - A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer. | 2013-10-03 |
20130260523 | METHOD FOR FABRICATING SUPER-JUNCTION POWER DEVICE WITH REDUCED MILLER CAPACITANCE - A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer. | 2013-10-03 |
20130260524 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY - A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening. | 2013-10-03 |
20130260525 | LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION - A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length. | 2013-10-03 |
20130260526 | SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT - A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively. | 2013-10-03 |
20130260527 | METHOD OF FORMING A METAL CHALCOGENIDE MATERIAL AND METHODS OF FORMING MEMORY CELLS INCLUDING SAME - A method of forming a metal chalcogenide material. The method comprises exposing a metal to a solution comprising a chalcogenide element source compound and an acid. Methods of forming memory cells including the metal chalcogenide material are also disclosed. | 2013-10-03 |
20130260528 | MEMORY DEVICE MANUFACTURING METHOD WITH MEMORY ELEMENT HAVING A METAL-OXYGEN COMPOUND - Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element. | 2013-10-03 |
20130260529 | METHODS OF FORMING CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING A RUTILE TITANIUM DIOXIDE MATERIAL - Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. | 2013-10-03 |
20130260530 | MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY - A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage. | 2013-10-03 |
20130260531 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring. | 2013-10-03 |
20130260532 | Method for Manufacturing Semiconductor Device - The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a shallow trench in a substrate; forming a shallow trench filling layer in the shallow trench; forming a cap layer on the shallow trench filling layer; and implanting ions into the shallow trench filling layer and performing an annealing to form a shallow trench isolation. In the method for manufacturing the semiconductor device according to the present invention, an insulating material is formed by implanting ions into the filling material in the shallow trench, and a compressive stress is applied to the active region of the substrate due to the volume expansion of the filling material, so that the carrier mobility in the channel regions to be formed later can be increased and the device performance can be improved. | 2013-10-03 |
20130260533 | INTRENCH PROFILE - A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. | 2013-10-03 |
20130260534 | STRESS REDUCTION MEANS FOR WARP CONTROL OF SUBSTRATES THROUGH CLAMPING - A method is provided for bonding a semiconductor chip to a packaging substrate while minimizing the variation in the solder ball heights and controlling the stress in the solder balls and the stress in the packaging substrate. During the solder reflow, the warp of the packaging substrate, including the absolute warp, thermal warp, and substrate to substrate variations of the warp, is constrained at a minimal level by providing a clamping constraint to the packaging substrate. During cool down of the solder balls, the stresses and strains of the solder joints are maintained at levels that do not cause tear of the solder joints or breakage of the packaging substrate by removing the clamping constraint. Thus, the bonding process provides both uniform solder height with minimized solder non-wets and stress minimization of the solder balls and the packaging substrate. | 2013-10-03 |
20130260535 | METHOD AND APPARATUS FOR REDUCING PACKAGE WARPAGE - Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time. | 2013-10-03 |
20130260536 | Controlling Printed Ink Line Widths using Fluoropolymer Templates - A method is provided for controlling printed ink horizontal cross-sectional areas using fluoropolymer templates. The method initially forms a fluoropolymer template overlying a substrate. The fluoropolymer template has a horizontal first cross-sectional dimension. Then, a primary ink is printed overlying the fluoropolymer template having a horizontal second cross-sectional dimension less than the first cross-sectional dimension. In the case of a fluoropolymer line having a template length greater than a template width, where the template width is the first cross-sectional dimension, printing the primary ink entails printing a primary ink line having an ink length greater than an ink width, where the ink width is the second cross-sectional dimension. In one aspect, the method prints a plurality of primary ink layers, each primary ink layer having an ink width less than the template width. Each overlying primary ink layer can be printed prior to solvents in underlying primary ink layers evaporating. | 2013-10-03 |
20130260537 | SYSTEM AND PROCESS FOR HIGH-DENSITY, LOW-ENERGY PLASMA ENHANCED VAPOR PHASE EPITAXY - A process for epitaxial deposition of compound semiconductor layers includes several steps. In a first step, a substrate is removably attached to a substrate holder that may be heated. In a second step, the substrate is heated to a temperature suitable for epitaxial deposition. In a third step, substances are vaporized into vapor particles, such substances including at least one of a list of substances, comprising elemental metals, metal alloys and dopants. In a fourth step, the vapor particles are discharged to the deposition chamber. In a fifth step, a pressure is maintained in the range of 10̂-3 to 1 mbar in the deposition chamber by supplying a mixture of gases comprising at least one gas, wherein vapor particles and gas particles propagate diffusively. In a sixth optional step, a magnetic field may be applied to the deposition chamber. In a seventh step, the vapor particles and gas particles are activated by a plasma in direct contact with the sample holder. In an eighth step, vapor particles and gas particles are allowed to react, so as to form a uniform epitaxial layer on the heated substrate by low-energy plasma-enhanced vapor phase epitaxy. | 2013-10-03 |
20130260538 | METHOD OF MANUFACTURING GALLIUM NITRIDE SUBSTRATE - A method of manufacturing a gallium nitride substrate includes machining a gallium nitride crystal, and wet-etching the gallium nitride crystal prior to the machining. | 2013-10-03 |
20130260539 | VAPOR DEPOSITION REACTOR FOR FORMING THIN FILM - A vapor deposition reactor includes a chamber filled with a first material, and at least one reaction module in the chamber. The reaction module may be configured to make a substrate pass the reaction module through a relative motion between the substrate and the reaction module. The reaction module may include an injection unit for injecting a second material to the substrate. A method for forming thin film includes positioning a substrate in a chamber, filling a first material in the chamber, moving the substrate relative to a reaction module in the chamber, and injecting a second material to the substrate while the substrate passes the reaction module. | 2013-10-03 |
20130260540 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element. | 2013-10-03 |
20130260541 | METHOD FOR PRODUCING Ga-CONTAINING GROUP III NITRIDE SEMICONDUCTOR - A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer. | 2013-10-03 |
20130260542 | METHOD FOR IMPROVING WRITE MARGINS OF SRAM CELLS - The present invention provides a method for improving the write margins of the SRAM cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a pre-implantation process to the polysilicon layer; wherein the polysilicon layer defines SRAM NMOSFETs regions and SRAM PMOSFETs regions; wherein the pre-implantation process comprises pre-implanting the fifth-group elements to the SRAM NMOSFETs regions and the NMOSFETs regions except to the SRAM NMOSFETs regions in the polysilicon layer, and pre-implanting the third-group elements to the PMOSFETs regions excluding the SRAM PMOSFETs regions in the polysilicon layer; wherein the process of pre-implanting the third-group elements comprises forming a pre-implantation photo mask capable of covering the SRAM PMOSFETs regions and using the pre-implantation photo mask to pre-implanting the third-group elements. | 2013-10-03 |
20130260543 | TECHNIQUE FOR PROCESSING A SUBSTRATE - Techniques for processing a substrate are disclosed. In one exemplary embodiment, the technique may be realized with an ion implantation system for processing a substrate. The ion implantation system may comprise: an ion source comprising an ion source chamber, the ion source chamber including an ion source chamber wall that define an ion generation region and an extraction aperture, through which ions generated in the ion generation region are extracted; an extraction system positioned downstream of the ion source near the extraction aperture; a material source comprising a fist source containing first material, a second source containing the second material, and a first and second conduits, where the first conduit may be in communication with the first source and the ion source chamber to provide the first material from the first source to the ion source chamber, and where the second conduit may be in communication with the second source and a first region outside of the ion source chamber to provide the second material from the second source to the first region. | 2013-10-03 |
20130260544 | TECHNIQUE FOR PROCESSING A SUBSTRATE - Techniques for processing a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method for processing a substrate, the method comprising: ionizing first material and second material in an ion source chamber of an ion source, the first material being boron (B) containing material, the second material being one of phosphorous (P) containing material and arsenic (As) containing material; generating first ions containing B and second ions containing one of P and As; and extracting the first and second ions from the ion source chamber and directing the first and second ions toward the substrate. | 2013-10-03 |
20130260545 | METHODS AND COMPOSITIONS FOR DOPING SILICON SUBSTRATES WITH MOLECULAR MONOLAYERS - Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred. | 2013-10-03 |
20130260546 | HEAT TREATMENT APPARATUS AND HEAT TREATMENT METHOD FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH FLASH OF LIGHT - After the completion of the transport of a semiconductor wafer into a chamber, the flow rate of nitrogen gas supplied into the chamber is decreased. In this state, a preheating treatment and flash irradiation are performed. The flow rate of nitrogen gas supplied into the chamber is increased when the temperature of the front surface of the semiconductor wafer is decreased to become equal to the temperature of the back surface thereof after reaching its maximum temperature by the irradiation of the substrate with a flash of light. Thereafter, the supply flow rate of nitrogen gas is maintained at a constant value until the semiconductor wafer is transported out of the chamber. This achieves the reduction in particles deposited on the semiconductor wafer while suppressing adverse effects resulting from the nonuniform in-plane temperature distribution of the semiconductor wafer. | 2013-10-03 |
20130260547 | METHOD OF FABRICATING A METAL GATE SEMICONDUCTOR DEVICE - A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer. | 2013-10-03 |
20130260548 | TECHNIQUES FOR USING MATERIAL SUBSTITUTION PROCESSES TO FORM REPLACEMENT METAL GATE ELECTRODES OF SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS - Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material. | 2013-10-03 |
20130260549 | REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. | 2013-10-03 |
20130260550 | LARGE-AREA TRANSPARENT CONDUCTIVE COATINGS INCLUDING ALLOYED CARBON NANOTUBES AND NANOWIRE COMPOSITES, AND METHODS OF MAKING THE SAME - Certain example embodiments of this invention relate to large-area transparent conductive coatings (TCCs) including carbon nanotubes (CNTs) and nanowire composites, and methods of making the same. The σ | 2013-10-03 |
20130260551 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented. | 2013-10-03 |
20130260552 | Reverse Damascene Process - The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. | 2013-10-03 |
20130260553 | SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS OF MAKING SAME - Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process. | 2013-10-03 |
20130260554 | Semiconductor Devices and Methods of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration. | 2013-10-03 |
20130260555 | METHOD OF ENABLING SEAMLESS COBALT GAP-FILL - Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved. | 2013-10-03 |
20130260556 | BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS - According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad. | 2013-10-03 |
20130260557 | PROCESS FOR SEMICONDUCTOR CIRCUIT - A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer. | 2013-10-03 |
20130260558 | POLISHING LIQUID AND METHOD FOR POLISHING SUBSTRATE USING THE POLISHING LIQUID - Provided is a polishing liquid including cerium oxide particles, an organic acid A, a polymer compound B having a carboxyl acid group or a carboxylate group, and water, wherein the organic acid A has at least one group selected from the group consisting of —COOM group, -Ph-OM group, —SO | 2013-10-03 |
20130260559 | METHODS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction. | 2013-10-03 |
20130260560 | Patterning Processes Comprising Amplified Patterns - The present invention is directed to substrates comprising amplified patterns, methods for making the amplified patterns, and methods of using the amplified patterns to form surface features on the substrates. | 2013-10-03 |
20130260561 | Aspect Ratio Dependent Deposition to Improve Gate Spacer Profile, Fin-Loss and Hardmask-Loss for FinFET Scheme - Techniques disclosed herein include systems and methods for an aspect ratio dependent deposition process that improves gate spacer profile, reduces fin loss, and also reduces hardmask loss in a FinFET or other transistor scheme. Techniques include depositing an aspect ratio dependent protective layer to help tune profile of a structure during fabrication. Plasma and process gas parameters are tuned such that more polymer can collect on surfaces of a structure that are visible to the plasma. For example, upper portions of structures can collect more polymer as compared to lower portions of structures. The variable thickness of the protection layer enables selective portions of spacer material to be removed while other portions are protected. | 2013-10-03 |
20130260562 | METHODS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings. | 2013-10-03 |
20130260563 | Mask Treatment for Double Patterning Design - A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask. | 2013-10-03 |
20130260564 | INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION - Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF. | 2013-10-03 |
20130260565 | METHOD TO FORM CONVEX STRUCTURE ON SURFACE OF SEMICONDUCTOR MATERIAL - A process to form a lens on a semiconductor material is disclosed. The process includes steps of: forming double layers of an intermediate layer on the semiconductor material and a mask layer made of hard-baked photoresist on the semiconductor substrate; the first transcribing the convex shape of the mask layer on the intermediate layer; and the second scribing the convex shape of the intermediate layer on the semiconductor material. | 2013-10-03 |
20130260566 | Method of Manufacturing Semiconductor Device, Cleaning Method, Substrate Processing Apparatus and Non-Transitory Computer Readable Recording Medium - Provided is a method of manufacturing a semiconductor device, which efficiently removes a high permittivity film (high-k film). The method of manufacturing a semiconductor device includes: (a) supplying a processing gas containing an organic compound into a process chamber to form a predetermined film on a substrate; (b) supplying a first cleaning gas into the process chamber with the substrate being unloaded from the process chamber to remove films adhered to an inner wall of a reaction tube defining the process chamber and members disposed in the process chamber; (c) supplying a modifying gas into the process chamber after performing (b) to modify a carbon-containing film remaining in a nozzle of the members configured to supply the processing gas; and (d) supplying a second cleaning gas into the process chamber to remove a film obtained by modifying the carbon-containing film in (c). | 2013-10-03 |
20130260567 | MULTI-RADIOFREQUENCY IMPEDANCE CONTROL FOR PLASMA UNIFORMITY TUNING - Circuits, methods, chambers, systems, and computer programs are presented for processing wafers. A wafer processing apparatus includes top and bottom electrodes inside a processing chamber; a first, second, third, and fourth radio frequency (RF) power sources; and one or more resonant circuits. The first, second, and third RF power sources are coupled to the bottom electrode. The top electrode may be coupled to the fourth RF power source, to electrical ground, or to the one or more resonant circuits. Each of the one or more resonant circuits, which are coupled between the top electrode and electrical ground, include a tune-in element operable to vary a frequency-dependent impedance presented by the resonant circuit. The wafer processing apparatus is configurable to select the RF power sources for wafer processing operations, as well as the connections to the top electrode in order to provide plasma and etching uniformity for the wafer. | 2013-10-03 |