40th week of 2008 patent applcation highlights part 27 |
Patent application number | Title | Published |
20080238447 | ISOLATED CAPACITIVE SIGNATURE DETECTION FOR POWERED DEVICES - In one embodiment, a method for determining capacitive signature validity of a powered device (PD) attached to power sourcing equipment (PSE) having (i) an isolated side with a primary coil and (ii) a line side with a secondary coil connected to the PD. The method includes determining, on the isolated side, a first time T | 2008-10-02 |
20080238448 | Capacitance sensing for percussion instruments and methods therefor - A percussion instrument data generating system can include a plurality of capacitance sensors coupled to the at least a first surface. A controller section can includes a plurality of switches for selectively connecting each capacitance sensor to a sense node. A capacitance sense circuit can be coupled to the common sense node and can measures a capacitance presented at the common sense node. An encoder section that generates a position value for a sensed input event based that varies according to which capacitance sensor detects the input event. | 2008-10-02 |
20080238449 | Fluid sensor and impedance sensor - A fluid sensor detects property of fluid by dipping the sensor in the fluid. The sensor includes: a semiconductor substrate; and a comb-teeth electrode made of a first diffusion layer and disposed on a first surface of the substrate. Although the comb-teeth electrode is capable of directly contacting the fluid without a protection film, corrosion resistance of the sensor against the fluid is improved. Further, since the sensor has no protection film, the sensor can detect the property accurately. | 2008-10-02 |
20080238450 | METHOD FOR INSPECTING QUALITY OF CORE MATERIAL FOR ELECTROPHOTOGRAPHIC FERRITE CARRIER - An object of the present invention is to provide a quality inspection method for obtaining a specifying factor which can more reliably indicate powder characteristics of a core material for an electrophotographic ferrite carrier. To achieve the object, a method for inspecting the quality of a core material for an electrophotographic ferrite carrier adopts a method characterized in that the impedance of the core material for the electrophotographic ferrite carrier is measured by using an AC-resistance measurement method to obtain a Nyquist diagram (Cole-Cole plot) in which a real number impedance (Z′) is arranged in an X-axis and an imaginary number impedance (Z″) is arranged in a Y-axis and then the characteristics of the particles of the core material for the electrophotographic ferrite carrier is evaluated by using the Nyquist diagram (Cole-Cole plot). Here, the quality of a core material for the electrophotographic ferrite carrier is judged according to a predetermined equivalent circuit by using the value of the parameters one or two or more in combination selected from |Rs|, Rp | 2008-10-02 |
20080238451 | AUTOMATIC MULTIPLEXING SYSTEM FOR AUTOMATED WAFER TESTING - A parametric test system is for testing devices in dice in a semiconductor wafer, each die having a plurality of pads for electrically connecting to the device in the die. A tester of the system has a plurality of input/output lines for providing and receiving electrical signals during a device test. Multiplexer circuitry of the test system includes a plurality of networks of automated switches. The multiplexer circuitry is configured to receive electrical signals on the input lines from the tester and to provide the electrical signals to a wafer prober, wherein the multiplexer circuitry is configured to restrict how the electrical signals can be provided to the networks of automated switches. As a result of the multiplexer being configured to restrict how the electrical signals can be provided to the networks of automated switches, the configuration of the networks of automated switches can be simplified. | 2008-10-02 |
20080238452 | Vertical micro probes - Embodiments of the present invention improve probes and probe assemblies. In one embodiment the present invention includes a micro probe comprising a lower contact end including a lower tip, an upper contact end, and a curved intermediate region between the upper contact end and lower contact end. An angle stop is included between the lower contact end and the curved intermediate region, and the lower contact end, upper contact end, and curved intermediate region have a uniform thickness | 2008-10-02 |
20080238453 | High accuracy and universal on-chip switch matrix testline - A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented. | 2008-10-02 |
20080238454 | TESTER AND STRUCTURE OF PROBE THEREOF - A split-type probe is used to contact with an object under test to detect an electrical characteristic thereof. The probe provided by the present invention has a contact head used to contact with the object under test, and a first needle body and a second needle body. The first needle body is connected to the contact head to transmit a testing signal to the object under test for performing detection. In addition, the second needle body is also connected to the contact head to transmit a response signal generated by the object under test due to the testing signal to obtain the electrical characteristic of the object under test. | 2008-10-02 |
20080238455 | PROBING METHOD, PROBE APPARATUS AND STORAGE MEDIUM - A probing method measures electrical characteristics of an object to be inspected by bringing a probe needle to make a contact with an electrode pad of the object, the probe needle formed to be vertically pointing the object. The method includes the steps of: mounting the object on a mounting table; aligning the object and the probe needle; thereafter, contacting the probe needle with the electrode pad by moving the mounting table upwards, and then moving the mounting table vertically upwards while moving same horizontally to rend an oxide film formed on a surface of the electrode pad, so that a tip of the probe needle is stuck into the electrode pad and the probe needle and the electrode pad to conduct with each other. | 2008-10-02 |
20080238456 | SEMICONDUCTOR INSPECTION APPARATUS - A semiconductor inspection apparatus includes a force probe applying voltage to a semiconductor device, and a sense probe detecting voltage of the semiconductor device, in which the force probe is contacted with an electrode pad of the semiconductor device and the force probe and the sense probe are contacted with each other to measure electric characteristics of the semiconductor device, and the force probe and the sense probe are arranged substantially on the same line when seen from a vertical direction with respect to an electrode surface (principal surface) of the semiconductor device. | 2008-10-02 |
20080238457 | NANOSCALE FAULT ISOLATION AND MEASUREMENT SYSTEM - Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material. | 2008-10-02 |
20080238458 | METHOD OF DESIGNING A PROBE CARD APPARATUS WITH DESIRED COMPLIANCE CHARACTERISTICS - A probe card apparatus is configured to have a desired overall amount of compliance. The compliance of the probes of the probe card apparatus is determined, and an additional, predetermined amount of compliance is designed into the probe card apparatus so that the sum of the additional compliance and the compliance of the probes total the overall desired compliance of the probe card apparatus. | 2008-10-02 |
20080238459 | Testing apparatus and method - A testing apparatus includes a circuit board and a first probe. The circuit board has a first testing point and a second testing point. The first testing point is electrically connected to an integrated circuit, and the second testing point is electrically connected to the first testing point. The first probe is used for electrically contacting with the first testing point and transmitting a signal to the integrated circuit through the first testing point. The second testing point is used for detecting if the first probe electrically contacts with the first measuring point. A testing method is also disclosed herein. | 2008-10-02 |
20080238460 | Accurate alignment of semiconductor devices and sockets - Methods and apparatus to provide accurate alignment for semiconductor sockets are described. In one embodiment, a carrier is utilized to align a device under test with a test socket. In some embodiments, alignment features on a carrier, a device under test, and/or a test socket are used to align the devices relative to each other. | 2008-10-02 |
20080238461 | Multi-type test interface system and method - Efficient automated testing systems and methods are presented. In one embodiment, an automated testing system includes a plurality of bucket modules, and a device under test transition interface. The plurality of bucket modules have similar external connection form factors for a variety of instruments. The interface is for transitioning connections from the plurality of bucket modules to a device under test. | 2008-10-02 |
20080238462 | TEST DEVICE FOR SEMICONDUCTOR DEVICES - A test device for semiconductor devices is disclosed. One embodiment provides a probe card, having at least one contact test body for contacting a semiconductor device. The probe card includes self-alignment devices and/or a penetration restriction device, or parts thereof. A semiconductor device is provided having at least one contact field adapted to be contacted by contact test bodies of a test device. The semiconductor device includes self-alignment devices and/or a penetration restriction device, or parts thereof, for the contact test body in the region of the contact field. | 2008-10-02 |
20080238463 | PROBE APPARATUS, PROBING METHOD AND STORAGE MEDIUM - A probe apparatus for sequentially testing electrical characteristics of chips includes an imaging unit for capturing images of the electrode pads of the inspection substrate, and a unit for calculating contact positions at which the probes are expected to contact with the electrode pads. The probe apparatus further includes a storage unit for storing correction data in which reference points on a reference substrate are associated with correction amounts corresponding to differences between actual and calculated contact positions of the reference points, and a unit for obtaining actual contact positions for the electrode pads by measuring relative positions of the electrode pads with respect to the reference points and correcting the calculated contact positions of the electrode pads based on the relative positions and the correction data. | 2008-10-02 |
20080238464 | SYSTEM AND METHOD OF MITIGATING EFFECTS OF COMPONENT DEFLECTION IN A PROBE CARD ANALYZER - A system and method of mitigating the effects of component deflections in a probe card analyzer system may implement three-dimensional comparative optical metrology techniques to model deflection characteristics. An exemplary system and method combine non-bussed electrical planarity measurements with fast optical planarity measurements to produce “effectively loaded” planarity measurements. | 2008-10-02 |
20080238465 | BURN-IN SYSTEM WITH HEATING BLOCKS ACCOMODATED IN COOLING BLOCKS - A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces. | 2008-10-02 |
20080238466 | TEMPERATURE SENSING AND PREDICTION IN IC SOCKETS - An apparatus is provided which preferably combines temperature sensing and prediction for more accurate temperature control of integrated circuits. An IC temperature sensing and prediction device includes a current sensing device that measures current passing through an IC, and a temperature control apparatus that measures a surface temperature of the IC. The device further includes an electronic controller that calculates the power consumed by the IC according to the measured current and adjusts the temperature of a heater or cooler responsive to the measured surface temperature and power consumption. | 2008-10-02 |
20080238467 | REINFORCED CONTACT ELEMENTS - Embodiments of reinforced resilient elements and methods for fabricating same are provided herein. In one embodiment, a reinforced resilient element includes a resilient element configured to electrically probe an unpackaged semiconductor device to be tested, the resilient element having a first end and an opposing second end; and a reinforcement member having a first end affixed to the resilient element at the first end thereof or at a point disposed between the first and the second ends of the resilient element, an opposing second end disposed in a direction towards the second end of the resilient element, and a resilient portion disposed between the first and second ends, wherein the resilient portion is not affixed to the resilient element. | 2008-10-02 |
20080238468 | Integrated circuit chip and method for testing an integrated circuit chip - In a method or apparatus such as an integrated circuit (IC) chip including a plurality of circuits for executing a plurality of testmodes, a testmode entry code specifying one of the plurality of testmodes and one of an unrestricted private testmode category and a restricted public testmode category is received. Execution of only a public testmode of the plurality of testmodes is enabled when the testmode entry code specifies the restricted public testmode category. Execution of all of the plurality of testmodes is enabled when the testmode entry code specifies the unrestricted private testmode category. | 2008-10-02 |
20080238469 | Semiconductor Device and Semiconductor Device Module - To provide a semiconductor module and a semiconductor device enabling more accurate testing of the connection state of the internal wiring between the semiconductor devices. The semiconductor device has switches SW | 2008-10-02 |
20080238470 | OPERATING METHOD OF TEST HANDLER - Operation methods of test handler are disclosed. The pick-and-place apparatus picks up semiconductor devices from first loading compartments arrayed in a matrix on a first loading element, moves, and places onto second loading compartments arrayed in a matrix on a second loading element. Pickers of the pick-and-place apparatus pick up the semiconductor devices from the first loading compartments and place them selectively onto a plurality of adjacent odd rows or a plurality of adjacent even rows of the second loading compartments during one operation. The pick-and-place apparatus includes a relatively large number of the pickers, preferably arrayed in a matrix, and thus performs loading and unloading of semiconductor devices at a relatively high speed. | 2008-10-02 |
20080238471 | ELECTRICAL INSPECTION METHOD AND METHOD OF FABRICATING SEMICONDUCTOR DISPLAY DEVICES - A method of electrically inspecting semiconductors display device, which is capable of inspecting whether a signal is normally input to the pixels and whether an electric charge is normally held by the holding capacitors without using the video signal line as a passage for reading the electric charge and without separately providing an inspection-dedicated circuit. | 2008-10-02 |
20080238472 | Low Power Mode Fault Recovery Method, System and Apparatus - A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. | 2008-10-02 |
20080238473 | Push-Pull Pulse Register Circuit - A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having second-inverter input and second-inverter output, a third logic inverter having third-inverter input and third-inverter output and configured to receive logic input data at the third-inverter input, a first logic gate having first-gate input, first-gate output, and first-gate control input, and a second logic gate having second-gate input, second-gate output, and second-gate control input. The third-inverter input is coupled to the first-gate input; the third-inverter output is coupled to the second-gate input; the second-inverter input is coupled to the second-gate output and the first-inverter output; the second-inverter output is coupled to the first-gate output and the first-inverter input; the first-gate control input is coupled to the second-gate control input; and the first-gate and the second-gate control inputs are configured to receive a clock pulse. | 2008-10-02 |
20080238474 | BOOSTER CIRCUITS FOR REDUCING LATENCY - A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition. | 2008-10-02 |
20080238475 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 2008-10-02 |
20080238476 | Configurable time borrowing flip-flops - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 2008-10-02 |
20080238477 | TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE - An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile. | 2008-10-02 |
20080238478 | FPGA architecture at conventonal and submicron scales - Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array. | 2008-10-02 |
20080238479 | REVERSIBLE SEQUENTIAL ELEMENT AND REVERSIBLE SEQUENTIAL CIRCUIT THEREOF - A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output. | 2008-10-02 |
20080238480 | REVERSIBLE SEQUENTIAL APPARATUSES - A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set to a constant level so that the second output line and the first output line have the same outputs. | 2008-10-02 |
20080238481 | LEVEL SHIFT CIRCUIT - In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W | 2008-10-02 |
20080238482 | Transmitter swing control circuit and method - disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver. | 2008-10-02 |
20080238483 | Reduced-Delay Clocked Logic - Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from affecting the current state of the clocked logic circuit during the first portion of the clock cycle. The next state of the clocked logic circuit is completely determined based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle. | 2008-10-02 |
20080238484 | LOCAL CLOCK BUFFER (LCB) WITH ASYMMETRIC INDUCTIVE PEAKING - A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (V | 2008-10-02 |
20080238485 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell. | 2008-10-02 |
20080238486 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS - A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact. | 2008-10-02 |
20080238487 | Duty cycle comparator - A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals. | 2008-10-02 |
20080238488 | Methods and apparatus for power monitoring with sequencing and supervision - Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein comprises supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail. | 2008-10-02 |
20080238489 | Fast Phase-Frequency Detector Arrangement - The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement. This provides the advantage that behavior of the charge pump circuit can alleviate extra ripple generated by the detector arrangement. | 2008-10-02 |
20080238490 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a control unit for outputting an oscillation enable signal in synchronization with transitions of an input clock and buffering the input clock to output a comparison clock corresponding to an activation timing of the oscillation enable signal. A reference frequency generating unit outputs a reference clock having a predetermined frequency based on the oscillation enable signal. First and second counting units count clocking numbers of the reference clock and the comparison clock respectively until a preset count value. A comparing unit compares the clocking number of the reference clock with that of the comparison clock to generate a comparison signal. | 2008-10-02 |
20080238491 | Interface circuit - An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver. | 2008-10-02 |
20080238492 | Slew-rate detection circuit using switched-capacitor comparators - In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal. | 2008-10-02 |
20080238493 | Analog comparator with precise threshold control - In general, in one aspect, the disclosure describes an apparatus that included a reference generator to receive a differential input signal and generate reference voltages having same common mode as the differential input signal. A replica bias generator is used to generate a bias signal based on the reference voltages. A comparator is used to compare the input signals to threshold voltages that are based at least in part on the bias signal. | 2008-10-02 |
20080238494 | METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION - The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L | 2008-10-02 |
20080238495 | FREQUENCY SYNTHESIZER AND WIRELESS COMMUNICATION DEVICE UTILIZING THE SAME - A frequency synthesizer includes a voltage-controlled oscillator to output an oscillation signal of a oscillating frequency in correspondence with a oscillation controlling voltage that is input to the oscillator, a first frequency-divider to subject the oscillation signal to frequency-division and output a first frequency signal, a second frequency-divider to subject the first frequency signal to frequency-division and output a second frequency signal, a controlling voltage generator to generate the oscillation controlling voltage corresponding to a phase difference between a reference clock signal and the second frequency signal, a frequency detector to detect a frequency difference between the second frequency signal and the reference clock signal, and a controller which controls a free-running frequency of the first frequency divider to minimize the frequency difference. | 2008-10-02 |
20080238496 | Current mode receiver - A current mode receiver is provided. The current mode receiver includes a first current mirror duplicating an input current to output a first output current, a second current mirror duplicating the first output current to output a second output current, a third current mirror duplicating a reference current to output a third output current, and means for pulling high or low an output voltage based on the second output current and the third output current. The first through third current mirrors are respectively inputted and outputting through gain boost circuits to increase the input and output impedance thereof. | 2008-10-02 |
20080238497 | OPERATIONAL AMPLIFIER HAVING ITS COMPENSATOR CAPACITANCE TEMPORARILY DISABLED - An operational amplifier includes a differential amplifier connected between an input and an output port of the operational amplifier, a phase compensator capacitance connected between the differential amplifier and the output port, a switching transistor for controlling the connection between the phase compensator capacitance and the differential amplifier, a detection transistor responsive to a potential difference between the input and output ports to be rendered conductive, and a control transistor responsive to the detection transistor for controlling the switching transistor. The operational amplifier has its slew rate improved without detracting from stability against oscillation and continuity of the output waveform. | 2008-10-02 |
20080238498 | CLOCK GENERATOR, METHOD FOR GENERATING CLOCK SIGNAL AND FRACTIONAL PHASE LOCK LOOP THEREOF - A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal. | 2008-10-02 |
20080238499 | CUSTOMIZABLE POWER-ON RESET CIRCUIT BASED ON CRITICAL CIRCUIT COUNTERPARTS - A power-on-reset circuit (POR) for integrated circuits that detects the minimum power levels needed to operate the most critical circuit(s) reliably. The circuit is implemented in a customized POR built into a custom IC, and emulates the critical circuit transistors in the custom IC using mimicking counterparts which are similarly affected by changes in temperature and process variations as the main circuit components. The mimicking counterparts may have smaller dimensions, to draw less current but still emulate the characteristics of the main working circuit components. Each critical sub-circuit of the main circuit may have a mimicking POR, and the multiple PORs may have their outputs combined by logic so that subtle failure modes can be modeled in the POR. The POR allows operation of the main circuit to continue at the lowest possible voltage levels while reducing the risk of unexpected results or undetected non-catastrophic failures. The POR also implements safety margins for the operation of the main circuit and tracks process sensitivity. | 2008-10-02 |
20080238500 | Power-up signal generating circuit and method for driving the same - A power-up signal generating circuit that prevents repeatedly generating a power-up signal even when there is noise on an external voltage. The power-up signal generating circuit includes a level detector, a level comparator, and a reentry protector. The level detector is configured to deactivate a first level detection signal when a level of an external voltage increases above a upper limit reference voltage. The level comparator is configured to deactivate a second level detection signal when the level of the external voltage increases above a lower limit reference voltage. The reentry protector is configured to activate the power-up signal in response to the second level detection signal and deactivate the power-up signal in response to a deactivation of the first level detection signal. | 2008-10-02 |
20080238501 | Initialization signal generating circuit - An initialization signal generating circuit includes a voltage distributor, a first initialization signal generator, a second initialization signal, and a controller. The voltage distributor outputs a voltage signal in response to an external voltage. The first initialization signal generator outputs a first initialization signal in response to the voltage signal output from the voltage distributor. The second initialization signal generator outputs a second initialization signal in response to the voltage signal output from the voltage distributor. The controller blocks the external voltage supplied to the voltage distributor and the first and second initialization signal generators, in response to the first and second initialization signals. | 2008-10-02 |
20080238502 | Delay cell and phase locked loop using the same - A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock. | 2008-10-02 |
20080238503 | Injection locked LC VCO clock deskewing - In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock. | 2008-10-02 |
20080238504 | Phase locked loop - A phase locked loop includes a first clock divider configured to divide a first input clock to generate a second input clock; a clock selector configured to selectively output one of the first input clock and the second input clock in response to a test signal; a phase/frequency detector configured to detect phase and frequency differences between the selected output clock of the clock selector and a feedback clock to generate a detection signal corresponding to the detected phase and frequency differences; a control voltage generator configured to generate a control voltage having a voltage level corresponding to the detection signal; a voltage controlled oscillator configured to generate an internal clock having a frequency corresponding to the control voltage; and a second clock divider configured to divide the internal clock to generate the feedback clock. | 2008-10-02 |
20080238505 | System and method for an automatic coarse tuning of a voltage controlled oscillator in a phase-locked loop (PLL) - Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop. | 2008-10-02 |
20080238506 | SEMICONDUCTOR MEMORY DEVICE USING MODULATION CLOCK SIGNAL AND METHOD FOR OPERATING THE SAME - A semiconductor memory device is capable of performing a modulation of output clock signals in order to prevent EMI characteristics of a system having the semiconductor memory device from being degraded. The semiconductor memory device includes a modulation clock signal generator, a clock input unit, a first modulation unit, a delay locked loop circuit, and a second modulation unit. The modulation clock signal generator generates a modulation clock signal. The clock input unit generates a reference clock signal from a system clock signal. The first modulation unit generates a modulated clock signal by modulating the reference clock signal with the modulation clock signal. The delay locked loop circuit performs a delay locking operation on the modulated clock signal to generate a delay locked clock signal. The second modulation unit modulates the delayed locked clock signal with the modulation clock signal. | 2008-10-02 |
20080238507 | Semiconductor memory device - A semiconductor memory device includes a phase comparator, a delay chain, a delay controller, a fine delay chain, a delay model, a locking state detector, and a fine delay controller. The phase comparator compares a phase of a reference clock with that of a feedback clock. The delay chain delays and outputs the reference clock. The delay controller controls a delay value of the delay chain in response to the comparison result of the phase comparator. The fine delay chain outputs a delay value of a clock outputted from the delay chain. The delay model delays a clock to a modeled delay value to provide a delayed clock as the feedback clock. The locking state detector generates a locking variation signal corresponding to a phase difference between the reference clock and the feedback clock. The fine delay controller controls a fine adjustment value of the fine delay chain. | 2008-10-02 |
20080238508 | Input Clock Detection Circuit for Powering Down a PLL-Based System - An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal. | 2008-10-02 |
20080238509 | BOUNDING A DUTY CYCLE USING A C-ELEMENT - A duty cycle bounding circuit for restoring the unbounded duty cycle of a periodic signal such as a forwarded clock signal. The duty cycle bounding circuit comprises a state holding logic element, such as a C-element, and a delay line. The delay line feeds back an inverted version of the output of the state holding logic element to an input of the state holding logic element. The periodic signal is applied to another input of the state holding logic element. | 2008-10-02 |
20080238510 | Low leakage state retention circuit - In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse. | 2008-10-02 |
20080238511 | Control Device with Terminal 15 - Holding Circuit - A terminal state of a terminal | 2008-10-02 |
20080238512 | Circuit and method for data alignment - A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data. | 2008-10-02 |
20080238513 | Hysteresis Circuit Without Static Quiescent Current - A hysteresis circuit including a comparator and capacitive voltage divider circuit. The capacitive voltage divider circuit includes a first capacitor coupled between an input terminal and a positive comparator input, a second capacitor coupled between ground and the positive comparator input, and a third capacitor coupled between the comparator output and positive comparator input. A reference voltage is applied to the negative comparator input. The comparator is powered by the input signal provided on the input terminal. When the voltage on the positive comparator input is less than the reference voltage, the third capacitor is effectively coupled in parallel with the first capacitor. When the voltage on the positive comparator input is greater than the reference voltage, the third capacitor is effectively coupled in parallel with the second capacitor. | 2008-10-02 |
20080238514 | LEVEL-CONVERTED AND CLOCK-GATED LATCH AND SEQUENTIAL LOGIC CIRCUIT HAVING THE SAME - A level-converted and clock-gated latch includes a pulse generator, a level converting unit, and a latch circuit. The pulse generator is provided with a first power-supply voltage and generates a pulse signal having a first voltage level, in response to a clock signal. The level converting unit is provided with a second power-supply voltage and generates an intermediate clock signal having a second voltage level, in response to an inverted clock signal, the clock signal and an enable signal. The latch circuit is provided with the second power-supply voltage, latches the intermediate clock signal, and provides a gated clock signal having the second voltage level. An activation interval of the gated clock signal is controlled based on the enable signal. | 2008-10-02 |
20080238515 | Signal generation apparatus for frequency conversion in communication system - A signal generation apparatus includes a signal generation portion and a phase compensator. The phase compensator generates a phase error control signal that maintains a phase difference between the in-phase and quadrature-phase signals generated by the signal generation portion. The phase compensator includes an offset compensator and a delay compensator. The offset compensator is set to compensate for an offset voltage through the phase compensator. The delay compensator is set to compensate for a difference of delays through paths for the in-phase and quadrature-phase signals within the phase compensator. | 2008-10-02 |
20080238516 | Timing interpolator with improved linearity - A programmable timing interpolator circuit includes low output impedance buffer circuitry driving a node having a capacitance that varies in response to a programmed delay to be introduced by the interpolator. The low output impedance buffer circuitry receives a subset of course delay signals and, after buffering, provides the buffered course delay signals to fine delay circuitry. The buffer may include two source follower stages coupled to each other. The first source follower stage shifts the level of the received signal down. The second source follower stage shifts the level of the signal from the first source follower stage up. The first and second source follower stages are implemented using NMOS and PMOS technology. | 2008-10-02 |
20080238517 | Oscillator Circuit and Semiconductor Device - An oscillator circuit includes a capacitance element; an inverter outputting an inverted voltage at a first terminal of the capacitance element; a voltage source including a resistor and an NMOS transistor connected in series between a first high-potential power supply and a ground power supply and outputting a voltage from a node to which the resistor and the NMOS transistor are connected; a switch circuit connecting a second terminal of the capacitance element to the voltage source or the ground power supply in accordance with the voltage output from the inverter; and a constant-current source connected to a second high-potential power supply and allowing, regardless of changes in the voltage and temperature of the second high-potential power supply within certain ranges, flow of a constant current into or out of the first terminal of the capacitance element in accordance with the voltage output from the inverter. | 2008-10-02 |
20080238518 | PROCESS, VOLTAGE, AND TEMPERATURE COMPENSATED CLOCK GENERATOR - According to some embodiments, a process, voltage, and temperature compensated clock generator is disclosed. The clock generator may be a charge-charge clock generator including a first load capacitive element and a second load capacitive element. A process, voltage, and temperature compensated current source is coupled to the charge-charge clock generator, and is used to charge the first load capacitive element and the second load capacitive element. | 2008-10-02 |
20080238519 | Signaling circuit and method for integrated circuit devices and systems - Integrate circuit systems and semiconductor devices for generating, transmitting, receiving, and manipulating clock and/or data signals. A semiconductor device including a clock circuit having field effect transistors and a clock driver circuit having bipolar junction transistors is disclosed. The clock circuit may provide a first clock output having a first voltage swing. The clock driver circuit may receive the first clock output and provide a second clock output having a second voltage swing substantially less than the first voltage swing. The field effect transistors can be junction field effect transistors or insulated gate field effect transistors, or the like. The system/devices further including a translator circuit, for translating signals with a lower voltage swing into signals with a higher voltage swing, and a circuit block, for operating at such higher voltage swing. Further included are global and local wiring networks for communicating the signals between and among the individual circuits or system components. | 2008-10-02 |
20080238520 | POWER ELECTRONIC MODULE INCLUDING DESATURATION DETECTION DIODE - A power electronic module includes: a switch module including a desaturation detection diode and a power semiconductor switch, and wherein the desaturation detection diode is coupled to a switching connection of the power semiconductor switch; and a driver module coupled to the switch module, wherein the driver module is configured for obtaining a voltage signal across the desaturation detection diode and the power semiconductor switch and configured for turning off the power semiconductor switch upon the voltage signal exceeding a threshold. In one example, the driver module is discrete from the switch module. In another example, the switch module and driver modules are configured to respectively provide and receive a voltage signal of less than or equal to seventy volts. | 2008-10-02 |
20080238521 | LOW DIFFERENTIAL OUTPUT VOLTAGE CIRCUIT - A low differential output voltage circuit having a voltage generator and a differential output unit is provided. The voltage generator includes a first PMOS transistor, a first amplifier circuit, a unit gain stage, a first NMOS transistor, a second NMOS transistor. The differential output unit includes a first controlled current source, a second controlled current source, a common voltage circuit, a first switch, a second switch, a third switch, and a fourth switch. Due to the voltage generator directly provides a common mode voltage to the differential output unit, and the first amplifier circuit and the unit gain stage could overcome a channel modulation effect of MOS transistors and enhance the driving ability of the common mode voltage respectively. Thus, a response time of the invention is decreased, and an output current of the differential output unit is in a proportion to the reference current received by the voltage generator. | 2008-10-02 |
20080238522 | METHOD FOR INCORPORATING TRANSISTOR SNAP-BACK PROTECTION IN A LEVEL SHIFTER CIRCUIT - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail. | 2008-10-02 |
20080238523 | LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail. | 2008-10-02 |
20080238524 | LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driving circuit is provided by the present invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between the level shifter and the buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter. | 2008-10-02 |
20080238525 | High Speed Level Shifter - The invention relates to a level shifter comprising an input stage having a parasitic capacitance and a first input terminal for applying an input signal, a limiter stage having a second input terminal for applying a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage, an output stage being coupled between a second supply terminal and said limiter stage and providing an output signal which is a level shifted version of said input signal, and a current source being adapted for injecting a current pulse into said parasitic capacitance dependent on variations of said switching signal over time. | 2008-10-02 |
20080238526 | Fast Switching Circuit With Input Hysteresis - The present invention relates to a switching circuit and a method of controlling a threshold voltage of a semiconductor switching element of the switching circuit, wherein a bulk voltage of the semiconductor switching element (M | 2008-10-02 |
20080238527 | Switching Device for Bi-Directionally Equalizing Charge Between Energy Accumulators and Corresponding Methods - A switching device for bi-directionally equalizing charge between energy accumulators, particularly between capacitive energy accumulators in a motor vehicle electric system, includes: an integrated starter generator; a first connection coupled to the integrated starter generator; a second connection coupled to an energy source; a controllable transfer gate having a first load current-conducting path connected between the first and second connection, and a controllable switching controller having a second load current-conducting path connected between the first and second connection in parallel to the first load current-conducting path. There is also provided a motor vehicle electric system with such a switching device, and the implementation and use of a switching controller in a transfer gate for such a switching device. | 2008-10-02 |
20080238528 | MOSFET GATE INTERFACE - In some embodiments a power circuit includes a driver output, a MOSFET, and circuitry to ensure a full and fast positive drive to a gate of the MOSFET when the driver output goes to a high signal level, and to ensure a full and fast low negative drive to the gate of the MOSFET when the driver output goes to a low signal level. Other embodiments are described and claimed. | 2008-10-02 |
20080238529 | TEMPERATURE DETECTION CIRCUIT - A PWM signal generation circuit in an IPM includes an amplification circuit amplifying a voltage across terminals of a temperature sensor, a comparison circuit generating a PWM signal based on a triangular wave signal and an output signal of the amplification circuit, and a correction circuit setting an amplification ratio of the amplification circuit such that a pulse width of the PWM signal is set to a reference pulse width in an adjustment mode in which a switching element is caused to have a reference temperature. Consequently, characteristic variations in the temperature sensor, the amplification circuit, and the like can be corrected, and the temperature of the switching element can be detected with high accuracy. | 2008-10-02 |
20080238530 | Semiconductor Device Generating Voltage for Temperature Compensation - An input transistor unit includes a first transistor having a control electrode to which a reference voltage is supplied. An output transistor unit includes a diode-connected second transistor. At least one of the input transistor unit and the output transistor unit further includes a third transistor that is diode-connected and connected in series with the corresponding first transistor or the second transistor and outputs a current in the same direction as the corresponding transistor does. The number of transistors included in the input transistor unit and the number of transistors included in output transistor unit are different from each other. The size of transistors included in the input transistor unit differs from that of transistors included in the output transistor unit. | 2008-10-02 |
20080238531 | SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS - A coupling system may include an rf-SQUID having a loop of superconducting material interrupted by a compound Josephson junction; and a first magnetic flux inductor configured to selectively provide a mutual inductance coupling the first magnetic flux inductor to the compound Josephson junction, wherein the loop of superconducting material positioned with respect to a first and second qubits to provide respective mutual inductance coupling therebetween. The coupling system may further include a second magnetic flux inductor configured to selectively provide a second magnetic flux inductor mutual inductance coupling the second magnetic flux inductor to the compound Josephson junction. A superconducting processor may include the coupling system and two or more qubits. A method may include providing the first, the second and the third mutual inductances. | 2008-10-02 |
20080238532 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - With an ultrasound pulser suitable for application to a medical ultrasound system, and so forth, a high voltage power supply of a transducer drive circuitry, on both high potential and low potential sides, is rendered variable in a range of 0 V on the order of ±200 V, thereby implementing a semiconductor integrated circuit wherein a plurality of the ultrasound pulsers corresponding to a plurality of channels, respectively, are integrally formed on a small area. The ultrasound pulser has a configuration wherein, in a MOSFET gate drive circuitry, an input voltage pulse is converted into a current pulse, and the current pulse is converted again into a voltage pulse on the basis of a high potential side voltage +HV, and a low potential side voltage −HV, applied to a transducer drive circuitry, whereupon voltage level shift in the input voltage pulse is attained, and a voltage pulse swing of an output buffer of the MOSFET gate drive circuitry receiving a shifted voltage pulse is generated by the MOSFET gate drive circuitry similarly on the basis of the high potential side voltage +HV, and the low potential side voltage −HV, applied to the transducer drive circuitry. The MOSFET gate drive circuitry is DC-coupled with the transducer drive circuitry. | 2008-10-02 |
20080238533 | Semiconductor Device - A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units. | 2008-10-02 |
20080238534 | PHASE SHIFTING IN DLL/PLL - The disclosure relates to phase shifting in Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs). A charge pump in the DLL or PLL includes a capacitor connected in parallel to an output node. A primary current switching circuit charges the capacitor with a source current and discharges the capacitor with a sink current. A supplemental source circuit sources a positive phase shift producing current which has a range of magnitudes. A magnitude of the positive phase shift producing current is determined by at least one source selection signal. A supplemental sink circuit for sources a negative phase shift producing current which has a range of magnitudes. A magnitude of the negative phase shift producing current is determined by at least one sink selection signal. | 2008-10-02 |
20080238535 | POWER SUPPLY CIRCUIT AND DISPLAY DEVICE THEREWITH - An unnecessary through current is suppressed and insufficiency of an output electric potential and increase in power consumption are suppressed in a power supply circuit using a charge pump method. In order to suppress a reduction in an output electric potential VPP as well as suppressing transient through currents I | 2008-10-02 |
20080238536 | SUPPLY VOLTAGE GENERATING CIRCUIT - A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply. | 2008-10-02 |
20080238537 | METHODS AND SYSTEMS FOR DRIVER NOISE REDUCTION IN A MEMS GYRO - Systems and methods for reducing driver noise in a MicroElectro-Mechanical Systems (MEMS) gyroscope system are disclosed. An example system includes motor drivers, two proof masses, two substrate electrodes, two motor drive capacitors, and two stationary capacitors. The motor drivers drive the proof masses through the motor driver capacitors. The stationary capacitors output a signal based on the drive signal from the motor drivers. A differential amplifier receives a sense signal from the proof masses and a noise signal from the stationary capacitors, and subtracts the noise signal from the rate sense signal, thereby producing a sense signal with reduced driver noise. | 2008-10-02 |
20080238538 | RECEIVING DEVICE AND RELATED METHOD FOR CALIBRATING DC OFFSET - A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal. | 2008-10-02 |
20080238539 | ARRANGEMENT FOR CANCELING OFFSET OF AN OPERATIONAL AMPLIFIER - Operational amplifier circuitry drives a device which may be run with a combination of output signals fewer in number than the output signals delivered from plural output circuits. Each output circuit adjusts the gain of an input signal supplied to its operational amplifier. An output selector selects and outputs output signals from the output circuits necessary for driving the device. A decision circuit compares an output signal not selected with a reference signal to adjust the gain of the output circuits to thereby cancel the offset of the operational amplifier. The operational amplifier has sets of feedback elements different in number between the sets formed by capacitances. Switching is made from one set to another until the decision circuit makes an acceptable decision. Offset may thus be canceled during the operational amplification even in case capacitive or resistance element is connected in circuit outside the operational amplifier. | 2008-10-02 |
20080238540 | POWER AMPLIFIER WITH NOISE SHAPING - A power amplifier with noise shaping is disclosed. The power amplifier with noise shaping is able to minimize the noise interference a regular power amplifier encounters. The power amplifier includes a differential-mode integrator, a driving unit, and a low pass filter and integration unit. The differential-mode integrator receives a differential-mode input signal and a differential-mode feedback signal and performs integration operations to output a differential-mode intermediate signal. The driving unit outputs a differential-mode output signal and drives a load according to the differential-mode intermediate signal. The low pass filter and integration unit performs a filtering operation on the differential-mode output signal and integration operations to output the differential-mode feedback signal to the differential-mode integrator. | 2008-10-02 |
20080238541 | SPATIALLY DISTRIBUTED AMPLIFIER CIRCUIT - An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array. | 2008-10-02 |
20080238542 | Variable gain amplifier and method for achieving variable gain amplification with high bandwidth and linearity - A fine granularity, wide-range variable gain amplifier (“VGA”) comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain. | 2008-10-02 |
20080238543 | Digital Amplifier with Analogue Error Correction Circuit - Digital amplifier for amplifying a digital input signal, comprising a digital modulator for converting the digital input signal into an amplitude-discrete and temporally analogue signal, comprising an analogue error correction circuit which modulates the pulse widths of the amplitude-discrete and temporally analogue signal in dependence on an analogue error signal, comprising a power switching stage, the input of which receives the signal modulated by the error correction circuit and which delivers the modulated signal amplified at an output and comprising an analogue feedback circuit which, in dependence on the output signal of the digital modulator and on the output signal of the power switching stage, generates the analogue error signal for adjusting the analogue error correction circuit. | 2008-10-02 |
20080238544 | AMPLIFIER PRE-DISTORTION SYSTEMS AND METHODS - A method of optimizing performance of a multiple path amplifier includes: splitting an input signal to derive a respective sub-signal for each branch of the multiple path amplifier; independently pre-distorting each sub-signal using a known performance characteristic of its associated branch of the multiple path amplifier; and supplying each pre-distorted sub-signal to its associated branch of the multiple amplifier. | 2008-10-02 |
20080238545 | LINEARIZED CLASS AB BIASED DIFFERENTIAL INPUT STAGE - A linearized bipolar differential input stage that contains two high gain current mirrors coupled in series with the input voltage signal through the input transistors to allow the output differential current to greatly exceed the DC output current in a Class AB fashion. The extended output current range over and above the DC current significantly lowers the percentage of effects for both DC offset and noise in the output signal path. Non-linearity cancellation is also optimized for the lowest level of input distortion through adjusting transistor area ratios. | 2008-10-02 |
20080238546 | FULLY DIFFERENTIAL CLASS AB AMPLIFIER AND AMPLIFYING METHOD USING SINGLE-ENDED, TWO-STAGE AMPLIFIER - A fully differential amplifier includes a first single-ended current mirror type fully differential amplifier outputting a first output signal by two stage amplifying a difference between a first input signal and a second input signal and a second single-ended current mirror type fully differential amplifier outputting a second output signal by two stage amplifying a difference between the first input signal and the second input signal. A first tail of the first single-ended current mirror type fully differential amplifier and a second tail of the second single-ended current mirror type fully differential amplifier are connected to each other and the first output signal and the second output signal are differential signals. | 2008-10-02 |