39th week of 2010 patent applcation highlights part 20 |
Patent application number | Title | Published |
20100244048 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate ( | 2010-09-30 |
20100244049 | Silicon carbide semiconductor device with schottky barrier diode and method of manufacturing the same - A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements. | 2010-09-30 |
20100244050 | SEMICONDUCTOR DEVICE - A semiconductor device which is capable of operating at an operation frequency “f”, includes a substrate, a first element unit and a second element unit. The substrate has a thermal diffusion coefficient “D”. The first element unit is formed on the substrate. The first element includes a first active element. The second element unit is adjacent to the first element unit on the substrate. The second element includes a second active element. The second active element acts on a different timing from the first active element. Moreover, a distance of between a first gravity center of the first element unit and a second gravity center of the second element unit is equal to or less than twice of a thermal diffusion length (D/πf) | 2010-09-30 |
20100244051 | Semiconductor Device and Manufacturing Method Thereof - An object is to realize an integrated circuit included in a semiconductor device which has multiple functions, or to increase the size of an integrated circuit even when the integrated circuit is formed using a silicon carbide substrate. The integrated circuit includes a first transistor including an island-shaped silicon carbide layer provided over a substrate with a first insulating layer interposed therebetween, a first gate insulating layer provided over the silicon carbide layer, and a first conductive layer provided over the first gate insulating layer and overlapped with the silicon carbide layer; and a second transistor including an island-shaped single crystal silicon layer provided over the substrate with a second insulating layer interposed therebetween, a second gate insulating layer provided over the single crystal silicon layer, and a second conductive layer provided over the second gate insulating layer and overlapped with the single crystal silicon layer. | 2010-09-30 |
20100244052 | HIGH OUTPUT GROUP III NITRIDE LIGHT EMITTING DIODES - A light emitting diode is disclosed that includes a silicon carbide substrate and a light emitting structure formed from the Group III nitride material system on the substrate. The diode has an area greater than 100,000 square microns and has a radiant flux at 20 milliamps current of at least 29 milliwatts at its dominant wavelength between 390 and 540 nanometers. | 2010-09-30 |
20100244053 | Light emitting device having pillar structure with hollow structure and the forming method thereof - A light emitting device, includes a substrate; a first semiconductor layer on the substrate; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; a transparent conductive layer on the second semiconductor layer; and a plurality of pillar structures with a hollow structure in the portion surface of the first semiconductor layer, thereby, the light extraction efficiency of the light emitting device can be improved due to the pillar structures with a hollow structure. | 2010-09-30 |
20100244054 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR COMPOSITE DEVICE - A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane. | 2010-09-30 |
20100244055 | SEMICONDUCTOR-BASED SUB-MOUNTS FOR OPTOELECTRONIC DEVICES WITH CONDUCTIVE PATHS TO FACILITATE TESTING AND BINNING - The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns. | 2010-09-30 |
20100244056 | Addressable Or Static Light Emitting, Power Generating Or Other Electronic Apparatus - The present invention provides an addressable or static electronic apparatus, such as a light emitting display or a power generating apparatus. An exemplary apparatus comprises a substrate having a plurality of cavities; a plurality of first conductors coupled to the substrate and at least partially within the cavities, with the plurality of first conductors having a first and substantially parallel orientation; a plurality of light emitting diodes, photovoltaic diodes or other electronic components coupled to the plurality of first conductors and having a second orientation substantially normal to the first orientation; and a plurality of substantially optically transmissive second conductors coupled to the plurality of diodes and having a third orientation substantially normal to the second orientation and substantially perpendicular to the first orientation. In an exemplary method, the plurality of electronic components in a suspending medium are deposited within the plurality of cavities, and the plurality of electronic components are oriented using an applied field, followed by a bonding of the plurality of electronic components to the plurality of first conductors. | 2010-09-30 |
20100244057 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device, including: a first substrate on which a plurality of light emitting elements are formed; a second substrate that is disposed to be opposed to the first substrate; a primary dam member that is provided between the first substrate and the second substrate in order to surround the plurality of light emitting elements; a filler that is filled between the first substrate and the second substrate and in a first region defined by the primary dam member, an auxiliary dam member that is between the first substrate and the second substrate and in a second region outside the first region, and is made of porous material; and an inorganic sealant that is provided between the first substrate and the second substrate and in a third region outside the first region and the second region, and is jointed to the first substrate and the second substrate. | 2010-09-30 |
20100244058 | Light emitting diode package - A light emitting diode package includes a substrate, a plurality of light emitting diode chips, a fluorescence layer, and a plurality of reflecting layers. The light emitting diode chips, the fluorescence layer, and the reflecting layers are disposed on the substrate. The fluorescence layer covers the light emitting diode chips, and the reflecting layers are disposed right above the light emitting diode chips, respectively. | 2010-09-30 |
20100244059 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An aspect of the present invention provides a semiconductor device, in which densely packaging and high performance of optical elements are realized by a simple manufacturing process. The semiconductor device includes: a first chip module, a second chip module and a bonding layer. The first chip module includes a plurality of optical chips that are bonded within a substantially same plane with a first resin layer. The second chip module includes a plurality of control semiconductor chips and a plurality of connecting chips. The connecting chips include conductive materials piercing through the connecting chips. The control semiconductor chips and the connecting chips are bonded within a substantially same plane with a second resin layer. And the optical chips and the control semiconductor chips are electrically connected through the connecting chips. | 2010-09-30 |
20100244060 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF LIGHT EMITTING CELLS AND PACKAGE MOUNTING THE SAME - Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type semiconductor layer located on a portion of the N-type semiconductor layer. The plurality of light emitting cells are bonded to a submount substrate. Accordingly, heat generated from the light emitting cells can be easily dissipated, so that a thermal load on the light emitting device can be reduced. Meanwhile, since the plurality of light emitting cells are electrically connected using connection electrodes or electrode layers formed on the submount substrate, it is possible to provide light emitting cell arrays connected to each other in series. Further, it is possible to provide a light emitting device capable of being directly driven by an AC power source by connecting the serially connected light emitting cell arrays in reverse parallel to each other. | 2010-09-30 |
20100244061 | LED illumination device - An LED illumination device includes: a substrate; one or more red LED chips arranged on the substrate; a plurality of blue LED chips arranged on the substrate; and a plurality of third-color LED chips arranged on the substrate. Respective centers of the red LED chips are arranged on a circumference of a first circle having as its center a point on the substrate, respective centers of the blue LED chips being arranged on the circumference of a second circle concentric with and greater than the first circle, respective centers of the third-color LED chips being arranged in a region between the first circle and the second circle. | 2010-09-30 |
20100244062 | WHITE LIGHT EMITTING ELEMENT - This invention provides a white light emitting element having a prolonged lifetime that can emit white light having high color purity. The white light emitting element comprises: opposed electrodes | 2010-09-30 |
20100244063 | NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device according to the present invention has a nitride-based semiconductor multilayer structure | 2010-09-30 |
20100244064 | LIGHT SOURCE - A light source is described herein. An embodiment of the light source comprises a reflector cup having a cavity; a light emitter located in the cavity; a first encapsulant encompassing the light emitter; and a film located adjacent the first encapsulant, the film comprising phosphor. | 2010-09-30 |
20100244065 | SEMICONDUCTOR LIGHT EMITTING DEVICE GROWN ON AN ETCHABLE SUBSTRATE - A III-nitride structure comprising a light emitting layer disposed between an n-type region and a p-type region is grown on a silicon substrate. The III-nitride structure is attached to a host, then a portion of the silicon substrate is etched away to reveal a top surface of the III-nitride structure. In some embodiments, the silicon substrate is etched to form an enclosure on the top surface of the III-nitride structure. A wavelength converting material such as phosphor may be disposed in the enclosure. | 2010-09-30 |
20100244066 | RED LIGHT FLUORESCENT MATERIAL AND MANUFACTURING METHOD THEREOF, AND WHITE LIGHT LUMINESCENT DEVICE - A red-light-emitting fluorescent material, suitable for being excited by a first light to emit red light, is provided. The red-light-emitting fluorescent material is characterized in the chemical formula (1): | 2010-09-30 |
20100244067 | PHOSPHOR PLATES FOR LEDS FROM STRUCTURED FILMS - The invention relates to a phosphor element which is based on natural and/or synthetic flake-form substrates, such as mica, corundum, silica, glass, ZrO | 2010-09-30 |
20100244068 | Method For Applying A Thin-Film Encapsulation Layer Assembly To An Organic Device, And An Organic Device Provided With A Thin-Film Encapsulation Layer Assembly Preferably Applied With Such A Method - A method for applying a thin-film encapsulation layer assembly to an organic device, which comprises a substrate which is provided with an active stack and is then provided with the thin-film encapsulation layer assembly for screening the active stack substantially from oxygen and moisture, wherein the thin-film encapsulation layer assembly is formed by applying at least one organic and at least one inorganic layer applied with PECVD or reactive sputtering, onto the active stack, wherein after application of a first organic layer a metal layer is applied to the first organic layer before an inorganic layer is applied thereto utilizing PECVD or reactive sputtering, wherein the metal layer is applied utilizing a deposition technique that causes relatively little radiation, wherein the metal layer protects the organic layer against radiation upon a subsequent PECVD or reactive sputtering process step for applying an inorganic layer. The invention also relates to an organic device manufactured with such a method. | 2010-09-30 |
20100244069 | NOVEL OLED DISPLAY ARCHITECTURE - A device is provided. The device includes first, second and third subpixels. The first sub-pixel includes an emissive layer having a first emitting material but not a second emitting material. The second sub-pixel includes an emissive layer having the second emitting material but not the first emitting material. The third sub-pixel includes an emissive layer having both the first and second emitting materials. A method of fabricating the device is provided. For a three subpixel device, a first electrode layer is deposited, having a first sub-pixel and a second sub-pixel. Then, in a first patterned deposition process, a first emitting material is deposited on the first sub-pixel and the third sub-pixel, but not the second sub-pixel. Then, in a second patterned deposition process, a second emitting material is deposited on the second sub-pixel and the third sub-pixel, but not the first sub-pixel. Then, a second electrode layer is deposited. The first, second and third subpixels may be defined, for example, by patterning in either or both of the first and second electrode layers. Preferably, the device and method include a fourth subpixel. | 2010-09-30 |
20100244070 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating an organic light emitting display device includes forming a first electrode in both a luminescent region and a part of a non-luminescent region, forming a buffer layer in the non-luminescent region, forming an insulation pattern on the buffer layer in the non-luminescent region, forming an auxiliary electrode on the insulation pattern in the non-luminescent region, forming an organic emission layer in both the luminescent region and the non-luminescent region, forming a second electrode in both the luminescent region and the non-luminescent region, and applying over-voltage to the auxiliary electrode, the organic emission layer on the auxiliary electrode and the second electrode. | 2010-09-30 |
20100244071 | Method of manufacturing led lamp - A method of manufacturing a LED lamp that is formed by sealing a LED element mounted on a substrate with glass, includes a mounting process for mounting the LED element on the substrate, a sealing member preparation process for preparing a glass sealing member that includes a concave portion being capable of housing the LED element, and a sealing process wherein the sealing member is arranged so that a forming surface of the concave portion faces the LED element, the sealing member is bonded to the substrate by thermal compression bonding, and the forming surface of the concave portion is made along the LED element. | 2010-09-30 |
20100244072 | Light-emitting devices and methods of fabricating the same - A light-emitting device includes: a substrate; a light-emitting element is mounted on a first surface of the substrate; at least one uneven heat dissipation pattern is formed on at least one surface of the substrate; and an electrode covers at least a portion of the at least one uneven heat dissipation pattern and is connected to the light-emitting element. | 2010-09-30 |
20100244073 | ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object of the present invention is to obtain an organic EL device having excellent light resistance and a method for manufacturing the same. An organic EL device comprises: a first substrate as a supporting substrate; a first electrode provided on the first substrate; an organic layer that is provided on the first electrode and includes at least an organic light-emitting layer; a second electrode provided on the organic layer; a resin layer provided to cover the first substrate and the second electrode thereon, the resin layer containing, at least in a region on the organic layer, an ultraviolet light absorber that absorbs ultraviolet light; and a second substrate arranged on the resin layer to block the organic layer from ambient air. | 2010-09-30 |
20100244074 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device and a manufacturing method are provided, in which a metal film is deposited with positional differences between edges of an insulating film and the metal film, opposite a ridge waveguide top face, utilizing an overhanging-shaped resist pattern. An opening through the insulating film is extended in width without another masking step by etching the insulation film on the ridge waveguide top face, using the metal film as a mask. The contact area between a p-side electrode and a p-type contact layer is increased and operating voltage of the semiconductor light-emitting device is reduced. | 2010-09-30 |
20100244075 | Performance Optically Coated Semiconductor Devices and Related Methods of Manufacture - The present application disclosed various embodiments of improved performance optically coated semiconductor devices and various methods for the manufacture thereof and includes depositing a first layer of a low density, low index of refraction material on a surface of a semiconductor device, depositing a multi-layer optical coating comprising alternating layers of low density, low index of refraction materials and high density, high index of refraction materials on the coated surface of the semi-conductor device, selectively ablating a portion of the alternating multi-layer optical coating to expose at least a portion of the low density first layer, and selectively ablating a portion of the first layer of low density material to expose at least a portion of the semiconductor device. | 2010-09-30 |
20100244076 | LIGHT EMITTING DEVICE COMPRISING A GREEN EMITTING SIALON-BASED MATERIAL - The invention relates to a light emitting device, especially a LED comprising a green emitting material of the composition Sr | 2010-09-30 |
20100244077 | PHOTOELECTRONIC ELEMENT AND THE MANUFACTURING METHOD THEREOF - A photoelectronic element includes a composite substrate including an electrically insulative substrate having a chamber; an intermediate layer; and an electrically conductive substrate; a bonding layer including an electrically conductive region and an electrically insulative region; a first current spreading layer; a first semiconductor stacked layer including a first semiconductor layer, an active layer, and a second semiconductor layer; a current blocking layer; a second current spreading layer; and a first electrode. | 2010-09-30 |
20100244078 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package including a light emitting device and a magnetic ring is provided. The magnetic ring surrounds the light emitting device for forming a magnetic source for applying a magnetic field to the light emitting device. | 2010-09-30 |
20100244079 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR FABRICATING THE SAME - Projections/depressions forming a two-dimensional periodic structure are formed in a surface of a semiconductor multilayer film opposing the principal surface thereof, while a metal electrode with a high reflectivity is formed on the other surface. By using the diffracting effect of the two-dimensional periodic structure, the efficiency of light extraction from the surface formed with the projections/depressions can be improved. By reflecting light emitted toward the metal electrode to the surface formed with the projections/depressions by using the metal electrode with the high reflectivity, the foregoing effect achieved by the two-dimensional periodic structure can be multiplied. | 2010-09-30 |
20100244080 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode package including a substrate; a plurality of electrodes on the substrate; a light emitting diode on the substrate; at least one wire connecting the light emitting diode and at least a first electrode of the plurality of electrodes; a reflecting member formed around the light emitting diode and being spaced apart from the light emitting diode; a cavity included in the reflecting member; a mold material including in the cavity; and a heat sink disposed under the light emitting diode and configured to emit heat generated by the light emitting diode. Further, a connection portion connecting the plurality of electrodes extends under a surface of the substrate through a portion of the substrate, and an inside surface of the reflecting member has a step-shape structure. | 2010-09-30 |
20100244081 | LIGHTING DEVICE USING HIGH POWER LED WITH MULTIPLE LEAD - The lighting device mainly contains a first material, a second material, at a light generation chip, and multiple metallic leads. The metallic leads are sandwiched between the first and second materials, and arranged in a radial manner around the indentation or the raised stand. The center of the first material has an obconical through channel and the center of the second material has either an indentation or a raised stand. The light generation chips are positioned in the center of the second material. High thermal conducting insulation paste is provided between the first material, the metallic leads, and the second material so that they are electrical insulated from each other. The present invention could achieve versatile color combinations and high brightness under superior heat dissipation effect, and could be applied in various types of packaging and welding. | 2010-09-30 |
20100244082 | QUASI-VERTICAL LIGHT EMITTING DIODE - A quasi-vertical light emitting device is provided. According to one embodiment of the present invention, the quasi-vertical light emitting diode includes a sapphire substrate; a plurality of semiconductor layers grown on the sapphire substrate, the plurality of semiconductor layers including an n-GaN layer, an active layer, and a p-GaN layer; a plurality of holes etched in the plurality of semiconductor layers, each of the plurality of holes etched to the sapphire substrate, and a plurality of sapphire holes in the sapphire substrate, each of the plurality of holes aligned with one of the plurality of sapphire holes to form hole walls, the hole walls and bottom deposited with an n-metal and each of the plurality of holes filled with another metal to form a n-electrode contact; an n-mesa in the active layer and the p-GaN layer, the n-mesa deposited with an n-metal and a passivation layer grown over the n-metal; and a p-metal layer deposited on the p-GaN layer, and a p-electrode bonded to the p-metal. | 2010-09-30 |
20100244083 | Light-Emitting Devices - Light-emitting devices are provided, the light-emitting devices include a light-emitting structure layer having a first conductive layer, a light-emitting layer and a second conductive layer sequentially stacked on a first of a substrate, a plurality of seed layer patterns formed apart each other in the first conductive layer; and a plurality of first electrodes formed through the substrate, wherein each of the first electrodes extends from a second side of the substrate to each of the seed layer patterns. | 2010-09-30 |
20100244084 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - A light emitting device (LED), an LED package, and a lighting system including the LED package are provided. The light emitting device (LED) may include a light emitting structure, a carrier injection layer, and an electrode layer. The light emitting structure may include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The carrier injection layer may be positioned over the light emitting structure, and the electrode layer may be positioned over the carrier injection layer. | 2010-09-30 |
20100244085 | LIGHT EMITTING DEVICE - A light emitting device including a light emitting chip and a magnetic material is provided. The light emitting chip includes a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting semiconductor layer disposed between the first doped semiconductor layer and the second doped semiconductor layer. The magnetic material is disposed beside the light emitting chip, wherein the magnetic material is not disposed on a conducting path of a current causing the light emitting chip to emit light. | 2010-09-30 |
20100244086 | METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR, METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - A method for manufacturing a Group III nitride semiconductor of the present invention, comprising a sputtering step for disposing a substrate and a target in a chamber and forming a Mg-doped Group III nitride semiconductor on the substrate by a reactive sputtering method, wherein the sputtering step includes respective substeps of: a film formation step for forming a semiconductor thin film while doping with Mg; and a plasma treatment step for applying an inert gas plasma treatment to the semiconductor thin film that has been formed in the film formation step, and the Group III nitride semiconductor is formed by laminating the semiconductor thin film through alternate repetitions of the film formation step and the plasma treatment step. | 2010-09-30 |
20100244087 | NITRIDE SEMICONDUCTOR, NITRIDE SEMICONDUCTOR CRYSTAL GROWTH METHOD, AND NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - During the growth of a nitride semiconductor crystal on a nonpolar face nitride substrate, such as an m-face, the gas that constitutes the main flow in the process of heating up to a relatively high temperature range, before growth of the nitride semiconductor layer, (the atmosphere to which the main nitride face of the substrate is exposed) and the gas that constitutes the main flow until growth of first and second nitride semiconductor layers is completed (the atmosphere to which the main nitride face of the substrate is exposed) are primarily those that will not have an etching effect on the nitride, while no Si source is supplied at the beginning of growth of the nitride semiconductor layer. Therefore, nitrogen atoms are not desorbed from near the nitride surface of the epitaxial substrate, thus suppressing the introduction of defects into the epitaxial film. This also makes epitaxial growth possible with a surface morphology of excellent flatness. | 2010-09-30 |
20100244088 | ZENER TRIGGERED ESD PROTECTION - Electrostatic discharge (ESD) protection clamps ( | 2010-09-30 |
20100244089 | LATERAL SCHOTTKY DIODE - High-side and low-side surface voltage sustaining regions is produced by utilizing optimum surface variation lateral doping. Schottky junctions are formed by depositing metal M on an n-type region having the lowest potential, taking M as the anode A | 2010-09-30 |
20100244090 | TVS with low capacitance & Forward voltage drop with depleted SCR as steering diode - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage. | 2010-09-30 |
20100244091 | INSULATED GATE BIPOLAR TRANSISTOR - In some embodiments, an insulated gate bipolar transistor includes a drift layer, insulation gates formed at a principle surface portion of the drift layer, base regions formed in a between-gate region, an emitter region formed in the base region so as to be adjacent to the insulation gate, an emitter electrode connected to the emitter region, a collector layer formed at the other side of the principle surface portion of the drift layer, and a collector electrode connected to the collector layer. The conductive type base regions are separated with each other by the drift layers, and the drift layer and the emitter electrode are insulated by an interlayer insulation film. | 2010-09-30 |
20100244092 | POWER SEMICONDUCTOR APPARATUS - A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted. | 2010-09-30 |
20100244093 | SEMICONDUCTOR MODULE - A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer. | 2010-09-30 |
20100244094 | DUAL TRIGGERED SILICON CONTROLLED RECTIFIER - A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; a well region, a first N+ diffusion region, a first P+ diffusion region, a second N+ diffusion region, a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the well region and semiconductor substrate; a third N+ diffusion region, positioned in another side of the DTSCR and across the well region and the semiconductor substrate; a first gate, positioned above the semiconductor substrate between the first P+ diffusion region and the third P+ diffusion region, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the well region between the second N+ diffusion region and the third N+ diffusion region, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage. | 2010-09-30 |
20100244095 | DUAL TRIGGERED SILICON CONTROLLED RECTIFIER - A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage. | 2010-09-30 |
20100244096 | SEMICONDUCTOR DEVICE - A device includes a substrate; a buffer layer; and a device formation layer, wherein the buffer layer is formed by sequentially stacking, a plurality of times, a first nitride-based semiconductor layer made of a material having a lattice constant lower than a lattice constant of a material of the substrate; a first composition graded layer made of a material having a lattice constant gradually higher than the lattice constant of the first nitride-based semiconductor layer in a thickness direction; a second nitride-based semiconductor layer made of a material having a lattice constant higher than the lattice constant of the first nitride-based semiconductor layer; and a second composition graded layer made of a material having a lattice constant gradually lower than the lattice constant of the second nitride-based semiconductor layer in the thickness direction, and the second composition graded layer is thicker than the first composition graded layer. | 2010-09-30 |
20100244097 | FIELD EFFECT TRANSISTOR - Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode | 2010-09-30 |
20100244098 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer made of Fe-doped GaN; a first buffer layer that is provided on the semiconductor layer so as to contact an upper surface of the semiconductor layer and is made of AlN or Al | 2010-09-30 |
20100244099 | Double heterojunction bipolar transistor having graded base region - A semiconductor device comprises: a heterojunction, comprises a first region comprising a first III-V semiconductor; a second region adjacent to the first region and comprising a second III-V semiconductor material, wherein the second III-V semiconductor material comprises a material of graded concentration over a width of the second region; and a third region adjacent to the second region and comprising a third III-V semiconductor material, wherein the graded concentration is selection to provide substantially no conduction band discontinuity at a junction of the second region and the third region, or to provide a type I semiconductor junction at the junction of the second region and the third region. | 2010-09-30 |
20100244100 | Compound semiconductor substrate - The present invention provides a compound semiconductor substrate, including: a single-crystal silicon substrate having a crystal face with (111) orientation; a first buffer layer which is formed on the single-crystal silicon substrate and is constituted of an Al | 2010-09-30 |
20100244101 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a method for fabricating a semiconductor device capable of setting carbon concentration within crystal to a desirable value while improving electron mobility. The carbon concentration within a buffer layer is controlled by introducing material gas of hydrocarbon or organic compounds containing carbon such as propane as a dopant in forming the buffer layer by introducing trimethylgallium (TMGa) and ammonium (NH | 2010-09-30 |
20100244102 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME - In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer. A wiring structure is determined based on a wiring structure equation expressing the relations among a voltage drop in the lines, the area occupied thereby, and a current consumed thereby and on a circuit characteristic equation expressing, when the circuit is subdivided while the ratio between the area of the circuit and a current consumed thereby is held constant, the relation between an area occupied by a circuit resulting from subdivision and a current consumed thereby. | 2010-09-30 |
20100244103 | STRUCTURE AND METHOD OF FABRICATING FINFET - A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing. | 2010-09-30 |
20100244104 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated structure; a first protective film formed over the compound semiconductor laminated structure between the source electrode and the gate electrode and including silicon; and a second protective film formed over the compound semiconductor laminated structure between the drain electrode and the gate electrode and including more silicon than the first protective film. | 2010-09-30 |
20100244105 | TRANSISTORS HAVING TEMPERATURE STABLE SCHOTTKY CONTACT METALS - A semiconductor structure having: a semiconductor comprising a indium gallium phosphide and molybdenum metal in Schottky contact with the semiconductor. | 2010-09-30 |
20100244106 | Fabrication and structure of asymmetric field-effect transistors using L-shaped spacers - Fabrication of an asymmetric field-effect transistor ( | 2010-09-30 |
20100244107 | REDUCING SILICIDE RESISTANCE IN SILICON/GERMANIUM-CONTAINING DRAIN/SOURCE REGIONS OF TRANSISTORS - In sophisticated P-channel transistors, a high germanium concentration may be used in a silicon/germanium alloy, wherein an additional semiconductor cap layer may provide enhanced process conditions during the formation of a metal silicide. For example, a silicon layer may be formed on the silicon/germanium alloy, possibly including a further strain-inducing atomic species other than germanium, in order to provide a high strain component while also providing superior conditions during the silicidation process. | 2010-09-30 |
20100244108 | CMOS IMAGE SENSOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND PROCESS FOR MAKING SAME - Methods and apparatus for producing a CMOS image sensor result in: a glass or glass ceramic substrate having first and second spaced-apart surfaces; a semiconductor layer disposed on the first surface of the glass or glass ceramic substrate; and a plurality of pixel structures formed in the semiconductor layer, each pixel structure including: at least first, second, and third semiconductor islands, each island operating as a color sensitive photo-detector and each being of a different thickness such that each is sensitive to a respective range of light wavelengths, and a fourth semiconductor island on which at least one transistor is disposed, the at least one transistor operating to at least one of buffer, select, and reset one or more of the photo-detectors. | 2010-09-30 |
20100244109 | TRENCHED METAL-OXIDE-SEMICONDUCTOR DEVICE AND FABRICATION THEREOF - A fabrication method of a trenched metal-oxide-semiconductor device is provided. After the formation of the gate dielectric layer, a first poly-silicon layer is deposited along the profile of the gate trench. Then, impurities of first conductivity type are implanted to the first poly-silicon layer at the bottom of the gate trench. Then, a second poly-silicon layer with second conductivity type is deposited over the first poly-silicon layer. The impurities in the first poly-silicon layer and the second poly-silicon layer are then driven by an annealing step to form a first doping region with first conductivity type located at the bottom of the gate trench and a second doping region with second conductivity type. | 2010-09-30 |
20100244110 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region. | 2010-09-30 |
20100244111 | Semiconductor Structure of a Display Device and Method for Fabricating the Same - A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode. | 2010-09-30 |
20100244112 | INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT - Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices. | 2010-09-30 |
20100244113 | MOS VARACTOR AND FABRICATING METHOD OF THE SAME - The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor. The MOS varactor include: island-like gate insulating layers which are arranged at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one), and a gate electrode of a first height (t1) placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire of a second height (t2) (where, t12010-09-30 | |
20100244114 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes: at least one first interconnection extending in a first direction; at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction; a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element; and an element isolation layer disposed between the memory cells. At least one dielectric film with a higher density than the element isolation layer is disposed on a sidewall surface of the memory cell. | 2010-09-30 |
20100244115 | ANTI-FUSE MEMORY CELL - An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor. | 2010-09-30 |
20100244116 | METHOD OF FORMING AN EEPROM DEVICE AND STRUCTURE THEREFOR - In one embodiment, an EEPROM device is formed to include a metal layer having an opening therethrough. The opening overlies a portion of a floating gate of the EEPROM device. | 2010-09-30 |
20100244117 | NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS - An array of memory cells configured to store at least one bit per one F | 2010-09-30 |
20100244118 | Nonvolatile Memory Device and Method of Manufacturing the Same - A nonvolatile memory device comprises floating gates formed over an active region of a semiconductor substrate, isolation layers formed within respective isolation regions of the semiconductor substrate, first nitridation patterns formed on sidewalls of the floating gates, a first insulating layer, a second nitride layer, a second insulating layer, and a third nitride layer formed on an entire surface of the first nitridation patterns and the isolation layers, and control gates formed over the third nitride layer. | 2010-09-30 |
20100244119 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit. | 2010-09-30 |
20100244120 | NONVOLATILE SPLIT GATE MEMORY CELL HAVING OXIDE GROWTH - A split gate nonvolatile memory cell on a semiconductor layer is made by forming a gate dielectric over the semiconductor layer. A first layer of gate material is deposited over the gate dielectric. The first layer of gate material is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion having a sidewall adjacent to the first portion. A treatment is applied over the semiconductor layer to reduce a relative oxide growth rate of the sidewall to the first portion. Oxide is grown on the sidewall to form a first oxide on the sidewall and on the first portion to form a second oxide on the first portion after the applying the treatment. A charge storage layer is formed over the first oxide and along the second oxide. A control gate is formed over the second oxide and adjacent to the sidewall. | 2010-09-30 |
20100244121 | STRESSED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING - A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate. | 2010-09-30 |
20100244122 | MEMORY UTILIZING OXIDE NANOLAMINATES - Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers. | 2010-09-30 |
20100244123 | FIELD-EFFECT TRANSISTOR WITH SELF-LIMITED CURRENT - A field-effect transistor is integrated in a chip of semiconductor material of a first type of conductivity, which has a first main surface and a second main surface, opposite to each other. The transistor includes a plurality of body regions of a second type of conductivity, each one extending from the second main surface in the chip. A plurality of drain columns of the second type of conductivity are provided, each one extending from a body region towards the first main surface, at a pre-defined distance from the first main surface. A plurality of drain columns are defined in the chip, each one extending longitudinally between a pair of adjacent drain columns. The transistor includes a plurality of source regions of the first type of conductivity, each one of them extending from the second main surface in a body region; a plurality of channel areas are defined, each one in a body region between a source region of the body region and each drain channel adjacent to the body region. There are then provided a gate terminal extending over the cannel areas (with the gate terminal that is insulated from the second main surface), a source terminal contacting the source regions on the second main surface, and a drain terminal contacting the chip on the first main surface. In the transistor according to an embodiment of the invention, each drain channel includes a first residual portion having a first transversal width and a second prevalent portion having a second transversal width higher than the first transversal width. | 2010-09-30 |
20100244124 | SEMICONDUCTOR DEVICES HAVING A VERTICAL CHANNEL TRANSISTOR - Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction. | 2010-09-30 |
20100244125 | POWER SEMICONDUCTOR DEVICE STRUCTURE FOR INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF - A power semiconductor device comprises a conductive gate, provided in an upper part of a trench ( | 2010-09-30 |
20100244126 | Structure and Method for Forming a Salicide on the Gate Electrode of a Trench-Gate FET - A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches. | 2010-09-30 |
20100244127 | BANDGAP ENGINEERED MOS-GATED POWER TRANSISTORS - Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate. | 2010-09-30 |
20100244128 | Configuration and fabrication of semiconductor structure using empty and filled wells - A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs ( | 2010-09-30 |
20100244129 | Semiconductor device and method of manufacturing semiconductor device - Second-conductivity-type high dose impurity layers are formed in a device forming region, and function as the source and drain; a second-conductivity-type low dose impurity layer is provided around each of the second-conductivity-type high dose impurity layers so as to expand each second-conductivity-type high dose impurity layer in the depth-wise direction and in the direction of channel length, at least a part of the second-conductivity-type low dose impurity layer is positioned below the gate electrode, and the gate insulting film; and the gate insulating film has, at a portion thereof positioned above the second-conductivity-type low dose impurity layer, a sloped portion which continuously increases in the thickness from the center towards a side face of the gate electrode, without causing an inflection point. | 2010-09-30 |
20100244130 | Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket - Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET ( | 2010-09-30 |
20100244131 | Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions - An asymmetric insulated-gate field-effect transistor ( | 2010-09-30 |
20100244132 | Methods for Normalizing Strain in Semiconductor Devices and Strain Normalized Semiconductor Devices - A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor. | 2010-09-30 |
20100244133 | Printed Dopant Layers - A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands. | 2010-09-30 |
20100244134 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an insulating layer; a semiconductor layer formed on the insulating layer; a first partially depleted transistor formed in the semiconductor layer; and a first diode formed in the semiconductor layer, wherein the first transistor has a first gate electrode formed above the semiconductor layer via an insulating film and a first source or a first drain of a first conductivity type formed in the semiconductor layer below both sides of the gate electrode, the first diode has a first impurity layer of a second conductivity type formed in a shallow portion of the semiconductor layer and a second impurity layer of the first conductivity type formed in a deep portion of the semiconductor layer, the first impurity layer and the second impurity layer are stacked in a depth direction of the semiconductor layer, and a side surface of the first impurity layer and a side surface of the second impurity layer are in contact with the semiconductor layer in a region just below the first gate electrode. | 2010-09-30 |
20100244135 | Semiconductor device - In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region. | 2010-09-30 |
20100244136 | SEMICONDUCTOR DEVICE, SINGLE-CRYSTAL SEMICONDUCTOR THIN FILM-INCLUDING SUBSTRATE, AND PRODUCTION METHODS THEREOF - The present invention provides a semiconductor device, a single-crystal semiconductor thin film-including substrate, and production methods thereof, each allowing single-crystal semiconductor thin film-including single-crystal semiconductor elements produced by being transferred onto a low heat resistant insulating substrate to have enhanced transistor characteristics and a reduced wiring resistance. | 2010-09-30 |
20100244137 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced. | 2010-09-30 |
20100244138 | SEMICONDUCTOR VARACTOR WITH REDUCED PARASITIC RESISTANCE - A semiconductor varactor with reduced parasitic resistance is disclosed. A contact isolation structure ( | 2010-09-30 |
20100244139 | STRAINED-SILICON CMOS DEVICE AND METHOD - The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension. | 2010-09-30 |
20100244140 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer. | 2010-09-30 |
20100244141 | THRESHOLD ADJUSTMENT OF TRANSISTORS INCLUDING HIGH-K METAL GATE ELECTRODE STRUCTURES COMPRISING AN INTERMEDIATE ETCH STOP LAYER - During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence. | 2010-09-30 |
20100244142 | SEMICONDUCTOR DEVICE - A semiconductor device in a continuous diffusion region formed on a semiconductor substrate and having either a P-type or N-type polarity includes: a first transistor formed within the continuous diffusion region; a second transistor formed within the continuous diffusion region and in an area that is different from an area where the first transistor is formed; a third transistor formed within the continuous diffusion region and in an area between the first and second transistors, and having a gate electrode to which a fixed potential is applied; and a fourth transistor formed within the continuous diffusion region and in an area between the second and third transistors, and having a gate electrode to which a fixed potential is applied. | 2010-09-30 |
20100244143 | Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length - A semiconductor structure contains a bipolar transistor ( | 2010-09-30 |
20100244144 | ELECTRICAL FUSE AND RELATED APPLICATIONS - In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology. | 2010-09-30 |
20100244145 | Semiconductor memory device using hot electron injection - A semiconductor memory device has a low-resistivity semiconductor substrate on which a higher-resistivity semiconductor layer of the same conductivity type is formed. Memory cell transistors are formed in the semiconductor layer. A diffusion region, also of the same conductivity type, is formed below the memory cell transistors. The resistivity of the diffusion region is lower than the resistivity of the semiconductor layer. In the programming of data into the memory cell transistors by hot electron injection, the diffusion region reduces the voltage drop due to current flow from the part of the semiconductor layer near the memory cell transistors into the semiconductor substrate, thereby reducing unwanted elevation of the potential of the semiconductor layer. | 2010-09-30 |
20100244146 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device capable of reducing a difference in wiring resistance between paths from a gate pad to a gate electrode and capable of applying a gate voltage to the gate electrode more uniformly, and a method of manufacturing the semiconductor device. The semiconductor device according to an exemplary aspect of the present invention includes a gate pad supplied with a gate voltage applied to a gate electrode of each MOSFET cell disposed in an active region, a gate connection line connected to the gate pad, and a plurality of gate lead-out lines connected in parallel between the gate electrode and the gate connection line. Each of the plurality of gate lead-out lines has a resistance value that becomes smaller by every one or plural gate lead-out lines as the gate lead-out lines are located farther away from the gate pad. | 2010-09-30 |
20100244147 | Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone - An asymmetric insulated-gate field effect transistor ( | 2010-09-30 |