39th week of 2008 patent applcation highlights part 43 |
Patent application number | Title | Published |
20080233679 | Semiconductor package with plated connection - A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material. | 2008-09-25 |
20080233680 | Semiconductor Die Collet and Method - Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface. The collet is configured for holding a die surface against the bearing surface and for simultaneously pushing outward on the center region of the die so held. | 2008-09-25 |
20080233681 | Design of BEOL Patterns to Reduce the Stresses on Structures Below Chip Bondpads - A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure. | 2008-09-25 |
20080233682 | METHODS OF FORMING A CORED METALLIC THERMAL INTERFACE MATERIAL AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a core portion of a TIM, wherein the core portion comprises a high thermal conductivity and does not comprise indium, and forming an outer portion of the TIM on the core portion. | 2008-09-25 |
20080233683 | PRE-PLATED LEADFRAME HAVING ENHANCED ENCAPSULATION ADHESION - A process for producing a pre-plated leadframe that has enhanced adhesion by molding compound is provided, wherein a base leadframe material is first plated with multiple layers of metallic material. Thereafter, the plated base leadframe material is covered with a mask, so as to expose selected surfaces thereof at unmasked areas where enhanced adhesion of molding compound is desired. The said unmasked areas are plated with a layer of copper before removing the mask. Optionally, the layer of copper may further be oxidized to form a layer of specially controlled copper oxide. | 2008-09-25 |
20080233684 | MICROELECTRONIC COMPONENT ASSEMBLIES EMPLOYING LEAD FRAMES HAVING REDUCED-THICKNESS INNER LENGTHS - The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals of the microelectronic component and a body having an outer surface spaced farther from the microelectronic component than a bond surface of the inner length. Each of the bond wires couples the microelectronic component to one of the leads and has a maximum height outwardly from the microelectronic component that is no greater than the height of the outer surface of the lead. | 2008-09-25 |
20080233685 | METHOD OF MANUFACTURE OF AN APPARATUS FOR INCREASING STABILITY OF MOS MEMORY CELLS - In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method of manufacture of a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices. | 2008-09-25 |
20080233686 | ESD PROTECTION FOR HIGH VOLTAGE APPLICATIONS - An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device. | 2008-09-25 |
20080233687 | ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION - A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate. | 2008-09-25 |
20080233688 | Method of Fabricating a Bipolar Transistor - A method of fabricating a bipolar transistor in a first trench ( | 2008-09-25 |
20080233689 | Method for manufacturing semiconductor device - The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed. | 2008-09-25 |
20080233690 | Method of Selectively Forming a Silicon Nitride Layer - A method for selectively forming a dielectric layer. An embodiment comprises forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby converting the silicon layer into a silicon nitride layer. This method allows for a protective silicon nitride layer to be formed, while also preventing and/or reducing the nitrogen itself from penetrating far enough to contaminate the substrate. In another embodiment the treating with nitrogen is continued to form not only a silicon nitride, but to also diffuse a small portion of nitrogen into the dielectric layer to nitridized a portion of the dielectric layer. Optionally, an anneal could be performed to repair any damage that has been done by the treatment process. | 2008-09-25 |
20080233691 | METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer. | 2008-09-25 |
20080233692 | Method and System for Forming a Controllable Gate Oxide - Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms. | 2008-09-25 |
20080233693 | COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) DEVICES INCLUDING A THIN-BODY CHANNEL AND DUAL GATE DIELECTRIC LAYERS AND METHODS OF MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer. | 2008-09-25 |
20080233694 | Transistor Device and Method of Manufacture Thereof - A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided. | 2008-09-25 |
20080233695 | Integration method of inversion oxide (TOXinv) thickness reduction in CMOS flow without added pattern - A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VT | 2008-09-25 |
20080233696 | Semiconductor device and method for fabricating the same - Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset. | 2008-09-25 |
20080233697 | Multiple-gate MOSFET device and associated manufacturing methods - One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed. | 2008-09-25 |
20080233698 | Semiconductor device and method of manufacturing the same - A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the semiconductor substrate and an insulator provided in the trench, a part of the isolation region in the trench around the MOSFET having a bottom deeper than other part of the isolation region. | 2008-09-25 |
20080233699 | BULK FinFET DEVICE - A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate. | 2008-09-25 |
20080233700 | Methods of forming integrated circuitry - The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems. | 2008-09-25 |
20080233701 | Methods of Forming Integrated Circuit Devices Including a Depletion Barrier Layer at Source/Drain Regions - Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion of a lateral face of the channel region. A source/drain layer is disposed on the depletion barrier layer and electrically contacting the lateral face of the channel region in a region not covered by the depletion barrier layer. The channel region may protrude from a surface of the substrate. The depletion barrier layer may be an L-shaped depletion barrier layer and the device may further include a device isolation layer disposed at a predetermined portion of the substrate through the source/drain layer and the depletion barrier layer. The depletion barrier layer and the device isolation layer may be formed of the same material. | 2008-09-25 |
20080233702 | Method of forming a recess in a semiconductor structure - One embodiment of the present invention relates to a method of processing a semiconductor device. During the method an amorphization implant is performed to amorphize a selected region of a semiconductor structure. The amorphized selected region is then removed by performing a recess etch that is selective thereto. Other methods and systems are also disclosed. | 2008-09-25 |
20080233703 | POLYSILICON CONDUCTIVITY IMPROVEMENT IN A SALICIDE PROCESS TECHNOLOGY - An electronic device and method for forming same. The electronic device includes a source and drain region. Each region has an uppermost portion comprised of a first silicide where the first silicide is overlaid with a first dielectric layer. The electronic device further includes a gate region having an uppermost portion comprised of a second silicide. The second silicide is both thicker than the first silicide and has a lower resistivity than the first silicide with at least a portion of the second silicide being formed in an opening in the first dielectric layer. | 2008-09-25 |
20080233704 | Integrated Resistor Capacitor Structure - A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers. | 2008-09-25 |
20080233705 | METHOD FOR SELECTIVELY FORMING ELECTRIC CONDUCTOR AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess. | 2008-09-25 |
20080233706 | MANUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY - A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench. | 2008-09-25 |
20080233707 | Semiconductor device comprising capacitor and method of fabricating the same - A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance. | 2008-09-25 |
20080233708 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a semiconductor substrate; forming a first groove penetrating the first semiconductor layer and the second semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; forming a support covering the second semiconductor layer from inside of the first groove to a surface of the second semiconductor layer so as to support the second semiconductor layer; etching a sidewall formed in the first groove of the support so as to render the sidewall thin; forming a second groove exposing the first semiconductor layer by sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer; forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the second groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; and forming a buried oxide film by thermally oxidizing an upper surface of the semiconductor substrate and a lower surface of the second semiconductor layer that are facing inside of the cavity. | 2008-09-25 |
20080233709 | METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR - A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material. | 2008-09-25 |
20080233710 | METHODS FOR FORMING SINGLE DIES WITH MULTI-LAYER INTERCONNECT STRUCTURES AND STRUCTURES FORMED THEREFROM - A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device The at least one fist metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die. | 2008-09-25 |
20080233711 | MANUFACTURING METHOD FOR DEVICES - A manufacturing method for devices including a wafer supporting step of mounting an adhesive film to the lower surface of a wafer and attaching the wafer through the adhesive film to the upper surface of a dicing tape mounted on an annular frame, a laser processing step of applying a pulsed laser beam having an absorption wavelength to the wafer along separation lines formed on the upper surface of the wafer after mounting the adhesive film to the dicing tape, thereby separating the wafer into the individual devices and cutting the adhesive film, and a pickup step of expanding the dicing tape after performing the laser processing step to thereby increase the spacing between any adjacent ones of the individual devices, and peeling off to pick up each of the individual devices from the dicing tape in the condition where the adhesive film is mounted on the lower surface of each device. | 2008-09-25 |
20080233712 | METHOD OF MANUFACTURING DEVICE - A method of manufacturing a device includes the steps of forming dividing grooves with a predetermined depth along planned dividing lines of a wafer, then grinding the backside surface of the wafer to expose the dividing grooves on the back side and to divide the wafer into individual devices, mounting a UV-curing adhesive film to the backside surface of the wafer divided into the individual devices, adhering the adhesive film side of the wafer to a dicing tape attached to an annular frame, radiating UV rays from the face side of the wafer to cure the regions of the adhesive film which correspond to the dividing grooves, expanding the dicing tape to exert tensile forces on the adhesive film, so as to split the adhesive film into the individual devices, with the cured regions of the adhesive film as starting points of splitting, and releasing the device from the dicing tape and thereby picking up the device. | 2008-09-25 |
20080233713 | METHOD OF PROCESSING SILICON WAFER AND METHOD OF MANUFACTURING LIQUID EJECTING HEAD - A break pattern is formed on a silicon wafer using an anisotropic etching process. The break pattern includes a plurality of through holes, each of having a first plane perpendicular to a plane defined by the silicon wafer, a second plane opposite to the first plane, a third plane that is perpendicular to the plane of the silicon wafer and intersects the first plane at an acute angle, and a fourth plane that is opposite to the third plane, is perpendicular to the plane of the silicon wafer, and intersects the second plane at an acute angle. The anisotropic etching is performed using a mask pattern having a predetermined shape to form, around the break pattern, a thin portion that has a smaller thickness than other portions of the silicon wafer. The silicon wafer is then divided into a plurality of silicon substrates along the break pattern. | 2008-09-25 |
20080233714 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - An object of the present invention is to provide a method for fabricating a semiconductor device to fabricate a semiconductor device. To achieve such an object, the present invention relates to a method for fabricating a semiconductor device composed of a hetero-junction substrate formed of a semiconductor substrate, and a heterogeneous substrate made of a material other than semiconductor bonded to a surface of the semiconductor substrate. A dicing step of cutting the hetero-junction substrate into semiconductor chips comprises a first dicing step of forming grooves having a depth of at least the thickness of the semiconductor substrate on the surface of the semiconductor substrate; and a second dicing step of cutting the entire hetero-junction substrate along the grooves to divide the hetero-junction substrate into a plurality of semiconductor chips. | 2008-09-25 |
20080233715 | METHOD AND APPARATUS FOR THE LASER SCRIBING OF ULTRA LIGHTWEIGHT SEMICONDUCTOR DEVICES - A system for the laser scribing of semiconductor devices includes a laser light source operable to selectably deliver laser illumination at a first wavelength and at a second wavelength which is shorter than the first wavelength. The system further includes a support for a semiconductor device and an optical system which is operative to direct the laser illumination from the light source to the semiconductor device. The optical system includes optical elements which are compatible with the laser illumination of the first wavelength and the laser illumination of the second wavelength. In specific instances, the first wavelength is long wavelength illumination such as illumination of at least 1000 nanometers, and the second wavelength is short wavelength illumination which in specific instances is 300 nanometers or shorter. By the use of the differing wavelengths, specific layers of the semiconductor device may be scribed without damage to subjacent layers. Also disclosed are specific scribing processes. | 2008-09-25 |
20080233716 | Method for fabricating semiconductor device - The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer. | 2008-09-25 |
20080233717 | SOI WAFER AND MANUFACTURING METHOD THEREOF - An SOI wafer which does not generate slip dislocation even if laser annealing is performed for no more than 0.1 seconds at a maximum temperature of 1200° C. or more is provided. | 2008-09-25 |
20080233718 | Method of Semiconductor Thin Film Crystallization and Semiconductor Device Fabrication - A method of fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a patterned heat retaining layer over the amorphous silicon layer, doping the amorphous silicon layer to form a pair of doped regions in the amorphous silicon layer by using the patterned heat retaining layer as a mask, and irradiating the amorphous silicon layer to activate the pair of doped regions, forming a pair of activated regions, and form a crystallized region between the pair of activated regions. | 2008-09-25 |
20080233719 | Method for Manufacturing Crystalline Semiconductor Film and Method for Manufacturing Thin Film Transistor - The present invention relates to a method for manufacturing a polycrystalline semiconductor film that can be used for a semiconductor device. In the method, an amorphous semiconductor film is irradiated with a femtosecond laser to be crystallized. By laser irradiation using a femtosecond laser, when an amorphous semiconductor film over which a cap film is formed is crystallized with a laser, it becomes possible to perform crystallization of the semiconductor film and removal of the cap film at the same time. Therefore, a step of removing the cap film in a later step can be omitted. | 2008-09-25 |
20080233720 | Method of Making a Solar Grade Silicon Wafer - A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing a solar grade wafer mold defining an interior for receiving the slurry; introducing the slurry into the solar grade wafer mold; precipitating the silicon powder from the slurry to form a preform of the solar grade silicon wafer; and crystallizing the preform to make the solar grade silicon wafer. | 2008-09-25 |
20080233721 | METHOD FOR FORMING AlGaN CRYSTAL LAYER - There is provided a method for preparing an AlGaN crystal layer having an excellent surface flatness. A buffer layer effective in stress relaxation is formed on a template substrate having a surface layer that is flat at a substantially atomic level and to which in-plane compressive stress is applied, and an AlGaN layer is formed on the buffer layer, so that an AlGaN layer can be formed that is flat at a substantially atomic level. Particularly when the surface layer of the template substrate includes a first AlN layer, a second AlN layer may be formed thereon at a temperature of 600° C. or lower, while a mixed gas of TMA and TMG is supplied in a TMG/TMA mixing ratio of 3/17 or more to 6/17 or less, so that a buffer layer effective in stress relaxation the can be formed in a preferred manner. | 2008-09-25 |
20080233722 | METHOD OF FORMING SELECTIVE AREA COMPOUND SEMICONDUCTOR EPITAXIAL LAYER - A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate. | 2008-09-25 |
20080233723 | PLASMA DOPING METHOD AND APPARATUS - There are provided a plasma doping method and an apparatus which have excellent reproducibility of the concentration of impurities implanted into the surfaces of samples. In a vacuum container, in a state where gas is ejected toward a substrate placed on a sample electrode through gas ejection holes provided in a counter electrode, gas is exhausted from the vacuum container through a turbo molecular pump as an exhaust device, and the inside of the vacuum container is maintained at a predetermined pressure through a pressure adjustment valve, the distance between the counter electrode and the sample electrode is set to be sufficiently small with respect to the area of the counter electrode to prevent plasma from being diffused outward, and capacitive-coupled plasma is generated between the counter electrode and the sample electrode to perform plasma doping. The gas used herein is a gas with a low concentration which contains impurities such as diborane or phosphine. | 2008-09-25 |
20080233724 | RECYCLING OF ELECTROCHEMICAL-MECHANICAL PLANARIZATION (ECMP) SLURRIES/ELECTROLYTES - A method, process and system for the recycling of electrochemical-mechanical planarization slurries/electrolytes as they are used in the back end of line of the semiconductor wafer manufacturing process is disclosed. The method, process and system includes with the removal of metal ions from slurries using ion exchange media and/or electrochemical deposition. | 2008-09-25 |
20080233725 | Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures - Semiconductor material strips are secured to substrates in such a way as to stress the semiconductor material. The strips of semiconductor material may be compressively stressed, subjected to tensile stress, or some strips may be compressively stressed while other strips are tensilely stressed. Stress may be induced by forming non-planarities on the surface of the substrate to which the strips are to be secured. The non-planarities may be configured to stress strips of semiconductor material as the strips are secured thereover and over an intervening surface of the substrate, or to stress strips as the non-planarities are removed from beneath the strips. The strain that ultimately results from stressing the strips improves carrier mobility (i.e., electron mobility, electron hole pair, or “hole,” mobility) relative to the carrier mobilities of unstrained semiconductor materials. The strained strips of semiconductor material may be used in the fabrication of semiconductor device structures such as transistors. | 2008-09-25 |
20080233726 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device includes forming a gate conductive layer, a first mask layer, a second mask layer, and a third mask layer over a semiconductor substrate that includes a cell region and a peripheral region. The method also includes forming a second mask pattern and a third mask pattern using a gate mask. The method further includes trimming the second mask pattern in the peripheral region to form a fourth mask pattern having a size smaller than that of the second mask pattern. Still further, the method includes removing the third mask pattern, and patterning the first mask layer and the gate conductive layer using the fourth mask pattern as a mask. | 2008-09-25 |
20080233727 | Method of manufacturing semiconductor device - Disclosed is a method for manufacturing a semiconductor device. More specifically, in the invention, a gate pattern is formed and then an interlayer insulating pattern burying the space between the gate patterns is formed to ensure the region into which a landing plug contact hole has to be opened, thereby avoiding a problem in that the landing plug contact hole is not opened when forming the landing plug contact hole in a subsequent process. As a result, a failure that may occur in a subsequent test process can be avoided and further a current drivability of a gate, a tWR feature and a timing margin are ensured and thereby improve the device features. | 2008-09-25 |
20080233728 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability. | 2008-09-25 |
20080233729 | METHOD OF FORMING MICRO PATTERN IN SEMICONDUCTOR DEVICE - A method of forming a fine pattern in a semiconductor device includes forming an target layer, a hard mask layer and first sacrificial patterns on a semiconductor substrate; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; performing the first etch process so as to allow the second sacrificial layer remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns; etch the hard mask layer through the second etch process utilizing the first and second sacrificial patterns as the etch mask to form a mask pattern; and etch the target layer through the third etch process utilizing the hard mask pattern as the etch mask. | 2008-09-25 |
20080233730 | Method for fabricating semiconductor device - A method for fabricating a semiconductor device includes providing a substrate where a cell region and a peripheral region are defined, stacking a conductive layer, a hard mask layer, a metal-based hard mask layer, and an amorphous carbon (C) pattern over the substrate etching the metal-based hard mask layer using the amorphous C pattern as an etch mask, thereby forming a resultant structure, forming a photoresist pattern covering the resultant structure in the cell region while exposing the resultant structure in the peripheral region, decreasing a width of the etched metal-based hard mask layer in the peripheral region, removing the photoresist pattern and the amorphous C pattern, and forming a conductive pattern by etching the hard mask layer and the conductive layer using the etched metal-based hard mask layer as an etch mask. | 2008-09-25 |
20080233731 | Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. | 2008-09-25 |
20080233732 | METHOD OF PLACING WIRES - A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division boundary, confirming whether the shield subject wire exists around the division boundary in the second area when the division boundary is not laid on top of the wire track, and determining whether to place the shield wire on a wire track being adjacent to division boundary in the first area based on the confirming. | 2008-09-25 |
20080233733 | METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT - A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure. | 2008-09-25 |
20080233734 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect. | 2008-09-25 |
20080233735 | Etching method for semiconductor element - An etching method for semiconductor element is provided. The etching method includes the following procedure. First, a to-be-etched substrate is provided. Then, a silicon-rich silicon oxide (SRO) layer is formed on the to-be-etched substrate. Afterwards, an anti-reflective layer is formed on the SRO layer. Then, a patterned photo resist layer is formed on the anti-reflective layer. Afterwards, the anti-reflective layer, the SRO layer and the to-be-etched substrate is etched so as to form an opening. | 2008-09-25 |
20080233736 | PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer. | 2008-09-25 |
20080233737 | METHOD OF FABRICATING INTERGRATED CIRCUIT CHIP - A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A number of circuit units are then formed in the internal region on the substrate. Thereafter, a dielectric layer is formed over the substrate, interconnects are formed in the dielectric layer within the internal region, and a number of bonding pad structures are formed in the dielectric layer within the external region. Finally, a cutting process is performed along a number of scribed lines on the substrate to form a number of chips. The bonding pad structures are exposed at the sides of each chip. | 2008-09-25 |
20080233738 | METHODS FOR FABRICATING AN INTEGRATED CIRCUIT - A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points. | 2008-09-25 |
20080233739 | METHOD FOR FABRICATING CONDUCTIVE LAYER - A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process. | 2008-09-25 |
20080233740 | Method for Producing Electrically Conductive Bushings Through Non-Conductive or Semiconductive Substrates - The present invention relates to a method for producing electrical bushings through non-conductive or semiconductive substrates, which are particularly suitable for electrical applications. The method is characterized in that a semiconductor substrate or a non-conductive substrate ( | 2008-09-25 |
20080233741 | Bulk-Isolated PN Diode and Method of Forming a Bulk-Isolated PN Diode - A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in the dielectric material exposing the doped region, and forming respective first and second polysilicon plugs within the first and second holes over the doped region. In one embodiment, the first and second polysilicon plugs are doped opposite one another such that a PN junction is formed between the first or second polysilicon plug and the doped region of the substrate, and has a cross-sectional area generally defined by the first or second hole adjacent the PN junction. Various devices, systems, and other methods are also disclosed. | 2008-09-25 |
20080233742 | METHOD OF DEPOSITING ALUMINUM LAYER AND METHOD OF FORMING CONTACT OF SEMICONDUCTOR DEVICE USING THE SAME - A contact hole is formed in an interlayer insulating layer disposed on a semiconductor substrate. The semiconductor substrate is loaded into a reaction chamber. A reaction gas including an aluminum precursor is injected into the reaction chamber. Reaction energy is supplied to the reaction chamber so as to allow thermal decomposition of the aluminum precursor. The injecting of the reaction gas and the supplying of the reaction energy are periodically repeated to deposit a first aluminum layer on the semiconductor substrate. A second aluminum layer is deposited to fill the contact hole. | 2008-09-25 |
20080233743 | Method and Structure for Self-Aligned Device Contacts - Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole. | 2008-09-25 |
20080233744 | CARBON NANOTUBE SWITCHES FOR MEMORY, RF COMMUNICATIONS AND SENSING APPLICATIONS, AND METHODS OF MAKING THE SAME - Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to electrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers. | 2008-09-25 |
20080233745 | Interconnect Structures for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 2008-09-25 |
20080233746 | METHOD FOR MANUFACTURING MOS TRANSISTORS UTILIZING A HYBRID HARD MASK - A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess. | 2008-09-25 |
20080233747 | Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process - In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch. | 2008-09-25 |
20080233748 | ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion. | 2008-09-25 |
20080233749 | METHODS AND APPARATUSES FOR REMOVING POLYSILICON FROM SEMICONDUCTOR WORKPIECES - Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other. | 2008-09-25 |
20080233750 | Method for forming fine patterns in semiconductor device - A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns. | 2008-09-25 |
20080233751 | IC CHIP UNIFORM DELAYERING METHODS - Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles. | 2008-09-25 |
20080233752 | METHOD FOR MANUFACTURING FLOATING STRUCTURE OF MICROELECTROMECHANICAL SYSTEM - Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate. | 2008-09-25 |
20080233753 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MANUFACTURING EQUIPMENT - A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing. | 2008-09-25 |
20080233754 | SUBSTRATE PERIPHERAL FILM-REMOVING APPARATUS AND SUBSTRATE PERIPHERAL FILM-REMOVING METHOD - A substrate peripheral film-removing apparatus which is capable of removing a film from a substrate periphery without complicating the construction of the apparatus. A wafer chamber receives a wafer having an SiO | 2008-09-25 |
20080233755 | Method of Removing Metallic, Inorganic and Organic Contaminants from Chip Passivation Layer Surfaces - A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO | 2008-09-25 |
20080233756 | Particle-removing apparatus for a semiconductor device manufacturing apparatus and method of removing particles - In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate. | 2008-09-25 |
20080233757 | PLASMA PROCESSING METHOD - A plasma processing method for processing a target substrate uses a plasma processing apparatus which includes a vacuum evacuable processing vessel for accommodating the target substrate therein, a first electrode disposed in the processing vessel and connected to a first RF power supply for plasma generation and a second electrode disposed to face the first electrode. The method includes exciting a processing gas containing fluorocarbon in the processing vessel to generate a plasma while applying a negative DC voltage having an absolute value ranging from about 100 V to 1500 V or an RF power of a frequency lower than about 4 MHz to the second electrode. The target layer is etched by the plasma, thus forming recesses on the etching target layer based on the pattern of the resist layer. | 2008-09-25 |
20080233758 | METHOD FOR FORMING TRENCH AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for forming a trench includes providing a substrate, and forming the trench in the substrate using a gas containing chlorine (Cl | 2008-09-25 |
20080233759 | HIGH SELECTIVITY BPSG TO TEOS ETCHANT - Methods of selectively etching BPSG over TEOS are disclosed. In one embodiment, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. An etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etchant may be utilized to etch the TEOS layer. The second etchant may be less aggressive and, thus, not damage the components underlying the TEOS layer. | 2008-09-25 |
20080233760 | Process for the Treatment of Substrate Surfaces - The present invention relates in general terms to the treatment or processing of substrate surfaces. In particular, the invention relates to processes for modifying the surface of silicon wafers. | 2008-09-25 |
20080233761 | Fabrication method of semiconductor integrated circuit device - An object of the present invention is to provide a fabrication method of a semiconductor integrated circuit device capable of improving the throughput, reducing the cost of a cleaning gas and prolonging the life of a process kit by automatically detecting the end point of cleaning in a chamber. A cleaning gas converted into plasma in a plasma gas generator is introduced into a chamber to remove an unnecessary film deposited over the interior wall of the chamber or electrode. By an RF power source adjusted to low output from the film formation time, a high frequency voltage is applied to a lower electrode and an upper electrode. This voltage is detected by an RF sensor and amplified by an electronic module. The voltage thus amplified by the electronic module is input to a termination controller. The termination controller automatically judges the termination of cleaning when the voltage thus input becomes substantially constant at a predetermined voltage or greater. | 2008-09-25 |
20080233762 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a high dielectric insulating layer. An amorphous high dielectric insulating layer having a high density is formed by using a precursor which can be deposited through the atomic layer deposition method at a temperature above 400° C. A resulting insulating exhibits a reduced crystallization during a subsequent annealing process. The capacitance equivalent thickness (CET) characteristic and the leakage current characteristic are improved. | 2008-09-25 |
20080233763 | METHOD OF ACHIEVING UNIFORM LENGTH OF CARBON NANOTUBES (CNTS) AND METHOD OF MANUFACTURING FIELD EMISSION DEVICE (FED) USING SUCH CNTS - In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predetermined depth to remove projected portions of the CNTs. After that, the organic film is removed. | 2008-09-25 |
20080233764 | Formation of Gate Insulation Film - A method of forming a gate insulation film | 2008-09-25 |
20080233765 | Method for enhancing adhesion between layers - A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging. | 2008-09-25 |
20080233766 | ASHING METHOD AND APPARATUS THEREFOR - An ashing method of a target substrate is applied after plasma-etching a part of a low-k film by using a patterned resist film as a mask in a vacuum processing chamber. The method includes a process of removing the resist film in the vacuum processing chamber, and a pre-ashing process, performed prior to the main ashing process, for ashing the target substrate for a time period while maintaining the target substrate at a temperature in a range of from about 80 to 150° C. | 2008-09-25 |
20080233767 | Bulb socket - A bulb socket is provided with a rubber socket into which a bulb is mounted and a resin cover which is mounted on the rubber socket by being put over the rubber socket. A projection which protrudes outward is formed on the resin cover. The resin cover is put over the rubber socket, inserted into a housing, rotated to engage the projection with an engaging part in the housing, and thereby mounted on the housing. At this time, the rubber socket comes into close contact with a socket mounting slot and thereby stops the socket mounting slot water-tightly. | 2008-09-25 |
20080233768 | INTELLIGENT, UNIVERSAL, RECONFIGURABLE ELECTROMECHANICAL INTERFACE FOR MODULAR SYSTEMS ASSEMBLY - An electromechanical connection includes a first conductor disposed in a first non-conductive array and a second conductor disposed in a second non-conductive array capable of mating with the first non-conductive array. The second conductor is capable of mating with the first conductor when the first non-conductive array and the second non-conductive array are mated. A processor associated with the first non-conductive array determines if an electrical connection is formed between the first conductor and the second conductor. The processor can assign a function to the electrical connection. | 2008-09-25 |
20080233769 | Right Angle Connection System for ATE Interface - There is disclosed apparatus for routing signals between at least one PCB within a test head and a socket card assembly. In an embodiment, the apparatus may include at least one flexible circuit electrically connecting first and second sides of the PCB and the socket card assembly with one another, and the flexible circuit having a defined shape configured to interface with the socket card assembly and the PCB along substantially perpendicular planes. Methods of routing signals between at least one PCB within a test head and a socket card assembly are disclosed. In one embodiment, a method may include electrically connecting first and second sides of the PCB and the socket card assembly with one another with at least one flexible circuit having a defined shape configured to interface with the socket card assembly and the PCB along substantially perpendicular planes. Other embodiments are also disclosed. | 2008-09-25 |
20080233770 | Electrical connector with retaining device - An electrical connector includes an insulating housing ( | 2008-09-25 |
20080233771 | CUSTOMIZABLE BACKER FOR ACHIEVING CONSISTENT LOADING AND ENGAGEMENT OF ARRAY PACKAGE CONNECTIONS - An electrical contact assembly includes a first module ( | 2008-09-25 |
20080233772 | METHOD AND SYSTEM FOR EASING ATTACHMENT OF A PERIPHERAL CABLE TO A PERSONAL COMPUTER - Aspects for easing the attachment of a peripheral cable to a personal computer (PC) include providing a connector with a symmetric shape that supports multiple orientations of cable attachment to a PC. An orientation of insertion is identified when the connector is attached to the PC, and signal lines from the connector are rearranged based on the identified orientation of the connector. | 2008-09-25 |
20080233773 | CAB POWER CONNECTORS - A wiring arrangement for interconnecting an alternating current power source to a receptacle within a motor vehicle includes a first wire harness having a current rating and a second wire harness having a similar current rating. A coupling mechanism electrically interconnects the first and second wire harnesses of similar current ratings. The coupling mechanism restricts interconnection of wire harnesses having dissimilar current ratings. | 2008-09-25 |
20080233774 | Electrical Receptacle for Outward Facing Ground Plugs - A multiplex electrical receptacle adapted for receiving at least a pair of power cords, such that the ground prongs of the power cords are directed outward from the center of the multiplex electrical receptacle in a “grounds out” configuration. The electrical receptacle of this invention includes an electrical outlet receptacle having a receptacle body, a conductive mounting strap, a conductive live blade receiving assembly, a conductive neutral blade receiving assembly, and a non-conductive housing. | 2008-09-25 |
20080233775 | Electrical card connector having grounding plate - An electrical card connector ( | 2008-09-25 |
20080233776 | RETRACTABLE MEMORY DRIVE - A retractable memory drive in accordance with the present invention comprises a top casing, a middle carrier, an electronic device such as a USB thumb drive, and a bottom casing. There are guide rails that allow the middle carrier to remain in an appropriate position. There is also a metal spring clip coupled to the middle carrier for contacting a connector of a device coupled to the drive to provide for improved EMI and ESD protection. | 2008-09-25 |
20080233777 | Device for restricting unauthorized access to electrical receptacles - A receptacle shroud and shroud removal tool coact to selectively restrict unauthorized access to a channel-bound electrical receptacle. The receptacle shroud comprises a channel-engaging wall and a receptacle cover. The receptacle cover comprises a tool-receiving aperture. The channel-engaging wall is sized and shaped for snug insertion in a pedestal-bounding, structure-receiving channel. The channel-engaging wall is retained by friction forces at shroud-to-channel interfacing. The shroud removal tool comprises a shroud-engaging end and a handle end. The shroud-engaging end is insertable through the tool-receiving aperture. The handle end enables a user to manually impart shroud-removing forces to the shroud-engaging end, which shroud-engaging end transfers the shroud-removing forces to the receptacle shroud. The shroud-removing forces are operable to remove the channel-engaging wall from the structure-receiving channel. | 2008-09-25 |
20080233778 | Shunted electrical connector and shunt therefore - An electrical connector is disclosed having a shunt member disposed between terminals in an electrical connector to shunt them together. The shunt member has shunt contacts defined by turned up portions from an edge of the members. | 2008-09-25 |