39th week of 2015 patent applcation highlights part 55 |
Patent application number | Title | Published |
20150270263 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are disclosed. In one aspect, the method includes forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate. The method also includes patterning the second and first semiconductor layers to form an initial fin. The method also includes selectively etching the first semiconductor layer of the initial fin to form a lateral recess in the first semiconductor layer. The method also includes filling the lateral recess with a dielectric material to form a body spacer. The method also includes forming an isolation layer on the substrate, wherein the isolation layer partially exposes the body spacer and thus defines a fin above the isolation layer. The method also includes forming a gate stack intersecting the fins on the isolation layer. | 2015-09-24 |
20150270264 | SHALLOW TRENCH ISOLATION FOR END FIN VARIATION CONTROL - A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap. | 2015-09-24 |
20150270265 | METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING - An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. | 2015-09-24 |
20150270266 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer. | 2015-09-24 |
20150270267 | ABRUPT SOURCE/DRAIN JUNCTION FORMATION USING A DIFFUSION FACILITATION LAYER - A method of forming a field effect transistor (FET) device includes forming a diffusion facilitation layer on top of a semiconductor substrate; forming a doped, raised source/drain (RSD) layer on the diffusion facilitation layer; removing a portion of the diffusion facilitation layer, corresponding to a region directly above a channel region of the FET device; and performing an anneal so as to define abrupt source and drain junctions in the semiconductor substrate, wherein dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate. | 2015-09-24 |
20150270268 | SEMICONDUCTOR DEVICE - The present invention is provided with: a plurality of pillars vertically arranged on a semiconductor substrate; a plurality of second diffusion layers respectively arranged on the upper part of each pillar; a conductive layer electrically connected to at least one of the second diffusion layers; and at least one contact formed on at least one of the plurality of second diffusion layers, the number of electrical connections (contacts) between the second diffusion layers and the conductive layer being smaller than the number of pillars, and the number of connections between the pillars and the conductive layer being changeable as needed. | 2015-09-24 |
20150270269 | METAL GATE STRUCTURE OF A CMOS SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate comprising an isolation region surrounding a P-active region and an N-active region. The semiconductor device also includes an N-metal gate electrode comprising a first metal composition over the N-active region. The semiconductor device further includes a P-metal gate electrode. The P-metal gate electrode includes a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes the first metal composition. The bulk portion includes a second metal composition different from the first metal composition. | 2015-09-24 |
20150270270 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V. | 2015-09-24 |
20150270271 | Semiconductor Integrated Circuit Device and Method For Producing The Same - A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film. | 2015-09-24 |
20150270272 | Finfet Drive Strength Modification - A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. | 2015-09-24 |
20150270273 | FLASH MEMORY DEVICE AND RELATED MANUFACTURING METHOD - A method for manufacturing a memory device may include obtaining a substrate structure that includes a substrate, an oxide material layer positioned on the substrate, a polysilicon material layer positioned on the oxide material layer, a first control gate and a second control gate positioned on the polysilicon material layer, and an offset oxide layer positioned between the first control gate and the second control gate. The method may further include the following steps: removing, using the offset oxide layer as a first mask, a portion of the polysilicon material layer for forming a polysilicon structure that includes a first step structure; forming a masking oxide layer on the offset oxide layer; removing, using the masking oxide layer as a second mask, a portion of the polysilicon structure for forming a floating gate polysilicon member that includes the first step structure and a second step structure. | 2015-09-24 |
20150270274 | METHOD OF FORMING SPLIT-GATE CELL FOR NON-VOLATIVE MEMORY DEVICES - Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates. | 2015-09-24 |
20150270275 | DAMASCENE NON-VOLATILE MEMORY CELLS AND METHODS FOR FORMING THE SAME - A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode. | 2015-09-24 |
20150270276 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device is provided, which may include: a well of a first conductivity type located within a substrate of a second conductivity type; a well terminal electrically coupled to the well; a floating gate disposed over the well; a floating gate terminal electrically coupled to the floating gate; a control gate disposed over the floating gate and electrically coupled to the well; and a control gate terminal electrically coupled to the control gate; wherein the floating gate terminal is configured to receive a first voltage; wherein the control gate terminal and the well terminal are configured to receive a second voltage. | 2015-09-24 |
20150270277 | Memory Cell and Manufacturing Method Thereof - The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof. | 2015-09-24 |
20150270278 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film. | 2015-09-24 |
20150270279 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films. | 2015-09-24 |
20150270280 | STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT - A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same. | 2015-09-24 |
20150270281 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes insulating patterns and conductive patterns stacked alternately with each other, penetrating structures passing through the insulating patterns and the conductive patterns, and deposition suppressing layers formed on one end portions of respective interfaces between the insulating patterns and the conductive patterns. | 2015-09-24 |
20150270282 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction. | 2015-09-24 |
20150270283 | NONVOLATILE MEMORY DEVICE, METHOD FOR OPERATING THE SAME, AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string. | 2015-09-24 |
20150270284 | JUNCTION BUTTING IN SOI TRANSISTOR WITH EMBEDDED SOURCE/DRAIN - After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects. | 2015-09-24 |
20150270285 | THIN CHANNEL-ON-INSULATOR MOSFET DEVICE WITH N+ EPITAXY SUBSTRATE AND EMBEDDED STRESSOR - A method of forming a field effect transistor (FET) device includes forming a recess in a PFET region of a starting semiconductor substrate comprising a bulk semiconductor layer an epitaxial n+ layer formed on the bulk semiconductor layer, a buried insulator (BOX) layer formed on the epitaxial n+ layer, and an active semiconductor or silicon-on-insulator (SOI) layer formed on the BOX layer, the recess being formed completely through the SOI layer, the BOX layer, and partially into the epitaxial n+ layer; epitaxially growing a silicon germanium (SiGe) transition layer on the epitaxial n+ layer, the SiGe transition layer having a lower dopant concentration than the epitaxial n+ layer; and epitaxially growing embedded source/drain (S/D) regions on the SiGe transition layer and adjacent the SOI layer in the PFET region, the embedded S/D regions comprising p-type doped SiGe. | 2015-09-24 |
20150270286 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL - The present invention discloses an array substrate comprising: a first substrate on which a thin film transistor and a data line are formed; and a shield metal layer comprising a first shield metal zone positioned at a location corresponding to a channel of the thin film transistor and a second shield metal zone positioned at a location corresponding to the data line. The present invention also discloses a display panel and a method for manufacturing the array substrate. The shield metal layer formed at the location on the array substrate corresponding to the data line, there is no any black matrix region between a color filter units along a direction corresponding to the data line. The display panel comprising the array substrate has increased aperture ratio of pixel, and difficulty of manufacturing the display panel is decreased. | 2015-09-24 |
20150270287 | DISPLAY DEVICE - A display device includes a substrate which has a display area and a non-display area adjacent to the display area, a first conductive wiring at the non-display area of the substrate, and a second conductive wiring at the non-display area of the substrate and on the first conductive wiring. The second conductive wiring surrounds at least a part of the first conductive wiring. | 2015-09-24 |
20150270288 | SEMICONDUCTOR DEVICE - Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacity with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing, a semiconductor device capable of high-speed reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a capacitor. A conductor penetrates and connects the first transistor, the capacitor, and the second transistor. An insulator is provided on a side surface of the conductor that penetrates the capacitor. | 2015-09-24 |
20150270289 | Method To Form Dual Channel Group III-V And Si/Ge FINFET CMOS And Integrated Circuit Fabricated Using The Method - A method includes providing a structure having a substrate, a first insulating layer on the substrate, a first semiconductor material layer on the first insulating layer, a second insulating layer on the first semiconductor layer in a first portion of the structure and a second semiconductor layer of a second, different semiconductor material on the second insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure forming a regrown semiconductor layer; forming first fins in the regrown semiconductor layer and second fins in the second semiconductor layer; and forming gate structures upon the first and second fins. A height difference, relative to a surface of the first insulating layer, of the gate structures formed upon the first fins and the gate structures formed upon the second fins is less than a predetermined value. | 2015-09-24 |
20150270290 | METAL OXIDE TFT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a metal oxide TFT device is provided. The method includes: selecting a substrate and forming a gate electrode on a first side of the substrate; sequentially depositing an insulating layer, a semiconductor layer, and a photoresist layer on the gate electrode; using the gate electrode as a photomask, exposing from a second side of the substrate and reserving the photoresist layer aligning to the gate electrode; depositing an electrode layer on the semiconductor layer and the reserved photoresist layer; stripping the reserved photoresist layer and lifting off the electrode layer stacked on the reserved photoresist layer; etching a part of the reserved electrode layer and the semiconductor layer, and forming a source electrode, a drain electrode, and a semiconductor island. The method realizes a self-alignment using the gate electrode as the photomask when forming the source, drain electrodes and the channel. Therefore, the manufacturing processes become simple and more accurate. | 2015-09-24 |
20150270291 | Array Substrate, Method for Preparing the Same and Display Device - The present invention provides an array substrate and method for preparing the same, and a display device. The array substrate comprises: a display area and a non-display area, and a plurality of signal connection wires located in the non-display area for connecting driver units, the signal connection wires comprising first connection wires electrically connected with the driver units and second connection wires electrically connected with the first connection wires, the second connection wires being arranged at least in two layers, and each layer of the second connection wires being insulated from one another. | 2015-09-24 |
20150270292 | SUBSTRATE DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention allows a current leakage path to be reliably disconnected even when a conductive film residue occurs between data wiring lines. An interlayer insulating film ( | 2015-09-24 |
20150270293 | PIXEL STRUCTURE - A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode. | 2015-09-24 |
20150270294 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties. | 2015-09-24 |
20150270295 | SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other. | 2015-09-24 |
20150270296 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD OF THE SAME - A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer. | 2015-09-24 |
20150270297 | HALF TONE MASK PLATE, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY APPARATUS - The present disclosure provides a half tone mask plate used to manufacture an active layer pattern as well as a source electrode pattern, a drain electrode pattern and a data line pattern located on the active layer pattern included in the array substrate. A surface of the array substrate includes a first region corresponding to the source electrode pattern, the drain electrode pattern and the data line pattern, a second region corresponding to a region of the active layer pattern located between the source electrode pattern and the drain electrode pattern, as well as a third region in addition to the first region and the second region; the half tone mask plate includes a semi-transparent region corresponding to the second region and a partial region of the third region. | 2015-09-24 |
20150270298 | SOLID-STATE IMAGING DEVICES AND METHODS OF FABRICATING THE SAME - Solid-state imaging devices and fabrication methods thereof are provided. The solid-state imaging device includes a substrate containing a first photoelectric conversion element and a second photoelectric conversion element. A color filter layer has a first color filter component and a second color filter component respectively disposed above the first and second photoelectric conversion elements. A light-shielding partition is disposed between the first and second color filter components. The light-shielding partition has a height lower than that of the first and second color filter components. A buffer layer is disposed between the first and second color filter components and above the light-shielding partition. The buffer layer has a refractive index lower than that of the color filter layer. | 2015-09-24 |
20150270299 | TFT AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, X-RAY DETECTOR AND DISPLAY DEVICE - A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film ( | 2015-09-24 |
20150270300 | CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A complementary metal-oxide-semiconductor (CMOS) image sensor includes a transfer gate formed on a substrate; a photo diode formed at or in a surface portion of the substrate on one side of the transfer gate, a floating diffusion region formed at or in a surface portion of the substrate on another side of the transfer gate, a first impurity region having a first conductive type formed at or in a surface portion of the substrate between the photo diode and the floating diffusion region, and a buried channel region having a second conductive type formed under the first impurity region. | 2015-09-24 |
20150270301 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first waveguide member is formed, as viewed from above, in an image pickup region and a peripheral region of a semiconductor substrate. A part of the first waveguide member, which part is disposed in the peripheral region, is removed. A flattening step is then performed to flatten a surface of the first waveguide member on the side opposite to the semiconductor substrate. | 2015-09-24 |
20150270302 | IMAGE SENSOR HAVING A GAPLESS MICROLENSES - An image sensor includes a plurality of photosensitive devices arranged in a semiconductor substrate. A planar layer is disposed over the plurality of photosensitive devices in the semiconductor substrate. A plurality of first microlenses comprised of a lens material is arranged in first lens regions on the planar layer. A plurality of lens barriers comprised of the lens material is arranged on the planar layer to provide boundaries that define second lens regions on the planar layer. A plurality of second microlenses comprised of the lens material is formed within the boundaries provided by the plurality of lens barriers that define the second lens regions on the planar layer. The plurality of lens barriers are integrated with respective second microlenses after a reflow process of the plurality of second microlenses. | 2015-09-24 |
20150270303 | IMAGE SENSOR WITH MICRO LENS - An image sensor includes a color filter configured to pass a specific color of light; a micro lens formed under the color filter and configured with a plurality of layers in which an upper layer has a smaller area than a lower layer; and a photo device formed under the micro lens and configured to receive light passing through the micro lens and convert the received light into an electrical signal. | 2015-09-24 |
20150270304 | SEMICONDUCTOR DEVICE, IMAGING DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes a wafer stack manufacturing process and a dicing process. The wafer stack manufacturing process includes: a first wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process. | 2015-09-24 |
20150270305 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device includes: a light-receiving pixel part configured to be formed on a semiconductor substrate; a black-level reference pixel part configured to be formed on the semiconductor substrate; and a multilayer interconnect part configured to be provided over the semiconductor substrate. The multilayer interconnect part includes an insulating layer formed over the semiconductor substrate and metal interconnect layers formed as a plurality of layers in the insulating layer. The multilayer interconnect part has a first light-blocking film formed above an area between first metal interconnects of a first metal interconnect layer as one of the metal interconnect layers above the black-level reference pixel part, and a second light-blocking film that is connected to the first light-blocking film and is formed of a second metal interconnect layer over the first metal interconnect layer. | 2015-09-24 |
20150270306 | PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS - Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region. | 2015-09-24 |
20150270307 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication. | 2015-09-24 |
20150270308 | CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A complementary metal-oxide-semiconductor (CMOS) image sensor includes a substrate including a photodiode, a transistor on the substrate; a first insulating layer on the substrate; a contact connected to the transistor and passing through the first insulating layer; an etch stop layer on the first insulating layer; a second insulating layer on the etch stop layer; and a signal line extending through the etch stop layer and the second insulating layer, on the first insulating layer and connected to the contact. | 2015-09-24 |
20150270309 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming, over a semiconductor substrate comprising a first region and a second region, a patterned first film in which an upper face of a portion located over the first region is positioned at a lower height from the semiconductor substrate than an upper face of a portion located over the second region, forming, over the first film, a second film which is an insulating film, a portion of the second film penetrating the first film and being located inside a trench of the semiconductor substrate, and polishing the second film to remove a portion of the second film located over the first film. An occupancy of the trench in the first region is lower than an occupancy of the trench in the second region. | 2015-09-24 |
20150270310 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing a solid-state image sensor which forms a wiring structure including a plurality of wiring layers on a semiconductor substrate including a photoelectric conversion unit, the method comprising steps of depositing a silicon-containing film which contains hydrogen on an uppermost wiring layer out of the plurality of wiring layers, and irradiating the silicon-containing film with UV light. | 2015-09-24 |
20150270311 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER - The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto. | 2015-09-24 |
20150270312 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes at least two control electrodes, a plurality of semiconductor layers and an insulating film. Each control electrode extends in a first direction. The semiconductor layers are provided between the control electrodes, and arranged in the first direction. Each semiconductor layer extends in a second direction orthogonal to the first direction. The insulating film covers side surfaces of the semiconductor layers, and is disposed between the control electrodes. Each semiconductor layer has a side surface that includes at least one curved surface swelling in a direction from a center of the semiconductor layer to the insulating film. | 2015-09-24 |
20150270313 | Organic Optoelectronic Component and Method for Operating the Organic Optoelectronic Component - An organic optoelectronic component and a method for operating the organic optoelectronic component are disclosed. In an embodiment an organic optoelectronic component includes at least one organic light emitting element, at least one first organic light detecting element including at least one first organic light detecting layer, and at least one second organic light detecting element including at least one second organic light detecting layer, wherein the at least one organic light emitting element, the at least one first organic light detecting element and the at least one second light detecting element are arranged laterally on a common substrate, wherein the at least one first organic light detecting element is configured to detect ambient light, and wherein the at least one second organic light detecting layer of the at least one second organic light detecting element is arranged between two non-transparent layers. | 2015-09-24 |
20150270314 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes: a first inorganic photoelectric converter; a semiconductor substrate that includes a light-receiving face to which light is to be incident and a circuit-formed surface on which a circuit including a readout circuit is formed, the light-receiving face facing the first inorganic photoelectric converter, the semiconductor substrate including a second inorganic photoelectric converter thereinside; and a first part including a microstructure arranged between the first inorganic photoelectric converter and the second inorganic photoelectric converter. | 2015-09-24 |
20150270315 | ORGANIC PHOTOELECTRIC CONVERSION ELEMENT AND IMAGING DEVICE - According to one embodiment, an organic photoelectric conversion element has a positive electrode, a first charge transport layer, an organic photoelectric conversion, a second charge transport layer and a negative electrode, in this order. The first charge transport layer contains a first charge transport material having a LUMO level equal to or greater than that of the organic photoelectric conversion layer. The second charge transport layer contains a second charge transport material having a HOMO level equal to or less than that of the organic photoelectric conversion layer. The first charge transport layer contains an electron trapping/scattering material that has a HOMO level which is +0.5 eV or more, or −0.5 eV or less, than the HOMO level of the first charge transport material, and has a LUMO level which is between −0.5 eV to +0.5 eV of the LUMO level of the first electron transport material. | 2015-09-24 |
20150270316 | LIGHT EMITTING APPARATUS - A first luminous body is formed on a substrate and is linear. A second luminous body is also formed on the substrate and is linear. The second luminous body extends in parallel with the first luminous body. A first anode and a first cathode are formed on the substrate, and supply electric power to the first luminous body. A second anode and a second cathode are also formed on the substrate, and supply electric power to the second luminous body. The first anode and the first cathode extend in parallel with each other, and the second anode and the second cathode extend in parallel with each other. In a range overlapping with the first luminous body when seen in a plan view, the first anode is not connected to the second anode, and the first cathode is not connected to the second cathode. | 2015-09-24 |
20150270317 | Pixel Patterns for Organic Light-Emitting Diode Display - An electronic device may include a display having an array of organic light-emitting diode display pixels. The display pixels may have subpixels of different colors. The subpixels may include red subpixels, green subpixels, and blue subpixels. The subpixels may be provided with shapes and orientations that improve manufacturing tolerances. Subpixels such as green and red subpixels may have hexagonal shapes while blue subpixel structures may be provided with diamond shapes coupled in pairs to form barbell-shaped blue subpixels. Subpixels can also be angled at 45° relative to horizontal. Subpixels ma have shapes that overlap adjacent display pixels. For example, an array of display pixels that has been rotated by 45° relative to the edges of a display substrate may have blue subpixels and or red subpixels that are shared between pairs of adjacent display pixels in an at of display pixels. | 2015-09-24 |
20150270318 | METHOD FOR PRODUCING ORGANIC ELECTRONIC DEVICES WITH BANK STRUCTURES, BANK STRUCTURES AND ELECTRONIC DEVICES PRODUCED THEREWITH - The present invention relates to a process for producing an organic electronic device, wherein a layer is selectively swelled with a swelling solvent so as to form bank structures allowing the deposition of the semiconductor material in a specific and well-defined area. The present invention further relates to bank structures, organic electronic devices and products or assemblies produced by said process. | 2015-09-24 |
20150270319 | MANUFACTURING METHOD OF AN ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE AND THE ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE - A manufacturing method of an organic electroluminescence display device including a device substrate provided with a plurality of pixel electrodes which have a gap part therebetween, a common electrode disposed opposite to the plurality of pixel electrodes, a light emitting layer provided over the plurality of pixel electrodes, and a bank layer provided in the gap part of the plurality of pixel electrodes, the method comprising forming a cover layer including a concave region to fit into a convex shaped part of the bank layer at a support substrate, forming a color filter layer facing the pixel electrode to the concave region, disposing a surface of the color filter layer on the device substrate so that the concave region fits into a convex shaped part, and attaching the cover layer and the color filter layer on the device substrate by peeling the cover layer from the support substrate. | 2015-09-24 |
20150270320 | ANODE CONNECTION STRUCTURE OF ORGANIC LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A method is provided for manufacturing an anode connection structure of an organic light-emitting diode. The anode connection structure includes: a thin-film transistor and an anode of an organic light-emitting diode arrange don the thin-film transistor. The thin-film transistor includes a low-temperature poly-silicon layer formed on a substrate, a gate insulation layer formed on the low-temperature poly-silicon layer, a gate formed on the gate insulation layer, a protection layer formed on the gate, and a source/drain formed on the protection layer. The method includes a step of forming a hole in the thin-film transistor to expose the low-temperature poly-silicon layer and a step of forming an electrically conductive layer in the hole for direct engagement with the low-temperature poly-silicon layer to serve as an anode and also the source/drain of the thin-film transistor. The anode of the organic light-emitting diode is thus directly connected to the low-temperature poly-silicon layer. | 2015-09-24 |
20150270321 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An object of the invention is to provide a method for manufacturing semiconductor devices that are flexible in which elements fabricated using a comparatively low-temperature (less than 500° C.) process are separated from a substrate. After a molybdenum film is formed over a glass substrate, a molybdenum oxide film is formed over the molybdenum film, a nonmetal inorganic film and an organic compound film are stacked over the molybdenum oxide film, and elements fabricated by a comparatively low-temperature (less than 500° C.) process are formed using existing manufacturing equipment for large glass substrates, the elements are separated from the glass substrate. | 2015-09-24 |
20150270322 | LIGHT EMITTING DEVICE - The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced. | 2015-09-24 |
20150270323 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a first conductive portion and a second conductive portion that are connected to each other via a contact hole which is formed through an insulation layer disposed between the first and second conductive portions. The display apparatus further includes a shield layer that covers at least one edge of the first conductive portion. | 2015-09-24 |
20150270324 | SEMICONDUCTOR DEVICE, DISPLAY UNIT, AND ELECTRONIC APPARATUS - There is provided a semiconductor device including: a transistor ( | 2015-09-24 |
20150270325 | DISPLAY SCREEN HAVING ORGANIC LIGHT-EMITTING DIODES - The invention relates to a matrix display screen which includes, in sequence: a mounting ( | 2015-09-24 |
20150270326 | ACTIVE MATRIX USING HYBRID INTEGRATED CIRCUIT AND BIPOLAR TRANSISTOR - A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed. | 2015-09-24 |
20150270327 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a substrate; a gate wire on the substrate; an interlayer insulating layer covering the gate wire; a data wire on the interlayer insulating layer; a passivation layer on the data wire and the interlayer insulating layer and having a protection opening; a pixel electrode on a first wiring portion of the data wire exposed through the protection opening and the interlayer insulating layer; a pixel definition layer on the passivation layer and having a pixel opening exposing the pixel electrode; an organic emission layer covering the pixel electrode; and a common electrode covering the organic emission layer and the pixel definition layer, wherein the pixel electrode contacting the first wiring portion of the data wire and the interlayer insulating layer has protrusions and depressions. | 2015-09-24 |
20150270328 | METHODS OF MANUFACTURING POLYRESISTORS WITH SELECTED TCR - Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR. | 2015-09-24 |
20150270329 | ELECTRICITY STORAGE DEVICE AND METHOD FOR MANUFACTURING ELECTRICITY STORAGE DEVICE - An electricity storage device includes a first electrode, a second electrode, an electricity storage layer, and a p-type semiconductor layer. The electricity storage layer is placed between the first electrode and the second electrode. The electricity storage layer contains a mixture of an insulating material and n-type semiconductor particles. The p-type semiconductor layer is placed between the electricity storage layer and the second electrode. The n-type semiconductor particles contain at least one of a titanium-niobium composite oxide and a titanium-tantalum composite oxide. | 2015-09-24 |
20150270330 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction. | 2015-09-24 |
20150270331 | ETCHSTOP LAYERS AND CAPACITORS - Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures. | 2015-09-24 |
20150270332 | SINGLE-CRYSTAL SOURCE-DRAIN MERGED BY POLYCRYSTALLINE MATERIAL - A method of forming a semiconductor structure includes forming a first fin and a second fin on a substrate. A gate structure is formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers are deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer is then deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin. The single-crystal epitaxial layers and the polycrystalline layer form a merged source-drain region. | 2015-09-24 |
20150270333 | Semiconductor Device with Peripheral Breakdown Protection - A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type. | 2015-09-24 |
20150270334 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, comprising a semiconductor base of a first conductivity type having a main surface, an element region arranged in the main surface; and a peripheral region surrounding the element region, the peripheral region comprising a field limiting ring region including a peripheral semiconductor region of a second conductivity type surrounding the element region in the main surface of the semiconductor base, the field limiting ring region including a groove formed in the peripheral semiconductor region, the groove extending in a film-thickness direction from an upper surface of the peripheral semiconductor region. As seen along a direction from the element region toward an outer edge of the peripheral region, a center position of the groove is closer to the element region than a center position of the peripheral semiconductor region. | 2015-09-24 |
20150270335 | HV COMPLEMENTARY BIPOLAR TRANSISTORS WITH LATERAL COLLECTORS ON SOI WITH RESURF REGIONS UNDER BURIED OXIDE - Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV. | 2015-09-24 |
20150270336 | METHOD FOR MANUFACTURING STRUCTURE HAVING AIR GAP - A method for manufacturing a structure having an air gap includes following steps. A plurality of patterns is formed in a pattern region of a substrate. A sacrificial layer is formed on the substrate, and a top surface of the sacrificial layer is lower than a top surface of the patterns to expose a plurality of upper portions of the patterns. A hard mask layer is formed to cover the sacrificial layer and the upper portions of the patterns. An etching-back process is performed to the hard mask layer to expose the sacrificial layer outside the pattern region, and the hard mask layer remaining inside the pattern region seals the opening between the upper portions of the patterns. The sacrificial layer is removed to form an air gap between the two adjacent patterns. | 2015-09-24 |
20150270337 | Semiconductor Device And Method for Producing the Same - A semiconductor device includes, on one semiconductor substrate: a first element isolation region having a first width, wherein a liner oxide film, a liner nitride film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the first element isolation region; and a second element isolation region having a second width that is larger than the first width, wherein a liner oxide film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the second element isolation region. | 2015-09-24 |
20150270338 | TRANSISTOR CHIP AND SEMICONDUCTOR DEVICE - A transistor chip includes at least two transistor cells; and a separation region electrically separating operation regions of the transistor cells from each other, wherein each of the transistor cells includes a gate pad, a drain pad, and a source pad. | 2015-09-24 |
20150270339 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device has a semiconductor substrate where a plurality of elements or penetration electrodes are arranged and a trench is arranged to insulate and separate the plurality of elements or penetrating elements by surrounding the plurality of elements or penetration electrodes. The trench is arranged to penetrate both sides of the semiconductor substrate, and has an inner part where a space is arranged. Accordingly, it is possible to configure a semiconductor device having a structure to suppress insulation breakdown while simplifying a manufacturing process and improving yield of product manufacture. | 2015-09-24 |
20150270340 | STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR - A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures. | 2015-09-24 |
20150270341 | METHOD FOR MANUFACTURING FIN STRUCTURE OF FINFET - The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate ( | 2015-09-24 |
20150270342 | Formation of Dislocations in Source and Drain Regions of FinFET Devices - Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices. | 2015-09-24 |
20150270343 | ABRUPT SOURCE/DRAIN JUNCTION FORMATION USING A DIFFUSION FACILITATION LAYER - A method of forming a field effect transistor (FET) device includes forming a diffusion facilitation layer on top of a semiconductor substrate; forming a doped, raised source/drain (RSD) layer on the diffusion facilitation layer; removing a portion of the diffusion facilitation layer, corresponding to a region directly above a channel region of the FET device; and performing an anneal so as to define abrupt source and drain junctions in the semiconductor substrate, wherein dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate. | 2015-09-24 |
20150270344 | P-FET WITH GRADED SILICON-GERMANIUM CHANNEL - A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile. | 2015-09-24 |
20150270345 | TRANSISTORS AND METHODS OF FORMING THE SAME - Provided is a method of fabricating a transistor. The method includes forming a fin portion protruding upward from a substrate, forming a device isolation pattern on the substrate to cover a lower portion of a sidewall of the fin portion, forming a trench in the device isolation pattern, the trench exposing a top surface and sidewalls of a channel region of the fin portion, and injecting a Group-IV element into the channel region of the fin portion to increase the volume of the channel region. | 2015-09-24 |
20150270346 | SEMICONDUCTOR DEVICES WITH A REPLACEMENT GATE STRUCTURE HAVING A RECESSED CHANNEL - Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening. | 2015-09-24 |
20150270347 | Semiconductor Device Including at Least One Type of Deep-Level Dopant - A semiconductor device includes a first semiconductor region including a first semiconductor material and a second semiconductor region adjoining the first semiconductor region, the second semiconductor region including a second semiconductor material different from the first semiconductor material. The semiconductor device further includes at least one of a drift zone and a base zone in the first semiconductor region, and at least one type of deep-level dopant in an emitter region of the second semiconductor region. The at least one type of deep-level dopant has a distance to the valence or conduction band of at least 100 meV. | 2015-09-24 |
20150270348 | SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE SIGE/SI FIN STRUCTURE - A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (SiGe) fin having a superlattice structure. The SiGe fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one silicon germanium fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a silicon germanium gate channel beneath the gate stack. | 2015-09-24 |
20150270349 | P-FET WITH STRAINED SILICON-GERMANIUM CHANNEL - A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region. | 2015-09-24 |
20150270350 | GRAPHENE-ON-SEMICONDUCTOR SUBSTRATES FOR ANALOG ELECTRONICS - Electrically conductive material structures, analog electronic devices incorporating the structures and methods for making the structures are provided. The structures include a layer of graphene on a semiconductor substrate. The graphene layer and the substrate are separated by an interfacial region that promotes transfer of charge carriers from the surface of the substrate to the graphene. | 2015-09-24 |
20150270351 | METHOD FOR FABRICATING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method. | 2015-09-24 |
20150270352 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor having a first conductivity type SiC layer, a second conductivity type SiC well region, a first conductivity type SiC first source region, a first conductivity type SiC first drain region, and a first gate electrode provided on the well region sandwiched between the first source region and the first drain region. The device includes a second transistor having a second conductivity type SiC second source region, a second conductivity type SiC second drain region provided on the SiC layer, and a second gate electrode provided on the SiC layer sandwiched between the second source region and the second drain region. There is an angle between a direction of a channel forming portion of first transistor and that of the second transistor. The device includes an element isolation region having a bottom positioned in the SiC layer. | 2015-09-24 |
20150270353 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device of according to an embodiment of the present disclosure includes a n-type SiC layer; a SiC region provided on the n-type SiC layer and containing H (hydrogen) or D (deuterium) in an amount of 1×10 | 2015-09-24 |
20150270354 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device of an embodiment includes a p-type SiC layer; a SiC region provided on the p-type SiC layer and containing H (hydrogen) or D (deuterium) in an amount of 1×10 | 2015-09-24 |
20150270355 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device includes: a first GaN based semiconductor layer (hereinafter abbreviated as GaN layer); a second GaN layer on the first GaN layer and having a bandgap larger than that of the first GaN layer; a source electrode on the second GaN layer; a drain electrode on the second GaN layer; a gate electrode between the source electrode and the drain electrode, a gate insulating film between the gate electrode and the first GaN layer, a film thickness of the second GaN layer between the gate electrode and the first GaN layer being thinner than that of the second GaN layer between the source electrode and the first GaN layer; and a p-type third GaN layer between the second GaN layer and an end portion on the drain electrode side of the gate electrode, the gate insulating film between the gate electrode and the third GaN layer. | 2015-09-24 |
20150270356 | VERTICAL NITRIDE SEMICONDUCTOR DEVICE - A vertical semiconductor device and a method of forming the same. A vertical semiconductor device has a substrate that includes a first material, a first electrode below the substrate, and at least one semiconductor region. The at least one semiconductor region includes a second material different from the first material. The second material is a III-nitride semiconductor material. The at least one semiconductor region is formed over the substrate. The vertical semiconductor device also has a second electrode over the at least one semiconductor region. | 2015-09-24 |
20150270357 | III-NITRIDE DEVICE AND METHOD HAVING A GATE ISOLATING STRUCTURE - A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate. | 2015-09-24 |
20150270358 | FABRICATION OF GRAPHENE ELECTRODES ON DIAMOND SUBSTRATE - One or more graphene layers may be formed on a diamond substrate by reforming sp | 2015-09-24 |
20150270359 | DIELECTRIC LINER FOR A SELF-ALIGNED CONTACT VIA STRUCTURE - At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active region contact via structures are formed through the at least one dielectric material layer to the source region and the drain region. A self-aligned gate contact cavity is formed over the gate electrode such that at least one sidewall of the gate contact cavity is a sidewall of the active region contact via structures. A dielectric spacer is formed at the periphery of the gate contact cavity by deposition of a dielectric liner and an anisotropic etch. A conductive material is deposited in the gate contact cavity and planarized to form a self-aligned gate contact via structure that is electrically isolated from the active region contact via structures by the dielectric spacer. | 2015-09-24 |
20150270360 | NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED FLOATING GATES - A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. A first source and a second source are disposed in the substrate and spaced apart from the drain mesa. A first floating gate overlaps with a first sidewall surface of the drain mesa and extends onto the first source, and a second floating gate overlaps with a second sidewall surface of the drain mesa and extends onto the second source. Related methods are also provided. | 2015-09-24 |
20150270361 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes steps of forming a trench in a surface of a semiconductor substrate of a first conductivity type in a depth direction; forming a conductive layer in the trench, with a first insulating film interposed therebetween; dividing the conductive layer into a gate electrode and an in-trench wiring layer which face each other in the trench and filling a gap between the gate electrode and the in-trench wiring layer with a second insulating film; introducing second-conductivity-type impurities into the entire surface of the semiconductor substrate to form a channel forming region of a second conductivity type; and selectively forming a main electrode region of the first conductivity type in a portion of the channel forming region which is provided along an opening portion of the trench so as to come into contact with the opening portion. | 2015-09-24 |
20150270362 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method for manufacturing the same are capable of improving GIDL in a buried gate, and preventing degradation of device characteristics and reliability due to reduction in gate resistance. The semiconductor device may include: junction regions formed at both sidewalls of a trench formed in a semiconductor substrate; a first gate electrode formed in a lower portion of the trench; a second gate electrode formed on at least one inner sidewall of the trench which overlaps one of the junction regions on the first gate electrode; and a third gate electrode formed on one side of the second gate electrode on the first gate electrode. | 2015-09-24 |