39th week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090236622 | White Semiconductor Light Emitting Device and Method for Manufacturing the Same - An LED chip ( | 2009-09-24 |
20090236623 | Light emitting diode device - A light emitting diode device includes a substrate, a reflector cup, a light emitting diode chip, and a phosphor paste. The reflector cup is set on the substrate, and has a wall of a first length and a first height wherein the first length is defined by a corresponding inner edge thereof. The LED chip is mounted on the substrate, and comprises a second length and a second height. The phosphor paste covers on the LED chip. The first height of the wall and the second height of the LED chip has a first ratio, and the first length of the wall and the second length of the LED chip has a second ratio wherein the first ratio is larger than the second ratio. | 2009-09-24 |
20090236624 | Organic light emitting device and organic light emitting display apparatus comprising the same - An organic light emitting device includes an anode electrode having an improved characteristic. The organic light emitting device is constructed with a first electrode including indium tungsten oxide (IWO) so that the anode electrode can be readily patterned, an organic light emitting layer formed on the first electrode, and a second electrode formed on the organic light emitting layer. An organic light emitting display apparatus may be constructed with the organic light emitting device. | 2009-09-24 |
20090236625 | LED DEVICE WITH CONDUCTIVE WINGS AND TABS - Apparatus for increased heat dissipation from a light-emitting diode (LED) die are provided. The apparatus may include a metal member thermally and electrically coupled to the LED die and having one or more wings for heat transfer away from the LED die and/or increased mechanical strength of the metal member. The wings may be flat, sloped, or tiered. For some embodiments, the wings may have holes in them in an effort to increase the structural integrity when combined with a housing, which made be composed of plastic or resin. | 2009-09-24 |
20090236626 | LED LAMP - An LED lamp includes a first heat sink, a second heat sink thermally contacting the first heat sink, and an LED module mounted on the first heat sink. The first heat sink comprises a plate and a plurality of first fins extending from the plate. The plate has a bare area on a top surface thereof. The LED module is mounted on the bare area and surrounded by the first fins of the first heat sink. The second heat sink comprises a base thermally contacting a bottom surface of the plate of the first heat sink and a plurality of second fins arranged at a bottom surface of the base of the second heat sink. Heat pipes are sandwiched between the plate and base of the first and second heat sinks. | 2009-09-24 |
20090236627 | METHOD OF FORMING METAL WIRING - Provided is a method of forming metal wiring. The method includes forming a photosensitive film pattern on a substrate, hydrophobicizing at least part of the photosensitive film pattern, coating metal ink on the substrate having the photosensitive film pattern, forming a seed layer, and forming a metal layer. Alternatively, a trench is formed by using the photosensitive film pattern as a mask, and metal aerosol is sprayed to form the seed layer and then the metal layer. In this method, there is no need to form a metal thin film on the photosensitive film pattern when the seed layer is formed. As a result, less metal is wasted, which, in turn, significantly reduces manufacturing costs. | 2009-09-24 |
20090236628 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a conductive substrate; a semiconductor light emitting layer which includes a first semiconductor layer formed on one surface of the conductive substrate and having a first conductivity type, and a second semiconductor layer formed on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type; first light emitting spots which are alternately arranged around a periphery of the semiconductor light emitting layer and emitting light to an exterior from the semiconductor light emitting layer; second light emitting spots having surfaces intersecting with the first light emitting spots and emitting light at an amount smaller than an amount of light emitted via the first light emitting spots; and wirings arranged along the second light emitting spots and electrically short circuiting an area between the first light emitting layer and the surfaces of the conductive substrate. | 2009-09-24 |
20090236629 | Sustrate and Semiconductor Light-Emitting Device - The present invention provides a substrate and a semiconductor light emitting device. Convexes having a curved surface are formed on the substrate. The semiconductor light emitting device comprises a substrate on which convexes having a curved surface are formed and a semiconductor layer on the substrate. | 2009-09-24 |
20090236630 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor light emitting device includes a nitride semiconductor multilayer film. The nitride semiconductor multilayer film is formed on a substrate and made of nitride semiconductor crystals, and includes a light emitting layer. In the nitride semiconductor multilayer film, facets of a cavity are formed, and a protective film made of aluminum nitride crystals is formed on at least one of the facets. The protective film has a crystal plane whose crystal axes form an angle of 90 degrees with crystal axes of a crystal plane of the nitride semiconductor crystals constituting the facet of the cavity having the protective film formed thereon. | 2009-09-24 |
20090236631 | Bidirectional PNPN silicon-controlled rectifier - The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type. | 2009-09-24 |
20090236632 | FET HAVING HIGH-K, VT MODIFYING CHANNEL AND GATE EXTENSION DEVOID OF HIGH-K AND/OR VT MODIFYING MATERIAL, AND DESIGN STRUCTURE - A field effect transistor (FET) including a high dielectric constant (high-k), threshold voltage (Vt) modifying channel and a gate extension devoid of the high-k and/or Vt modifying material, and a related design structure, are disclosed. In one embodiment, a FET may include a gate having a channel region thereunder including a gate insulator portion of a high dielectric constant (high-k) material and a threshold voltage (Vt) modifying portion (e.g., of SiGe); and a gate extension having a region thereunder devoid of at least one of the high-k material or the Vt modifying portion. | 2009-09-24 |
20090236633 | SRAM Devices Utilizing Strained-Channel Transistors and Methods of Manufacture - A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow. | 2009-09-24 |
20090236634 | Nitride semiconductor epitaxial wafer and nitride semiconductor device - A nitride semiconductor epitaxial wafer includes a growth substrate including a surface for growing a nitride semiconductor thereon, a first structure layer formed on the growth substrate, a dislocation propagation direction changing layer formed on the first structure layer for changing a propagation direction of a dislocation propagated in the first structure layer into a lateral direction, a second structure layer formed on the dislocation propagation direction changing layer, and a buffer layer formed on the second structure layer for changing a propagation direction of a dislocation propagated in the second structure layer. | 2009-09-24 |
20090236635 | WIDE BANDGAP HEMTS WITH SOURCE CONNECTED FIELD PLATES - A HEMT comprising an active region comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the active region. A spacer layer is formed on at least a portion of a surface of said active region and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT. | 2009-09-24 |
20090236636 | Closed Cell Array Structure Capable of Decreasing Area of non-well Junction Regions - A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of gate windows, each formed in a corner of a closed cell unit in a gate layer without doped source ion material. | 2009-09-24 |
20090236637 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer. | 2009-09-24 |
20090236638 | Semiconductor Constructions - The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region. | 2009-09-24 |
20090236639 | STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY - An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. | 2009-09-24 |
20090236640 | METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES - Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET. | 2009-09-24 |
20090236641 | Method of manufacturing semiconductor device for providing improved isolation between contact and cell gate electrode - A manufacture method is provided for forming a semiconductor device. The method includes: forming a plurality of gate electrodes through etching a conductive film deposited on a semiconductor substrate; forming a first nitride film to cover the gate electrodes; partially exposing the semiconductor substrate in a region between adjacent two of the gate electrodes through performing an etch-back process on the first nitride film; thermally oxidizing a residual of the gate electrode film remaining in the region between the adjacent two of the gate electrodes to change the residual into an thermal oxide film; and forming a contact in the region between the adjacent two of the gate electrodes. | 2009-09-24 |
20090236642 | TRANSISTOR AND CVD APPARATUS USED TO DEPOSIT GATE INSULATING FILM THEREOF - In a transistor adapted to suppress characteristic degradation resulting from fluorine contained in a deposited film, the concentration of fluorine contained in a gate insulating film is reduced to 1.0×10 | 2009-09-24 |
20090236643 | CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING - A method of manufacturing an image sensor is capable of preventing image lag and suppressing dark current by performing a substantially perfect reset process. Embodiments relate to a CMOS image sensor which includes a P−-type epi layer which is formed over a semiconductor substrate and defines a photodiode region FD, an active region, and a device isolation region. A device isolation film may be formed in the device isolation region and includes an electrode. A gate electrode may be formed over the P−-type epi layer with a gate insulating film interposed therebetween. | 2009-09-24 |
20090236644 | HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY - A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided. | 2009-09-24 |
20090236645 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; a high-concentration diffusion region of the first conductive type formed around the device isolation layer; a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween; a low-concentration diffusion region of a second conductive type formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and a high-concentration diffusion region of the second conductive type formed on the transistor region. | 2009-09-24 |
20090236646 | Field-effect transistor with spin-dependent transmission characteristics and non-volatile memory using the same - When a gate voltage V | 2009-09-24 |
20090236647 | SEMICONDUCTOR DEVICE WITH CAPACITOR - An embodiment of the invention is a semiconductor structure, comprising: a semiconductor chip at least partially embedded within a support; and a capacitor disposed outside the lateral boundary of the chip, the capacitor electrically coupled to the chip. | 2009-09-24 |
20090236648 | SEMICONDUCTOR DEVICE - To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner. | 2009-09-24 |
20090236649 | EMBEDDED MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF - An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory. | 2009-09-24 |
20090236650 | TANTALUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film. | 2009-09-24 |
20090236651 | SEMICONDUCTOR DEVICES HAVING A CONVEX ACTIVE REGION - Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions. | 2009-09-24 |
20090236652 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged. | 2009-09-24 |
20090236653 | Nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge. | 2009-09-24 |
20090236654 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film. | 2009-09-24 |
20090236655 | INTEGRATED CIRCUIT DEVICE GATE STRUCTURES - Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm | 2009-09-24 |
20090236656 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact. | 2009-09-24 |
20090236657 | IMPACT IONIZATION DEVICES AND METHODS OF MAKING THE SAME - Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices. | 2009-09-24 |
20090236658 | ARRAY OF VERTICAL TRIGATE TRANSISTORS AND METHOD OF PRODUCTION - An array of vertical trigate transistors and method of production are disclosed. One embodiment provides an array of selection transistors for selecting one of a plurality of memory cells. A selection transistor is a vertical trigate transistor. | 2009-09-24 |
20090236659 | ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICE WITH MULTIPLE TERMINALS - A semiconductor device has a first region ( | 2009-09-24 |
20090236660 | Insulated-Gate Field-Effect Transistor and Method of Making the Same - An IGFET that can be turned off when a reverse voltage is applied. Included is a semiconductor substrate having formed therein an n-type drain region, p-type first body region, p | 2009-09-24 |
20090236661 | DMOS-transistor having improved dielectric strength of drain source voltages - A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and has the same type of doping as the first well region. A gate electrode and a gate insulation layer for forming a transistor channel are included on a surface of the first well region. The DMOS-transistor further comprises an isolation structure, a highly doped drain doping region, and a second well complementarily doped to the first well region. The second well accommodates the first well region and the drain doping region. A highly doped region is formed at least adjacent to the second well and has the same type of doping as the second well for enhancing the dielectric strength of the highly doped source region. | 2009-09-24 |
20090236662 | GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION - A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor. | 2009-09-24 |
20090236663 | HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER - A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer. | 2009-09-24 |
20090236664 | INTEGRATION SCHEME FOR CONSTRAINED SEG GROWTH ON POLY DURING RAISED S/D PROCESSING - A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers. | 2009-09-24 |
20090236665 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 2009-09-24 |
20090236666 | Integrated Circuitry - Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs. | 2009-09-24 |
20090236667 | SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN - By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions. | 2009-09-24 |
20090236668 | METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE - The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer. | 2009-09-24 |
20090236669 | METAL GATE TRANSISTOR AND POLYSILICON RESISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region. | 2009-09-24 |
20090236670 | Semiconductor Device and a Manufacturing Process Thereof - A semiconductor device has a plurality of drain metal blocks, a plurality of source metal blocks, a plurality of polysilicon strips, a first source metal strip, a first drain metal strip, and a plurality of first conductive wires. Each of the source metal blocks is disposed between two of the drain metal blocks, and at least two of the polysilicon strips are correspondingly disposed across one of the drain metal blocks and one of the source metal blocks. The first source metal strip, in the absence of the polysilicon strips, is electrically connected to some of the source metal blocks. The first drain metal strip, in the absence of the polysilicon strips, is electrically connected to some of the drain metal blocks. The first conductive wires, coupled to the polysilicon strips, form a plurality of grids. | 2009-09-24 |
20090236671 | HIGH VOLTAGE-RESISTANT SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING HIGH VOLTAGE-RESISTANT SEMICONDUCTOR DEVICE - High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 Å in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes. | 2009-09-24 |
20090236672 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of metal-insulator-semiconductor (MIS) transistors formed on a surface portion of a semiconductor substrate; and an isolation region isolating each of element regions of the MIS transistors, the isolation region including a first isolation region formed with a coating type insulating film embedded in a first trench, the first trench surrounding each of the element regions of the MIS transistors, and a second isolation region formed with a coating type insulating film embedded in a second trench, the second trench surrounding at least one of the first isolation regions with a predetermined distance from each of the first isolation regions, wherein the semiconductor substrate exists between the first isolation region and the second isolation region. | 2009-09-24 |
20090236673 | METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY - A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout | 2009-09-24 |
20090236674 | MOS Transistor and Manufacturing Method Thereof - Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited thereon. A photolithography process is performed, and the silicon carbide layer is etched except for predetermined portions corresponding to source-drain regions and the gate electrode. Then, a metal layer is formed on the resulting structure after performing a source-drain ion implantation process. The metal layer is heated to form a salicide layer on the gate electrode and the source-drain diffusion regions. Then, the unreacted metal layer is removed, thereby forming the MOS transistor. | 2009-09-24 |
20090236675 | SELF-ALIGNED FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A self-aligned field-effect transistor (FET) is provided. The self-aligned FET includes a substrate, a dielectric layer, conductive electrodes, and a carbon nanotube. A patterned back-gated conductive electrode is disposed in the substrate. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer and function as a source/drain. The patterned source/drain conductive electrodes contain a metal silicide such as cobalt silicide serve as a catalyst for carbon nanotube synthesis. The carbon nanotube is disposed on the dielectric layer to be electrically connected with the source/drain conductive electrodes. | 2009-09-24 |
20090236676 | STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE - The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact the metal layer, wherein momentum transfer from of the chemically inert ions force metal atoms from the metal layer into the silicon containing gate conductor to provide a silicide gate conductor. | 2009-09-24 |
20090236677 | Micro Electro-Mechanical Sensor (MEMS) Fabricated with Ribbon Wire Bonds - A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon conductors are disposed over the conducting plane and electrically connected to the conducting via, such that the plurality of ribbon conductors form a transducer array in combination with the conducting plane, such as through capacitive coupling that changes in response to changes in the physical shape of the plurality of ribbons. | 2009-09-24 |
20090236678 | SENSOR DEVICE AND PRODUCTION METHOD THEREFOR - A sensor device having small variations in sensor characteristics and improved resistance to electrical noise is provided. This sensor device has a sensor unit, which is provided with a frame having an opening, a movable portion held in the opening to be movable relative to the frame, and a detecting portion for outputting an electric signal according to a positional displacement of the movable portion, and a package substrate made of a semiconductor material, and bonded to a surface of the sensor unit. The package substrate has an electrical insulating film on a surface facing the sensor unit. The package substrate is bonded to the sensor unit by forming a direct bonding between an activated surface of the electrical insulating film and an activated surface of the sensor unit at room temperature. | 2009-09-24 |
20090236679 | Schottky Diode Structures Having Deep Wells for Improving Breakdown Voltages - An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region. | 2009-09-24 |
20090236680 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR ITS PRODUCTION - A semiconductor device with a semiconductor body and method for its production is provided. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion. | 2009-09-24 |
20090236681 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 2009-09-24 |
20090236682 | LAYER STACK INCLUDING A TUNGSTEN LAYER - A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described. | 2009-09-24 |
20090236683 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 2009-09-24 |
20090236684 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND TRENCHES USING NON-CONCURRENTLY FORMED HARD MASK PATTERNS - A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trenches with a first insulation material to form first device isolation layers, forming a plurality of second trenches on a second region of the semiconductor substrate, and filling the second trenches with a second insulation material different from the first insulation material to form second device isolation layers, wherein the first trenches and the second trenches are formed using different respective processes. | 2009-09-24 |
20090236685 | EMBEDDED INTERCONNECTS, AND METHODS FOR FORMING SAME - The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition. | 2009-09-24 |
20090236686 | Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die - A semiconductor device is made by forming a first conductive layer over a temporary carrier. A UBM layer is formed over the temporary carrier and fixed in position relative to the first conductive layer. A conductive pillar is formed over the first conductive layer. A semiconductor die is mounted to the UBM layer to align the die relative to the conductive pillar. An encapsulant is deposited over the die and around the conductive pillar. The UBM layer prevents shifting of the semiconductor die while depositing the encapsulant. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected through the conductive pillar. The first or second interconnect structure includes an integrated passive device electrically connected to the conductive pillar. | 2009-09-24 |
20090236687 | Fuse of Semiconductor Device and Method for Forming the Same - A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process. | 2009-09-24 |
20090236688 | SEMICONDUCTOR DEVICE HAVING FUSE PATTERN AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern. | 2009-09-24 |
20090236689 | INTEGRATED PASSIVE DEVICE AND METHOD WITH LOW COST SUBSTRATE - According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device ( | 2009-09-24 |
20090236690 | WIRE BOND AND REDISTRIBUTION LAYER PROCESS - A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip. | 2009-09-24 |
20090236691 | DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR - A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench. | 2009-09-24 |
20090236692 | RC FILTERING DEVICE HAVING AIR GAP CONSTRUCTION FOR OVER VOLTAGE PROTECTION - The present invention relates to a RC filtering device, consists of: a lower substrate, a first intermediate substrate, a second intermediate substrate and an upper substrate. On top surface of the lower substrate is a cross form electrode layer. At both ends of the electrode layer in one direction forms a pair of air gaps to function as over voltage protection. The first intermediate substrate is formed above the lower substrate also has a pair of grooves corresponding to said air gaps, and on the top surface of the second intermediate layer, there is a transmission wire. The said transmission wire is formed with metallic layer at its both ends and the metallic oxide layer made with electrical resistance, this transmission wire and the electrode layer on the lower substrate form an RC filtering device. | 2009-09-24 |
20090236693 | Planarization of Gan by Photoresist Technique Using an Inductively Coupled Plasma - Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chose photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductivel coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarize III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided. | 2009-09-24 |
20090236694 | Method of Manufacturing III-Nitride Crystal, and Semiconductor Device Utilizing the Crystal - The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal ( | 2009-09-24 |
20090236695 | Semiconductor Wafer With A Heteroepitaxial Layer And A Method For Producing The Wafer - A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate. | 2009-09-24 |
20090236696 | Semiconductor Wafer With A Heteroepitaxial Layer and A Method For Producing The Wafer - A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate. | 2009-09-24 |
20090236697 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part. | 2009-09-24 |
20090236698 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability. | 2009-09-24 |
20090236699 | DISCREET PLACEMENT OF RADIATION SOURCES ON INTEGRATED CIRCUIT DEVICES - An integrated circuit and methods of forming and using the integrated circuit. The circuit includes: a radiation-emitting layer over a selected region of a top surface of an integrated circuit chip, the radiation emitting layer comprising a first polymer or resin and a first radioactive material, the region smaller than a whole of the top surface of the integrated circuit chip, the region including a circuit that is liable to temporary failure when struck by radiation generated by the first radioactive material. | 2009-09-24 |
20090236700 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode. | 2009-09-24 |
20090236701 | Chip arrangement and a method of determining an inductivity compensation structure for compensating a bond wire inductivity in a chip arrangement - A chip arrangement is disclosed. The chip arrangement includes a first chip, a first bond wire having an inductive element and coupled with the first chip at its one end and an inductivity compensation structure including a first conductive plate coupled with the first bond wire at the other end of the first bond wire, and a second conductive plate arranged in parallel to the first conductive plate, wherein the first conductive plate and the second conductive plate are configured such that a resonant condition for a partial circuit formed by the first bond wire and the inductivity compensation structure is formed to compensate for the inductive element of the first bond wire. A method of determining an inductivity compensation structure for compensating a bond wire inductivity in a chip arrangement is also disclosed. | 2009-09-24 |
20090236702 | SiP SUBSTRATE - Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace. | 2009-09-24 |
20090236703 | Chip package structure and the method thereof - A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 2009-09-24 |
20090236704 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ISOLATED LEADS - An integrated circuit package system comprising: forming a finger; forming a die pad adjacent the finger; applying a fill material around the finger and the die pad; forming a cavity in the finger and fill material; and attaching an integrated circuit die over the die pad adjacent the finger with the fill material. | 2009-09-24 |
20090236705 | APPARATUS AND METHOD FOR SERIES CONNECTION OF TWO DIE OR CHIPS IN SINGLE ELECTRONICS PACKAGE - An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions. Alternatively, it can be by adding an electrically isolating coating on the non-active area of the P-side of a semiconductor device to allow it to be mounted P side down on an electrically conductive substrate or mounting location without modification to the substrate or lead frame. | 2009-09-24 |
20090236706 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively. | 2009-09-24 |
20090236707 | ELECTRONIC DEVICES WITH ENHANCED HEAT SPREADING - An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer. | 2009-09-24 |
20090236708 | SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION - A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metallized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metallized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions. | 2009-09-24 |
20090236709 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is disclosed. The semiconductor chip package comprises a lead frame having a chip carrier, wherein the chip carrier has a first surface and an opposite second surface. A semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier. A package substrate comprises a central region attached to the second surface, having an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a marginal region of the package substrate. | 2009-09-24 |
20090236710 | COL SEMICONDUCTOR PACKAGE - A Chip-On-Lead (COL) semiconductor package is revealed, primarily comprising a plurality of leadframe's leads each having a carrying bar, a finger and a connecting portion connecting the carrying bar to the finger. A chip has a back surface attached to the carrying bars and is electrically connected to the fingers by a plurality of bonding wires. Therein, at least one of the bonding wires overpasses one of the connecting portions without electrical relationship. An insulation tape is attached onto the connecting portions in a manner to be formed between the overpassing section of the bonding wire and the overpast connecting portion so that electrical short can be avoided during wire-bonding processes of the COL semiconductor package. Therefore, the carrying bars under the chip have more flexibility in the layout design of COL semiconductor packages to use die pad(s) with smaller dimensions or even eliminate die pad. | 2009-09-24 |
20090236711 | METHOD OF MAKING AND DESIGNING LEAD FRAMES FOR SEMICONDUCTOR PACKAGES - A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired. | 2009-09-24 |
20090236712 | IC PACKAGE HAVING REDUCED THICKNESS - An IC package having reduced thickness includes a lead frame, a chip, and a plurality of bonding wires. The lead frame includes a front side, a rear side, a plurality of pins located on the front side, and a hollow portion formed on the lead frame. The chip is larger than the rear side of the lead frame. The chip includes a plurality of electrodes and is adhered to the rear side of the lead frame. The electrodes correspond to the hollow portion. The bonding wires pass through the hollow portion to be connected with the pins and the electrodes. Accordingly, the IC package can effectively take good use of the space below the lead frame, reducing the height of the bonding wires and saving the packaging space above the lead frame, and reduce the thickness of the IC package without addition of the cost and equipment. | 2009-09-24 |
20090236713 | SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT - In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits. | 2009-09-24 |
20090236714 | ROBUST LEADED MOLDED PACKAGES AND METHODS FOR FORMING THE SAME - A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region. | 2009-09-24 |
20090236715 | SEMICONDUCTOR PACKAGE STRUCTURE WITH LAMINATED INTERPOSING LAYER - The invention relates to microelectronic semiconductor chip assemblies having vertically stacked layers. In a disclosed example of a preferred embodiment, a vertically stacked semiconductor chip assembly includes a first semiconductor chip affixed to the surface of a substrate. A laminated interposing layer therebetween includes a first adhesive material and a second adhesive material, at least one of the adhesive materials adapted to capturing debris. Methods are disclosed for making a vertically stacked semiconductor chip assemblies by joining first and second adhesive materials to form a laminated interposing layer between a first chip and second chip or substrate. In preferred embodiments of the invention, the interposing layer includes polyimide film and one adhesive material of relatively low elasticity, and another adhesive material having relatively high elasticity. | 2009-09-24 |
20090236716 | RECTIFYING DIODE PACKAGE STRUCTURE - A rectifying diode package structure includes a base which has a holding deck to hold a diode chip and a protective portion on the perimeter of the base to form sealing space filled by a filling material to seal the diode chip in an integrated manner. The diode chip has a conductive element extended outside the sealing space. The holding deck and the protective portion are interposed by a buffer ring embedded in the filling material. The buffer ring has at least one retaining ridge which has at least one first end and one second end of different cross sections formed in an upright manner to form a retaining relationship between the buffer ring and the filling material. | 2009-09-24 |
20090236717 | Organic Electronic Component With Dessicant-Containing Passivation Material - The invention relates to an organic electronic component, such as e.g. an organic light diode or an organic solar cell with structures made of passivation material, the passivation material comprising at least one dessicant. | 2009-09-24 |
20090236718 | PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER - A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors. | 2009-09-24 |
20090236719 | PACKAGE IN PACKAGE SYSTEM INCORPORATING AN INTERNAL STIFFENER COMPONENT - The present invention is a package-in-package system, comprising: providing a bottom internal stacking module incorporating a semiconductor die and a package substrate, attaching an internal stiffening module with a die receptacle on the bottom internal stacking module, and attaching a top internal stacking module incorporating a semiconductor die and a package substrate upside-down on the internal stiffening module. | 2009-09-24 |
20090236720 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STEP MOLD RECESS - An integrated circuit package system includes: providing a stackable integrated circuit package system having a base encapsulation and a recess therein; stacking a top integrated circuit package system, having a top encapsulation with a protruding portion, with the stackable integrated circuit package system with the protruding portion aligned and matched within the recess; and connecting the top integrated circuit package system and the stackable integrated circuit package system. | 2009-09-24 |
20090236721 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern. | 2009-09-24 |