38th week of 2010 patent applcation highlights part 28 |
Patent application number | Title | Published |
20100238661 | ASYMMETRICAL LIGHT PRODUCING BAFFLE AND LUMINAIRE INCLUSIVE THEREOF - Disclosed is a baffle assembly configured for asymmetric distribution of light, the baffle assembly including a baffle body, a series of baffle blades disposed with the baffle body, and a series of openings defined by at least one of the baffle body and the blades of the series of baffle blades, the openings being configured for passage of the light, wherein the series of blades is configured to redirect the light that passes through the openings, wherein the blades are angled away from perpendicular or parallel disposal relative to a plane normal to a centerline of the baffle body. | 2010-09-23 |
20100238662 | OUTDOOR LAMP HAVING WATERPROOF FASTENING ASSEMBLY - A waterproof fastening assembly secures a first structure to a second structure. The first structure defines a number of through holes and a number of flanges surrounding the through holes, respectively. The second structure defines a number of screw holes and includes a number of LED light source modules. A connection shank extends through a corresponding through hole and screws in a corresponding screw hole. An elastic waterproof ring comprises an annular body and a number of protrusions protruding from a top surface of the body. When the first structure is secured to the second structure, the connection shank presses the protrusions to enable the elastic waterproof ring to deform outwardly and inwardly simultaneously. The flange of the first structure resists the outward deformation of the elastic waterproof ring, meanwhile the body of the elastic waterproof ring inwardly engages the connection shank. | 2010-09-23 |
20100238663 | Adjustable Light-Emitting Diode Display Module - An adjustable LED display module is provided, including a plurality of light-emitting units, and at least a set of spacing adjusting mechanism. The spacing adjusting mechanism is of a retractable grid-like structure or a retractable mesh-structure. The plural light-emitting units are distributed on different locations of the components of the spacing adjusting mechanism. When the spacing adjusting mechanism operates to adjust the spacing, at least spacing between some neighboring light-emitting units will change so that the location after adjustment will vary. Hence, the display module will have different form factor and light dots arrangement to provide higher flexibility to fit various application environments and conditions as well as convenience for storage and transportation when contracted. | 2010-09-23 |
20100238664 | AMBIENT LIGHT USING SWITCHABLE CANVAS - A display system includes a unit configured to provide information, and a plate extending away from the unit in at least one direction. The plate is configured to receive input light and to provide ambient light that may be related to the information. In response to voltage levels, the plate is substantially transparent in a transparent mode and substantially light scattering in a scattering mode to provide the ambient light. | 2010-09-23 |
20100238665 | DIFFUSIVE LIGHT REFLECTORS WITH POLYMERIC COATING - A diffuse light reflector is disclosed for use in lighting fixtures including luminaires, light boxes, displays, signage, daylighting applications, and the like. The reflector includes a light reflective nonwoven and a polymer layer that enhances reflectivity. The reflector can be laminated to coil steel or aluminum and can be formed in metal coil or sheet forming operations. The polymer layer can be easily cleaned of machine oils from the metal forming operations. | 2010-09-23 |
20100238666 | Prism and lighting device - A prism includes a light incident portion that has first and second convex portions, the first and second convex portions each are a convex portion that refracts rays of light incident to a prism body and reduces a spread angle after incidence to the prism body via the convex portion to be smaller than that before the incidence, the spread angle is an angle between a given two of the rays, a first reflecting surface, provided on the prism body, that can reflect a first ray of light that has entered the prism body via the first convex portion, a first emitting portion, provided on the prism body, that emits, to the outside, the first ray reflected by the first reflecting surface, and a second emitting portion that emits, to the outside, a second ray of light that has entered the prism body via the second convex portion. | 2010-09-23 |
20100238667 | ELECTRONIC DEVICE WITH ILLUMINATED LOGO - An electronic device includes a semitransparent housing and a light module. The light module is mounted in the housing, and includes a light source, a light guide, and a light tight shield. The light guide includes a logo. The light tight shield coveres the light guide, and defines an opening aligned with and exposing the logo to the housing. Light emitted by the light source illuminates the logo through the light guide and spreads out from the opening. The logo is not visible when not being illuminated. | 2010-09-23 |
20100238668 | OPTICAL LENS AND ILLUMINATING DEVICE INCORPORATING THE SAME - An optical lens includes an array of lens units. Each lens unit includes a main body, a light diverging portion and a light converging portion. The main body includes a light incident surface and a light emitting surface opposite to the light incident surface. The light diverging portion is configured for expanding a light field along a first direction, and the light converging portion is configured for compressing a light field along a second direction. The light diverging portion and the light converging portion are both formed on one of the light incident surface and the light emitting surface. | 2010-09-23 |
20100238669 | LED Device for Wide Beam Generation and Method of Making the Same - A predetermined illuminated surface pattern is generated from a predetermined energy distribution pattern of an LED light source within an LED package having a light transmitting dome. An estimated optical transfer function of a lens shape of an optic is defined by the shape of an exterior and inner surface which envelopes at least in part the light transmitting dome of the LED package. An energy distribution pattern is obtained by combination of the estimated optical transfer function and the predetermined energy distribution pattern of the light source. A projection of the energy distribution pattern onto the illuminated surface is determined. The projection is compared to the predetermined illuminated surface pattern. The estimated optical transfer function is illuminated surface pattern. | 2010-09-23 |
20100238670 | Recessed ceiling fixture enclosure - An enclosure for use in conjunction with a recessed ceiling fixture is provided which includes a substantially rectangular housing defining a top wall and side walls constructed from a single piece of fire-resistant gypsum wallboard. The housing is fastened to continuous stamped metal support flange depend inwardly from bottom edges of side walls of the housing to facilitate mounting of the housing between spaced apart building joists. The recessed fixture is mounted to the interior of the support flange after installation of the housing between the building joists. | 2010-09-23 |
20100238671 | LED LUMINAIRE - A luminaire having a plurality of LED boards mounted within a housing is provided. Each LED board has at least one light emitting diode mounted thereon and an axis extending from a first end of the board to a second end of the board. Each LED board is adjusted about its respective axis to an orientation that is unique from at least two other LED boards. | 2010-09-23 |
20100238672 | LIGHT-EMITTING DIODE LIGHT BULB AND APPLICATION THEREOF - A light-emitting diode (LED) light bulb and an application thereof are described. The light-emitting diode light bulb comprises: a light-emitting diode light source module; a base, wherein the light-emitting diode light source module is disposed on the base; and a driver portion to drive the light-emitting diode light source module, comprising a rotation shaft, wherein the driver portion is connected to the base via the rotation shaft, such that the light-emitting diode light source module can rotate relative to the driver portion. | 2010-09-23 |
20100238673 | Modular light fixtures - A modular light fixture having a construction that enables the same fixture to be used for standard on/off operation under control of a wall-mounted switch in a circuit by itself and/or with other fixtures and to be upgraded in “plug and play” fashion to operate independently of other fixtures in the same circuit and/or for stepped dimming. The modular construction of the fixture also allows for safety and ease of maintenance in that ballasts can be replaced without quickly and conveniently without exposing an electrician or maintenance worker to the internal wires of the fixture. The construction of the fixture also provides temperature management by isolating the temperature-sensitive components of the fixture from high temperatures while placing the lamps of the fixture in an enclosure, or shroud, in which temperature is contained so that the lamps operate efficiently. In the event the passive thermal management provided by the construction of the fixture is not enough to maximize the operating efficiency of the fixture and/or the service life of its components, the fixture is upgradeable, again in plug and play fashion, to provide active thermal management. | 2010-09-23 |
20100238674 | LIGHTING DEVICE - A lighting device comprises: a first substrate comprising a first connector and a first connection terminal, the first connector being connected to an external power supply or driving device, the first connection terminal being electrically connected to the first connector; and a second substrate connected electrically to the first connection terminal and comprising a light emitting device. | 2010-09-23 |
20100238675 | LIGHTING OR SIGNALING DEVICE COMPRISING A CURVED LIGHT GUIDING PLATE - A lighting or signaling device for a motor vehicle which is capable of emitting a linear beam in the direction of an optical axis and which comprises a point light source that emits light rays radially around a source; a light ray guiding plate; wherein the light guiding plate is shaped so that the light rays generally propagate in incident propagation planes normal to the plate between the light source and the reflection edge and in reflected propagation planes normal to the plate between the reflection edge and the output edge. | 2010-09-23 |
20100238676 | VEHICLE LAMP - A vehicle lamp includes a first lamp unit and a second lamp unit. The first lamp unit includes a first light source, a reflector on which the first light source is mounted, and a first lamp body on which the reflector is supported. The reflector reflects light emitted from the first light source. The second lamp unit includes a second light source, and a second lamp body on which the second light source is mounted. The second lamp body is configured as a one-piece structure including a concealing portion. The concealing portion partially conceals the first lamp unit in a front view of the vehicle lamp. | 2010-09-23 |
20100238677 | LED ILLUMINATION MODULE WITH TOUCH SENSITIVE CONTROLS AND OVERHEAD CONSOLE USING THE MODULE - The invention discloses an illumination module with an LED light source for illuminating interior of the vehicle and for establishing a map reading light, controlled by a touch sensitive switch. A further aspect of the invention shows an overhead console that encloses additional modules: module with a door light switch, a module with a pivotable door member to form a compartment, module with touch sensitive switch for sun roof, module with LEDs for rear compartment illumination. | 2010-09-23 |
20100238678 | LIGHT PIPE AND LIGHT GUIDING DEVICE WITH SAME - An exemplary light pipe includes a main pipe and branch pipes. The main pipe includes a light inputting segment, an end portion, and a light outputting segment between the light inputting segment and the end portion. The light inputting segment includes connecting openings defined therein. A distance between each connecting opening and the end portion of the main pipe is different from a distance between each other connecting opening and the end portion of the main pipe. The branch pipes connect with the light inputting segment at the respective connecting openings. | 2010-09-23 |
20100238679 | LIGHT PIPE STRUCTURE AND LUMINAIRE WITH LIGHT PIPE STRUCTURE - Disclosed is a light pipe structure configured for transmittal of light rays, the light pipe structure including a light entry end associated with a visible end via a light pipe body, the light entry end being configured for entrance of the light rays, and a depression disposed in a visible surface of the visible end, the depression being disposed substantially along a major axis of the visible surface. | 2010-09-23 |
20100238680 | LASER ENERGY SOURCE DEVICE AND METHOD - An innovative device and method for providing a laser system utilizing high efficiency diode lasers and optionally the high quality beam characteristics of a crystal gain medium single mode laser by utilizing an optical and mechanical method of forming the beam and directing it to the desired target. | 2010-09-23 |
20100238681 | OPTICAL-FIBER-BASED LIGHT SOURCE - Various embodiments of the present invention are directed to optical-fiber-based light sources for use in microscopy, spectrometry, and other scientific and technical instruments, devices, and processes. Light-emitting diodes (“LEDs”) and other light sources are, in various embodiments of the present invention, incorporated on or within an optical fiber or fiber-optic cable in order to produce a bright optical-fiber-based light source. By incorporating light-emitting devices on or within an optical fiber, a significantly greater photon flux can be obtained, within the optical fiber or fiber-optic cable, than can be obtained by directing light from equivalent, external light-emitting elements into the optical fiber or fiber-optic cable, and the optical-fiber-based light sources of the present invention provide desirable characteristics of the light sources embedded on or within them. | 2010-09-23 |
20100238682 | HeadLyte safety device - The “HeadLyte” Safety Device is intended to be attached or embedded within a helmet worn by a bicyclist, or, worn around the head of a walker or jogger. The “HeadLyte” is comprised of a band that is populated with light emitting devices providing 360 degrees of illumination. The purpose of this illumination is to alert other individuals and/or vehicles as to the presence and direction of travel of the person wearing the “HeadLyte”, The light emitting devices are connected to a power source and a microcontroller that enables them to flash in a variety of patterns. The light emitting devices may also utilize color to indicate direction of color. The increased visibility provided by the light emitting devices, combined with the location of the “HeadLyte” as it is worn at the highest possible point on the walker, jogger or bicyclist will further enhance the visibility of the wearer to others. | 2010-09-23 |
20100238683 | FLEXIBLE LIGHT-EMITTING APPARATUS - A flexible light-emitting apparatus including a side light-emitting flexible light guide rod, two light emitting diodes, and two lenses is provided. The side light-emitting flexible light guide rod has a first end, a second end opposite to the first end, and a light-emitting surface connecting the first and the second ends. The LEDs are respectively disposed beside the first end and the second end and adapted for emitting light beams toward the side light-emitting flexible light guide rod, respectively. One of the lenses is located between the first end and the LED disposed beside the first end, and the other lens is located between the second end and the LED disposed beside the second end. Each of the light beams enters the side light-emitting flexible light guide rod through the corresponding lens and is transmitted to the outside of the side light-emitting flexible light guide rod through the light-emitting surface. | 2010-09-23 |
20100238684 | BACKLIGHT MODULE - A backlight module includes a plurality of first light sources emitting first light and a light guide plate. The first light sources are arranged in a line and spaced from each other. Two adjacent first light sources define a first space therebetween. The light guide plate includes a first light incident surface and a light output surface. The first light incident surface has a plurality of bright areas respectively corresponding to the first light sources and a plurality of dark areas respectively corresponding to the first spaces. A plurality of first reflectors is disposed on the plurality of dark areas of the first incident surface. The light output surface is adjacent and perpendicular to the light incident surface. | 2010-09-23 |
20100238685 | LIGHT DIFFRACTION MEMBER AND DISPLAY AND BACKLIGHT MODULE HAVING THE SAME - A display including a display panel and a backlight module adjacent to the display penal is provided. The backlight module includes a light source emitting a light beam and at least one light diffraction member. The light diffraction member includes a first surface, a second surface, an azimuth convergence structure and a light diffraction structure. The second surface is opposite the first surface, and the light beam enters the light diffraction member through the second surface and leaves the light diffraction member from the first surface. The azimuth convergence structure is disposed on the second surface for converging the azimuth of the light beam incident thereon. The light diffraction structure is disposed on the first surface for adjusting the emergence angle of the light beam. | 2010-09-23 |
20100238686 | RECYCLING BACKLIGHTS WITH SEMI-SPECULAR COMPONENTS - A hollow light-recycling backlight has a “semi-specular” component providing a balance of specularly and diffusely reflected light improving the uniformity of the light output. The component may be arranged on the reflectors ( | 2010-09-23 |
20100238687 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device of what is called a side view type can achieve directional characteristics having substantial symmetry with respect to an optical axis. The semiconductor light emitting device can emit light in a direction substantially parallel to a surface on which the semiconductor light emitting device is to be held. The semiconductor light emitting device can include a semiconductor light emitting element emitting light in a light emitting direction parallel to the surface on which the semiconductor light emitting element is to be held, a base substrate having a main surface on which the semiconductor light emitting device is held, the main surface being parallel to the surface on which the semiconductor light emitting device is to be held. The base substrate can have a cutoff portion defined forward of the semiconductor light emitting element in the light emitting direction and in a position in which light emitted from the semiconductor light emitting element crosses the main surface. A light-transmitting first sealing resin can be provided on the base substrate, to bury the semiconductor light emitting element while filling the cutoff portion. The light emitted from the semiconductor light emitting element can travel through the cutoff portion. | 2010-09-23 |
20100238688 | POWER SUPPLY APPARATUS - The DC power supply apparatus includes a switching operation control part that is provided between a current detection part to detect a current flowing through a primary coil of a transformer and a control part to control the operation of a switching part and controls the operation of the switching part according to an output voltage so that consumption power in a low-load state can be further reduced. | 2010-09-23 |
20100238689 | METHOD AND APPARATUS FOR CONTROLLING A CONSTANT CURRENT OUTPUT IN A SWITCHING MODE POWER SUPPLY - A controller for providing a constant output current control signal in a switched mode power supply (SMPS) includes a conduction time compensation circuit that is configured to produce a compensated conduction time interval signal that includes compensation for a ringing waveform of a feedback signal. The compensated signal reflects more accurately the actual conductive time of a rectifying diode in a secondary winding of the switched mode power supply. In one embodiment, the compensated conduction time interval signal is used to generate a fixed ratio between the conduction time and the non-conduction time of the rectifying diode. In another embodiment, the controller also provides a constant voltage control signal. | 2010-09-23 |
20100238690 | METHODS FOR MINIMIZING DOUBLE-FRQUENCY RIPPLE POWER IN SINGLE-PHASE POWER CONDITIONERS - A method is provided for minimizing a double-frequency ripple power exchanged between a load and an energy source, the energy source delivering electrical power to the load through a single-phase power conditioner, and the power conditioner being coupled to an energy storage device. The method senses a first AC signal at an output of the power conditioner and generates a second AC signal at the energy storage device. The second AC signal has a frequency substantially equal to a frequency of the first AC signal and a phase shift of about 45 degrees relative to a phase of the first AC signal. | 2010-09-23 |
20100238691 | AC-TO-DC POWER SUPPLY CIRCUIT - An AC-to-DC power supply circuit has an AC capacitor, a half-wave rectifier, and a filter capacitor. Through the AC capacitor, the half-wave rectifier forms a power supply circuit with an AC power supply for converting AC power to half-wave DC power. The filer circuit further converts the half-wave DC power into low-voltage DC power. The AC-to-DC power supply circuit adjusts the ratio of the AC capacitor and the filter capacitor so that the capacitance ratio matches with the voltage ratio of the half-wave DC power and the lower-voltage DC power. As a consequence, the AC-to-DC power supply circuit does not need to use a large-size transformer and can still effectively convert AC power to low-voltage DC power. This can largely reduce the manufacturing cost. | 2010-09-23 |
20100238692 | RECTIFIER WITH SIC BIPOLAR JUNCTION TRANSISTOR RECTIFYING ELEMENTS - A rectifier circuit can include an input circuit and first and second silicon carbide (SiC) bipolar junction transistors (BJTs). The input circuit is configured to respond to an alternating current (AC) input signal by generating a first pair of opposite polarity AC signals and a second pair of opposite polarity AC signals. The first pair of AC signals has a greater voltage range than the second pair of AC signals. The first and second SiC BJTs each include an input terminal connected to receive a different one of the second pair of opposite polarity AC signals, a base terminal connected to receive a different one of the first pair of opposite polarity AC signals, and an output terminal connected to a rectified signal output node of the rectifier circuit. The input circuit is further configured to control the first and second SiC BJTs through the first and second pairs of opposite polarity AC signals to forward bias the first SiC BJT while reverse biasing the second SiC BJT during a first half cycle of the AC input signal and to reverse bias the second SiC BJT while forward biasing the second SiC BJT during a second half cycle of the AC input signal. | 2010-09-23 |
20100238693 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 2010-09-23 |
20100238694 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is configured to reduce data read time. In the semiconductor storage device, an input/output control circuit is formed along one side of a memory cell array disposed between a data input pad and a data output pad. The input/output control circuit is disposed between a hold command input pad and a clock input pad. Accordingly, it is possible to minimize the distances of the wirings from the input/output control circuit to the pads and to make the distances of the wirings equal and thus to minimize the read time of the memory cell array. In addition, since it is also possible to make equal wiring distances from the input/output control circuit to the address decoder and output multiplexer, it is possible to minimize the read time of the memory cell array. | 2010-09-23 |
20100238695 | MEMORY MODULE INCLUDING MEMORY CHIPS - To provide a module substrate, memory chips mounted on the module substrate, and data input/output wirings that are connected respectively to the memory chips and read data or write data is transmitted thereto. The number of memory chips is equal to the number of bits of read data or write data transmitted through the data input/output wirings at the same time. Because a plurality of data input/output wirings are connected to different memory chips, the load exerted upon each channel can be reduced without using memory buffers. | 2010-09-23 |
20100238696 | MULTI-CHIP PACKAGES INCLUDING EXTRA MEMORY CHIPS TO DEFINE ADDITIONAL LOGICAL PACKAGES AND RELATED DEVICES - A packaged integrated circuit device includes a primary chip stack and a secondary chip stack. The primary chip stack includes memory chips therein that define a logical package addressable by a memory controller. The secondary chip stack includes fewer memory chips than the primary chip stack. The memory chips of the secondary chip stack are configured to be electrically connected to memory chips of at least one external device package to define an additional logical package addressable by the memory controller. For example, the additional logical package may include a same number of memory chips as the primary chip stack. Related devices are also discussed. | 2010-09-23 |
20100238697 | SYSTEMS AND DEVICES INCLUDING LOCAL DATA LINES AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices including local data lines. In some embodiments, the device includes a local data line connected to a plurality of access devices, at least a portion of a capacitor plate connected to the plurality of access devices, and a global data line connected to the local data line by the capacitor plate. | 2010-09-23 |
20100238698 | Data writing and reading method for memory device employing magnetic domain wall movement - A method of data recording and reading for a memory device employing magnetic domain wall movement. The memory device includes a writing track, an interconnecting layer formed on the writing track, and a recording track formed on the interconnecting layer | 2010-09-23 |
20100238699 | SEMICONDUCTOR MEMORY AND TEST METHOD FOR THE SEMICONDUCOR MEMORY - Semiconductor memory contains memory cells having ferroelectric capacitors and cell transistors, bit lines connected to memory cells, word lines connected to gate electrodes of cell transistors, plate lines connected to one of two electrodes of ferroelectric capacitors, sense amplifiers connected between each pair of bit lines. Further, a test pad is provided in order to apply an external voltage to each of bit lines, test transistors are provided corresponding to bit lines respectively, each of test transistors is connected between the test pad and each of bit lines, a fatigue test bias circuit is connected to a first node located between the test pad and test transistors. Test transistors are shared in a first test to apply a first voltage to ferroelectric capacitors from an outside via the test pad and a second test to apply a second voltage to ferroelectric capacitors from the fatigue test bias circuit. | 2010-09-23 |
20100238700 | Quiescent Testing of Non-Volatile Memory Array - A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a column decoder connected to the plurality of unit cells. A test circuitry sends a non-operational test pattern through the array via the row and column decoders with a quiescent supply current to identify defects in the array of memory cells. | 2010-09-23 |
20100238701 | SEMICONDUCTOR MEMORY DEVICE - A memory cell arranged between first and second wirings includes a variable-resistor element. A controller controls a voltage applied between the first and second wirings. The controller performs a first operation that applies a first voltage between the first and second wirings to switch the variable-resistor element from a first state with a resistance value not less than a first resistance value, to a second state with a resistance value not more than a second resistance value smaller than the first resistance value. The second operation applies a second voltage smaller than the first voltage between the first and second wirings to switch the variable-resistor element from the second state to the first state. In the first operation, a verify voltage is applied between the first and second wirings. Based on the obtained signal, a third voltage smaller than the first voltage is applied between the first and second wirings. | 2010-09-23 |
20100238702 | SEMICONDUCTOR MEMORY DEVICE - A memory array includes a memory cell, the memory cell being disposed between a first line and a second line and being configured by a variable resistor and a rectifier connected in series. The variable resistor is a mixture of silicon oxide (SiO2) and a transition metal oxide, a proportion of the transition metal oxide being set to 55˜80%. | 2010-09-23 |
20100238703 | INFORMATION RECORDING/REPRODUCING DEVICE - An information recording/reproducing device includes a first electrode layer, a second electrode layer, a recording layer as a variable resistance between the first and second electrode layer, and a circuit which supplies a voltage to the recording layer to change a resistance of the recording layer. Each of the first and second electrode layers is comprised of IV or III-V semiconductor doped with p-type carrier or n-type carrier. | 2010-09-23 |
20100238704 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF SCREENING THE SAME - A memory cell comprises a variable resistance film; a first conductive film having one surface contacted with one surface of the variable resistance film; and a second conductive film having one surface contacted with another surface of the variable resistance film. A width of the first conductive film or the second conductive film in a direction orthogonal to a direction that a current flows in the first conductive film or the second conductive film is smaller than a width of the variable resistance film in a direction orthogonal to a direction that a current flows in the variable resistance film. The width of the first conductive film and the second conductive film is smaller than a width of the first line and the second line in a direction orthogonal to a direction that a current flows in the first line and the second line. | 2010-09-23 |
20100238705 | NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME - A nonvolatile memory device performs interleaving of data to be stored in each wordline (memory page), or of data to be stored in multiple wordlines (memory pages). The NVM includes a memory cell array, a storage circuit of a de-interleaving circuit, and a read/write circuit. The storage circuit of the de-interleaving circuit is configured to store program data to be written interleaved into the memory cell array. The read/write circuit is configured to control the interleaved/deinterleaved data input/output between the memory cell array and the storage circuit. The write operation unit size may be the same or different from the read operation unit size. The storage circuit stores the program data of integer k times of a common divisor of a read operation unit size and a write operation unit size of the read/write circuit, wherein k may equal ‘m’ (the number of bits stored in each memory cell of the NVM). | 2010-09-23 |
20100238706 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a memory core that includes plural banks, the bank including plural memory cells and a data write circuit that supplies a bias voltage to the memory cell, the memory core being logically divided into plural pages, the page including a predetermined number of memory cells belonging to a predetermined number of banks; and a control circuit that controls the data write circuit to perform page write in each write unit including a predetermined number of memory cells, pieces of data being written in the page in the page write, the control circuit performing the page write by repeating a step including a program operation and a verify operation, the control circuit performing the program operation and the verify operation in a next step or later only to the write unit in which the data write is not completed in the verify operation. | 2010-09-23 |
20100238707 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes memory cells including two transistors connected in parallel between a first node and a connecting node and a variable resistance element whose one end is connected to the connecting node. The first node of each memory cell and a second node, which is the other end of the variable resistance element of the memory cell, are connected to different bit lines. The first node of a one memory cell and the first node of another memory cell which is adjacent on a first side along the second axis to the one memory are connected to the same bit line. The second node of the one memory cell and the second node of still another memory cell which is adjacent on a second side along the second axis to the one memory cell are connected to the same bit line. | 2010-09-23 |
20100238708 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells each provided at individual intersection between a first wiring and a second wiring, the memory cell comprising a variable resistive element, and predetermined numbers of the memory cells shearing the same first wiring to configure a page; a first control circuit configured to select a page subjected to data-writing, and to supply a constant voltage to the first wiring belonging to the selected page; a writing-voltage generating circuit configured to generate plural kinds of writing voltages for programming a resistance of the variable resistive element to one of three or more values based on a write-in data specifying three or more values; and a second control circuit configured to select the page subjected to data-writing, and to supply the writing voltages to predetermined numbers of the respective second wirings belonging to the selected page. | 2010-09-23 |
20100238709 | MEMORY DEVICES INCLUDING DECODERS HAVING DIFFERENT TRANSISTOR CHANNEL DIMENSIONS AND RELATED DEVICES - An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed. | 2010-09-23 |
20100238710 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device, includes: a memory layer having a resistance changeable by performing at least one selected from applying an electric field and providing a current, the storage layer having a first major surface; a plurality of first electrodes provided on the first major surface; a plurality of probe electrodes disposed to face the plurality of first electrodes, the plurality of probe electrodes having a changeable relative positional relationship with the first electrodes; a drive unit connected to the plurality of probe electrodes to record information in the memory layer by causing at least the one selected from the electric field and the current between at least two of the plurality of first electrodes via the plurality of probe electrodes, the electric field having a component parallel to the first major surface, the current flowing in a direction having a component parallel to the first major surface. | 2010-09-23 |
20100238711 | RESISTANCE-CHANGE MEMORY - A resistance-change memory of an aspect of the present invention including a first bit line, second and third bit lines extending in a direction intersecting with the first bit line, first and second word lines, a first select transistor in which a control terminal thereof is connected to the first word line and in which one end of a current path thereof is connected to the second bit line, a second select transistor in which a control terminal thereof is connected to the second word line and in which one end of a current path thereof is connected to the third bit line and in which the end of a current path thereof forms a node together with the other end of the first select transistor, and a resistance-change storage element which has one end connected to the first bit line and the other end connected to the node. | 2010-09-23 |
20100238712 | VARIABLE WRITE AND READ METHODS FOR RESISTIVE RANDOM ACCESS MEMORY - Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell. | 2010-09-23 |
20100238713 | Non-volatile register - A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations. | 2010-09-23 |
20100238714 | VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges. | 2010-09-23 |
20100238715 | VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges. | 2010-09-23 |
20100238716 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE GROUP - A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region. | 2010-09-23 |
20100238717 | MAGNETORESISTIVE DEVICE AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistive device includes: a magnetic recording layer including a first magnetic layer having perpendicular magnetic anisotropy, and a second magnetic layer having in-plane magnetic anisotropy and being exchange-coupled to the first magnetic layer, Curie temperature of the second magnetic layer being lower than Curie temperature of the first magnetic layer, and the magnetic recording layer having a magnetization direction perpendicular to a film plane; a magnetic reference layer having a magnetization direction which is perpendicular to a film plane and is invariable; and a nonmagnetic layer provided between the magnetic recording layer and the magnetic reference layer. The magnetization direction of the magnetic recording layer is changeable by spin-polarized electrons caused by flowing current between the magnetic recording layer and the magnetic reference layer in a direction perpendicular to the film plane. | 2010-09-23 |
20100238718 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate including an active area, a first select transistor in the active area, a first interconnection layer above the semiconductor substrate configured to run in a first direction, a first magnetoresistive element above the first interconnection layer including a fixed layer having a fixed magnetization direction, a nonmagnetic layer on the fixed layer, and a recording layer on the nonmagnetic layer having a variable magnetization direction, the fixed layer being electrically connected to the first interconnection layer, the recording layer being electrically connected to a first diffusion region of the first select transistor, and a second interconnection layer configured to run in the first direction and electrically connected to a second diffusion region of the first select transistor. | 2010-09-23 |
20100238719 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATING METHOD OF THE SAME - A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line. | 2010-09-23 |
20100238720 | Electronic Device, And Method of Operating An Electronic Device - An electronic device ( | 2010-09-23 |
20100238721 | Stuck-At Defect Condition Repair for a Non-Volatile Memory Cell - A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition. | 2010-09-23 |
20100238722 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICES AND VOLTAGE CONTROL CIRCUIT - A memory includes a binary-code setter BCS and the thermometer-code setter TCS, the BCS includes resistance elements with resistance values of R×2 | 2010-09-23 |
20100238723 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell. During writing of information to a plurality of the memory cells connected to an identical word line, the control circuit is configured to apply, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written. | 2010-09-23 |
20100238724 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor memory device includes a memory cell array including a plurality of memory cells, a first data latch circuit, a second data latch circuit, an arithmetic circuit, a counter circuit, and a controller. And controller compares the number (N) counted by the counter circuit with a reference number (M), and performs control to output flag information outside if N≧M. | 2010-09-23 |
20100238725 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF PROGRAMMING DATA THEREIN - Each of the memory cells stores multiple bits of data by way of a threshold voltage distribution having a negative value and representing an erase state, and a plurality of threshold voltage distributions each having a value higher than the threshold voltage distribution representing the erase state and representing a programming state. In a data programming operation, a control circuit applies a certain verify voltage to a control gate of one of the memory cells to be written to obtain a threshold voltage distribution higher than the threshold voltage distribution representing the erase state, thereby confirming the programming state of the memory cells. The control circuit also applies, in a data programming operation, a certain verify voltage to a control gate of one of the memory cells maintained in the erase state, thereby adjusting a lower limit value of the threshold voltage distribution representing the erase state. | 2010-09-23 |
20100238726 | FLASH MEMORY WITH MULTI-BIT READ - A memory device is described that comprises determining which read data state of more than 2 | 2010-09-23 |
20100238727 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory. | 2010-09-23 |
20100238728 | Method and apparatus of operating a non-volatile DRAM - A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully charged. The pass-gate transistor is activated and if the pass-gate transistor is erased it does not turn on and if it is programmed, it turns on. Charge is shared on the complementary pair of pre-charged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in to the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished Gate-induced drain-lowering (GIDL) assisted band-to-band tunneling and Fowler-Nordheim tunneling respectively. Programming or erasing a selected row of cells does not affect the data states of the cells in the unselected rows. | 2010-09-23 |
20100238729 | NON-VOLATILE MEMORY WITH REDUCED LEAKAGE CURRENT FOR UNSELECTED BLOCKS AND METHOD FOR OPERATING SAME - A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block. | 2010-09-23 |
20100238730 | CONTROLLING SELECT GATE VOLTAGE DURING ERASE TO IMPROVE ENDURANCE IN NON-VOLATILE MEMORY - A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates float after being driven at a specific initial level, to reach a specific, optimal final level. In another approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. In another approach, onset of select gate floating is delayed while the p-well voltage ramps up. In another approach, p-well voltage is ramped up in two steps, and the select gates are not floated until the second ramp begins. Floating can be achieved by raising the drive voltage to cut off pass gates of the select gates. | 2010-09-23 |
20100238731 | PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL - A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage. | 2010-09-23 |
20100238732 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state. | 2010-09-23 |
20100238733 | NAND FLASH MEMORY - A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be written and a semiconductor well, and after the write operation and before performing a verification read operation of verifying whether data has been written into the selected memory cell, the control circuit performs a de-trapping operation, in which a first voltage of a same potential as that of the semiconductor well or a same polarity as that of the writing voltage is applied to the control gate of the selected memory cell and in which a second voltage of a same polarity as that of the writing voltage and larger than the first voltage as an absolute value is applied to a control gate of unselected memory cells not to be written. | 2010-09-23 |
20100238734 | SEMICONDUCTOR NON-VOLATILE MEMORY, CHARGE ACCUMULATING METHOD FOR SEMICONDUCTOR NON-VOLATILE MEMORY, CHARGE ACCUMULATING PROGRAM STORAGE MEDIUM - There is provided a semiconductor non-volatile memory including: plural memory sections, a voltage application section, and a control section that controls the voltage application section wherein the control section controlling voltage application such that, based on a value of current detected by a current detection section, in a region where the current flowing in a channel region is greater than a predetermined target value at which a amount of charge accumulated has become a specific value in at least one of a first charge accumulating section or a second charge accumulating section, when a value of current flowing in the channel region approaches a target value, a rate of increase in the charge accumulating amount per time is decreased at least once. | 2010-09-23 |
20100238735 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably. | 2010-09-23 |
20100238736 | Semiconductor storage device - 1. A semiconductor storage device has a first MOS transistor connected at a first end thereof to a power supply and diode-connected; a second MOS transistor connected in parallel with the first MOS transistor; a memory cell connected between the second end of the first MOS transistor and ground, the memory cell capable of adjusting a current flowing through the memory cell; a third MOS transistor connected at a first end thereof to the power supply, and diode-connected; a fourth MOS transistor connected in parallel with the third MOS transistor; a fifth MOS transistor connected between the second end of the fourth MOS transistor and the ground and supplied at a gate thereof with the first reference voltage; and an amplifier circuit which compares the sense voltage with the comparison voltage, and which outputs a comparison result signal depending upon a result of the comparison. | 2010-09-23 |
20100238737 | BIT LINE SELECT VOLTAGE GENERATOR AND NONVOLATILE MEMORY DEVICE USING THE SAME - A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, wherein the second voltage is lower than the first voltage. The second voltage generator operates to change the first voltage according to change of temperatures thereby generating a third voltage. The voltage transmission unit operates to transmit the second voltage or the third voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal. | 2010-09-23 |
20100238738 | EEPROM Having Single Gate Structure and Method of Operating the Same - An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap. | 2010-09-23 |
20100238739 | NOR FLASH MEMORY DEVICE AND RELATED METHODS OF OPERATION - A NOR flash memory device is programmed by selecting one of a plurality of global bit lines and sequentially selecting a plurality of local bit lines commonly connected with the selected global bit line to supply a program voltage to memory cells. | 2010-09-23 |
20100238740 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1 | 2010-09-23 |
20100238741 | SEMICONDUCTOR DEVICE AND WRITE CONTROL METHOD FOR SEMICONDUCTOR DEVICE - To include a memory cell array that stores therein data in a reversible manner, an antifuse circuit that stores therein data in a nonvolatile manner, a sense amplifier array that temporarily holds data that is read from the memory cell array of data to be written in the memory cell array, and a control circuit that performs a control for writing the data held in the sense amplifier array in the antifuse circuit. According to the present invention, it is not required to provide any dedicated latch circuit for each antifuse element. Therefore, a writing process of writing data in the antifuse circuit can be performed at high speed without causing an increase of the chip dimension due to a dedicated latch circuit. | 2010-09-23 |
20100238742 | APPARATUS AND METHOD FOR OUTPUTTING DATA OF SEMICONDUCTOR MEMORY APPARATUS - An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately whit a change in the system, which enables the applied range of the products to be extended. | 2010-09-23 |
20100238743 | FAST EMBEDDED BiCMOS-THYRISTOR LATCH-UP NONVOLATILE MEMORY - This disclosure describes a new semiconductor non-volatile memory that can be potentially faster than DRAM and FLASH, and the manufacturing cost can be lower than SRAM, which is volatile. It is possible to fabricate an ULSI microprocessor and this type of new memory array in the same chip—realizing the “embedded” process. There are a CMOS transistor and latched-up Bipolar transistors (A thyristor) in the device. The fast read, write and erase operations are done by charging the MOS gate capacitor interface and sensing the latch-up voltage of the thyristor. The latch-up voltage of the thyristor is reduced for the additional MOSFET current during the write process, causing early avalanche breakdown and the latch-up of the bipolar transistors. The semiconductor memory can be fabricated as a planar device or a vertical device. | 2010-09-23 |
20100238744 | Semiconductor stroage device - A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BL | 2010-09-23 |
20100238745 | Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 2010-09-23 |
20100238746 | READING CIRCUITRY IN MEMORY - A reading circuit in a memory, having a first memory cell coupled to a first bit line and a second bit line, a second memory cell coupled to the second bit line and a third bit line and a third memory cell coupled to the third bit line and a fourth bit line, is provided. The reading circuitry includes a sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line to the drain side bias circuit to receive the drain side bias in a read operation mode. The second selection circuit connects the first bit line and the fourth bit line to the sensing circuit in the read operation mode, so that the sensing circuit senses a current of the first memory cell. | 2010-09-23 |
20100238747 | Method and Circuit of Calibrating Data Strobe Signal in Memory Controller - A method for calibrating a data strobe (DQS) signal and associated circuit is provided. The calibrating method includes determining N buffers from a delay chain having M buffers to delay a predetermined phase during a first period; serially connecting the N buffers of the delay chain during a second period; and inputting the DQS signal to the N serially connected buffers to delay the DQS signal by the predetermined phase. | 2010-09-23 |
20100238748 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the delayed reference signal to output a signal for determining a timing of a predetermined operation on a bank selected by the delayed bank address. | 2010-09-23 |
20100238749 | SEMICONDUCTOR STORAGE DEVICE - After a bit line is pre-charged by a pre-charge circuit that pre-charges the bit line, the voltage of a power supply for actuating a sense amplifier, which amplifies a signal read out from a memory cell, is switched. | 2010-09-23 |
20100238750 | CONTROL OF INPUTS TO A MEMORY DEVICE - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 2010-09-23 |
20100238751 | Method and Apparatus for Increasing Yield in a Memory Device - An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level. | 2010-09-23 |
20100238752 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first region configured to operate at a specified first voltage, a second region configured to operate at a varying second voltage, and a memory device formed between the first region and the second region so as to straddle the first and second regions, wherein the memory device comprises a first port driven at the first voltage to transmit an output signal to and receive an input signal from the first region, a second port driven at the second voltage to transmit an output signal to and receive an input signal from the second region, and a memory cell accessed by the first and second ports. | 2010-09-23 |
20100238753 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage. | 2010-09-23 |
20100238754 | CLOCK AND POWER FAULT DETECTION FOR MEMORY MODULES - A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module. | 2010-09-23 |
20100238755 | SEMICONDUCTOR MEMORY DEVICE HAVING POWER SAVING MODE - A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit receives a clock signal, a chip select signal and a mode signal, and generates the internal clock signal. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal when the mode signal transitions from a power saving mode to a normal mode. | 2010-09-23 |
20100238756 | Self Reset Clock Buffer In Memory Devices - A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal. | 2010-09-23 |
20100238757 | Apparatus, System, and Method for Adding a Liquid in a Mixing Process - An apparatus, system, and method are disclosed for adding a liquid in a mixing process. The apparatus in the described embodiments includes a liquid inlet, a continuous flow heater, a holding tank, a support structure, and a metering device. The continuous flow heater is coupled to the liquid inlet. The holding tank is adapted to be coupled to the continuous flow heater and to receive heated liquid from the continuous flow heater. The support structure is configured to support the holding tank at a height greater than approximately four feet above a ground level. The metering device is coupled to the holding tank and has an indicator for identifying an amount of liquid dispensed from the holding tank. | 2010-09-23 |
20100238758 | MIXING APPARATUS - A mixing apparatus, such as a mobile concrete mixer, has a frame ( | 2010-09-23 |
20100238759 | DEVICE AND METHOD FOR PROCESSING OF POLYMER MATERIALS - A device for processing a polymer material including a first screw having a first length; and a second screw having a second length different from the first length, wherein the first screw is configured to be rotated at one of a direction and a speed of rotation that is independent from a respective speed or rotation of the second screw. | 2010-09-23 |
20100238760 | CONSTANT LOAD SHEAR CELL FOR MAGNETORHEOLOGICAL FLUIDS - The invention relates to a constant load shear cell and a method for constant loading of a magnetorheological fluid in a constant load shear cell. The constant load shear cell comprises a rotatable shaft ( | 2010-09-23 |