38th week of 2014 patent applcation highlights part 52 |
Patent application number | Title | Published |
20140264361 | III-NITRIDE TRANSISTOR WITH ENGINEERED SUBSTRATE - A transistor includes a buffer layer, a channel layer over the buffer layer, a barrier layer over the channel layer, a source electrode electrically connected to the channel layer, a drain electrode electrically connected to the channel layer, a gate electrode on the barrier layer between the source electrode and the drain electrode, a backside metal layer, a substrate between a first portion of the buffer layer and the backside metal layer; and a dielectric between a second portion of the buffer layer and the backside metal layer. | 2014-09-18 |
20140264362 | Method and Apparatus for Forming a CMOS Device - A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions. | 2014-09-18 |
20140264363 | Oxygen Controlled PVD Aluminum Nitride Buffer for Gallium Nitride-Based Optoelectronic and Electronic Devices - Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer. | 2014-09-18 |
20140264364 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer, a first insulation layer formed on the second semiconductor layer, the first insulation layer being formed of a material that includes SiO | 2014-09-18 |
20140264365 | Rectifier Structures with Low Leakage - An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier. | 2014-09-18 |
20140264366 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor apparatus includes a semiconductor substrate that has a diameter of 2 inches or larger, and an N-type semiconductor layer that is stacked on the semiconductor substrate using a material including gallium nitride (GaN). A median of a plurality of measured values of the concentration of carbon (C) at a plurality of locations on a face of a region of the N-type semiconductor layer is equal to or lower than 1.0×10 | 2014-09-18 |
20140264367 | HEMT Semiconductor Device and a Process of Forming the Same - A HEMT semiconductor device can include a dielectric layer that includes a silicon nitride film and an AlN film. In an embodiment, the HEMT semiconductor device can include a GaN film and an AlGaN film. In a process of forming the HEMT device, the AlN can provide an etch stop when forming an opening for a gate electrode. | 2014-09-18 |
20140264368 | Semiconductor Wafer and a Process of Forming the Same - A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate. | 2014-09-18 |
20140264369 | HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device. | 2014-09-18 |
20140264370 | CARBON DOPING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×10 | 2014-09-18 |
20140264371 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 2014-09-18 |
20140264372 | STRUCTURE AND MANUFACTURING METHOD OF THE STRUCTURE, AND GALLIUM NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE USING THE STRUCTURE AND MANUFACTURING METHOD OF THE DEVICE - In a structure including a gallium nitride-based semiconductor having an m-plane as a principal plane, and a metal layer provided on the principal plane, the principal plane has an n-type conductivity. An interface between the gallium nitride-based semiconductor and the metal layer contains oxygen. The metal layer includes a crystal grain extending form a lower surface to an upper surface of the metal layer. | 2014-09-18 |
20140264373 | III-Nitride Heterojunction Device - A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. | 2014-09-18 |
20140264374 | METHOD FOR MANUFACTURING A SILICON CARBIDE SUBSTRATE FOR AN ELECTRICAL SILICON CARBIDE DEVICE, A SILICON CARBIDE SUBSTRATE AND AN ELECTRICAL SILICON CARBIDE DEVICE - A method for manufacturing a silicon carbide substrate for an electrical silicon carbide device includes providing a silicon carbide dispenser wafer including a silicon face and a carbon face and depositing a silicon carbide epitaxial layer on the silicon face. Further, the method includes implanting ions with a predefined energy characteristic forming an implant zone within the epitaxial layer, so that the ions are implanted with an average depth within the epitaxial layer corresponding to a designated thickness of an epitaxial layer of the silicon carbide substrate to be manufactured. Furthermore, the method comprises bonding an acceptor wafer onto the epitaxial layer so that the epitaxial layer is arranged between the dispenser wafer and the acceptor wafer. Further, the epitaxial layer is split along the implant zone so that a silicon carbide substrate represented by the acceptor wafer with an epitaxial layer with the designated thickness is obtained. | 2014-09-18 |
20140264375 | LATTICE MISMATCHED HETEROJUNCTION STRUCTURES AND DEVICES MADE THEREFROM - Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material. Also provided are devices incorporating the heterojunction structures, methods of making the devices and method of using the devices. | 2014-09-18 |
20140264376 | Power Switching Module with Reduced Oscillation and Method for Manufacturing a Power Switching Module Circuit - A power switching module includes a three-terminal power semiconductor device designed for a rated current and a freewheeling unit. The freewheeling unit includes a pn-diode integrated in a first semiconductor material having a first band-gap, and a Schottky-diode integrated in a second semiconductor material having a second band-gap that is larger than the first band-gap. The Schottky-diode is electrically connected in parallel to the pn-diode. | 2014-09-18 |
20140264377 | SOL-GEL PROCESS FOR THE MANUFACTURE OF HIGH POWER SWITCHES - According to one embodiment, a photoconductive semiconductor switch includes a structure of nanopowder of a high band gap material, where the nanopowder is optically transparent, and where the nanopowder has a physical characteristic of formation from a sol-gel process. According to another embodiment, a method includes mixing a sol-gel precursor compound, a hydroxy benzene and an aldehyde in a solvent thereby creating a mixture, causing the mixture to gel thereby forming a wet gel, drying the wet gel to form a nanopowder, and applying a thermal treatment to form a SiC nanopowder. | 2014-09-18 |
20140264378 | SEMICONDUCTOR STRUCTURE - A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction. | 2014-09-18 |
20140264379 | III-Nitride P-Channel Field Effect Transistor with Hole Carriers in the Channel - A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal. | 2014-09-18 |
20140264380 | Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material - A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET. | 2014-09-18 |
20140264381 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED OHMIC CONTACTS - A method of fabricating a semiconductor device includes providing one or more semiconductor layers, providing a gate contact on a first surface of the one or more semiconductor layers, then using the gate contact as a mask to deposit a source contact and a drain contact on the first surface of the one or more semiconductor layers, such that the source contact and the drain contact include an interior edge that is laterally aligned with a different lateral edge of the gate contact. | 2014-09-18 |
20140264382 | SILICON CARBIDE SEMICONDUCTOR DEVICES - Methods, systems, and devices are disclosed for thermal processing of silicon carbide semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen and phosphorous co-doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen and phosphorous co-doped SiC epitaxial layer, in which the thermally growing the oxide layer results in at least partially consuming the nitrogen and phosphorous co-doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen and phosphorous between the SiC epitaxial layer and the oxide layer. | 2014-09-18 |
20140264383 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a die pad, an SiC chip mounted on the die pad, a porous first sintered Ag layer bonding the die pad and the SiC chip, and a reinforcing resin portion covering a surface of the first sintered Ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the SiC chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the SiC chip, the first sintered Ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the SiC chip. | 2014-09-18 |
20140264384 | SiC SUBSTRATE WITH SiC EPITAXIAL FILM - A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec. | 2014-09-18 |
20140264385 | Manufacture of wafers of wide energy gap semiconductor material for the integration of electronic and/or optical and/or optoelectronic devices - A method is provided for fabricating a wafer of semiconductor material intended for use for the integration of electronic and/or optical and/or optoelectronic devices. The method comprises: providing a starting wafer of crystalline silicon ( | 2014-09-18 |
20140264386 | PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL - A semiconductor device includes a first transistor having first drain and source regions and a first channel region and a second transistor having second drain and source regions and a second channel region. A first silicon/carbon alloy material is embedded in the first drain and source regions, the first silicon/carbon alloy material inducing a first strain component along a first channel length direction of the first channel region. A second silicon/carbon alloy material is embedded in the second drain and source regions, the second silicon/carbon alloy material inducing a second strain component along a second channel length direction of the second channel region, wherein the second strain component is of an opposite type of the first strain component. | 2014-09-18 |
20140264387 | FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS - A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material. | 2014-09-18 |
20140264388 | LOW CARBON GROUP-III NITRIDE CRYSTALS - The present disclosure generally relates to systems and methods for producing and using Group-III nitride crystals that have enhanced or increase ultraviolet transparency in a range of wavelengths. The crystals may also be used in a number of UV optics and UV optical semiconductor devices. | 2014-09-18 |
20140264389 | LIGHT EMITTING DIODE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) structure including a substrate, a polymer layer, and an epitaxy layer is provided. The polymer layer is disposed on the substrate, wherein the polymer layer has a chemical formula of: | 2014-09-18 |
20140264390 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of fabricating an epitaxial device, comprising: providing a substrate having a first surface and a normal direction; epitaxially forming a first transition layer in a first temperature on the first surface of the substrate and in-situ incorporating a porogen into the first transition layer; and adjusting the first temperature to a second temperature to burn out the porogen from the first transition layer to form a hollow component inside the first transition layer. | 2014-09-18 |
20140264391 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film. | 2014-09-18 |
20140264392 | LIGHT-RECEIVING AND EMITTING DEVICE INCLUDING INTEGRATED LIGHT-RECEIVING AND EMITTING ELEMENT AND SENSOR - The light receiving/emitting device uses an integrated light receiving/emitting element wherein a light receiving element and a light emitting element are provided on one main surface of a substrate. The substrate comprises a first-conductivity-type semiconductor. At least one electrode layer is placed in an area corresponding to at least the light receiving element and the light emitting element on the other main surface of the substrate. The light receiving element comprises: a first second-conductivity-type semiconductor layer formed on the one main surface of the substrate; a first anode electrode formed on the top surface of the first second-conductivity-type semiconductor layer; and a first cathode electrode formed on the top surface of the one main surface of the substrate. The electrode layer, the first anode electrode and the first cathode electrode have the same electric potential. | 2014-09-18 |
20140264393 | LIGHT ENGINE - A light engine with a heat sink having a curved recessed cavity that receives a flexed or cupped PCB bearing a plurality of LEDs. Once situated within the cavity and released, the PCB has a tendency to return to its flat state, but flanges or other suitable mechanisms at the ends of the cavity restrain the edges of the PCB and prevent the PCB from returning to its flat state. In this way, the PCB is securely retained within and biased against the cavity by its own forces. As the PCB heats, the PCB expands, further biasing the PCB against the cavity of the heat sink and increasing the thermal conductivity between the two components. | 2014-09-18 |
20140264394 | LIGHT EMITTING DIODE - A light emitting diode with a front surface adapted to emit light and a rear surface is provided with a reflective coating on the rear surface, the reflective coating being primarily silver and containing either 0.4% bismuth or a combination of 0.5% tin, 0.2% copper, and 0.2% samarium. | 2014-09-18 |
20140264395 | LIGHT EMITTING MODULE - Disclosed is a light emitting module. The light emitting module includes a substrate and a plurality of light emitting devices disposed on the substrate, at least one of the plurality of light emitting devices includes a plurality of light emitting cells which are individually driven, and the plurality of light emitting cells include a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer, and has a light emitting surface emitting light. | 2014-09-18 |
20140264396 | ULTRA-THIN PRINTED LED LAYER REMOVED FROM SUBSTRATE - Ultra-thin flexible LED lamp layers are formed over a release layer on a substrate. The LED lamp layers include a first conductor layer overlying the release layer, an array of vertical light emitting diodes (VLEDs) printed over the first conductor layer, where the VLEDs have a bottom electrode electrically contacting the first conductor layer, and a second conductor layer overlying the VLEDs and contacting a top electrode of the VLEDs. Other layers may be formed, such as protective layers, reflective layers, and phosphor layers. The LED lamp layers are then peeled off the substrate, wherein the release layer provides a weak adherence between the substrate and the LED lamp layers to allow the LED lamp layers to be separated from the substrate without damage. The resulting LED lamp layers are extremely flexible, enabling the LED lamp layers to be adhered to flexible target surfaces including clothing. | 2014-09-18 |
20140264397 | CERAMIC BASED LIGHT EMITTING DIODE (LED) DEVICES AND METHODS - Light emitter devices, such as light emitting diode (LED) devices and related methods are disclosed. A light emitter device includes a ceramic based substrate, at least one LED chip disposed on the substrate, and a filling material. The ceramic substrate can include one or more surface features. The filling material can be disposed over and/or within a portion of the one or more surface features. Surface features can include one or more pedestals, trenches, holes, indentions, depressions, waves, and/or convexly or concavely curved surfaces. Surface features can improve optics of the LED device, for example, improving brightness, reflection, and/or light extraction associated with the device. Related methods are disclosed. | 2014-09-18 |
20140264398 | Light Emitting Unit, Light Emitting Device, and Lighting Device - The light-emitting unit has at least a first light-emitting element, a second light-emitting element, and a separation layer. The separation layer has a leg portion and a stage portion which protrudes outside of a bottom surface of the leg portion over the leg portion. An upper electrode of the first light-emitting element is electrically connected to a lower electrode of the second light-emitting element in a region where the upper electrode and the lower electrode overlap with the stage portion of the separation layer. By providing the separation layer, the light-emitting unit can be formed without using a metal mask. The upper electrode can be a composite material including an organic compound and a metal oxide or a stacked layer of the composite material and a metal material or a light-transmitting conductive material. | 2014-09-18 |
20140264399 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURE - A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of the receptacle on the elastomeric encapsulant. | 2014-09-18 |
20140264400 | INTEGRATED MULTI-CHIP MODULE OPTICAL INTERCONNECT PLATFORM - Techniques, systems, and devices are disclosed to provide multilayer platforms for integrating semiconductor integrated circuit dies, optical waveguides and photonic devices to provide intra-die or inter-die optical connectivity. For example, an integrated semiconductor device having integrated circuits respectively formed on different semiconductor integrated circuit dies is provided to include a carrier substrate structured to form openings on a top side of the carrier substrate; semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate, each semiconductor integrated circuit die including a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die being structured to have a top surface substantially coplanar with the top side of the carrier substrate; and planar layers formed on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide (1) intra-die optical connectivity for photonic devices associated with a semiconductor integrated circuit die, or (2) inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies. | 2014-09-18 |
20140264401 | FLEXIBLE LIGHTING DEVICE - A flexible lighting element is provided, comprising: a first flexible substrate; first and second conductive elements located on the first flexible substrate; a light-emitting element having a positive contact and a negative contact, the positive and negative contacts both being on a first side of the light-emitting element, the light-emitting element being configured to emit light having a selected narrow range of wavelengths; a first conductive connector electrically connecting the first conductive element to the positive contact; a second conductive connector electrically connecting the second conductive element to the negative contact; a second flexible substrate located adjacent to a second surface of the light-emitting element; and an affixing layer located between the first flexible substrate and the second flexible substrate. | 2014-09-18 |
20140264402 | PHOSPHORS FOR WARM WHITE EMITTERS - A method for fabricating light-emitting devices includes obtaining a plurality of light-emitting diode (LED) chips fabricated to emit blue light and preparing a phosphor-containing material comprising a matrix material having dispersed therein a mixture of a red phosphor and a green phosphor in a fixed ratio to each other. The method also includes disposing different thicknesses of the phosphor-containing material on different ones of the LED chips. The fixed ratio is chosen such that LED chips having different thicknesses of the phosphor-containing material emit light characterized by different points along the Planckian locus in a CIE chromaticity diagram. | 2014-09-18 |
20140264403 | LIGHT-EMITTING MODULE AND METHOD OF MANUFACTURING A SINGLE LIGHT-EMITTING STRUCTURE THEREOF - The instant disclosure provides a light-emitting module and a method of manufacturing a single light-emitting structure. The light-emitting module includes two identical light-emitting structures disposed on the same plane. One of the two light-emitting structures disposed on the plane is rotated by 180 degrees relative to the other light-emitting structure, and the two light-emitting structures are connected to each other. Each light-emitting structure includes a base, a conducting element, a light-emitting element and an encapsulation element. The conducting element includes a plurality of conductors separated from each other and passing through the base body, where the number of the conductors is N and N>1. The light-emitting element includes at least one light-emitting chip electrically connected between at least two of the conductors. The encapsulation element includes a transparent encapsulation body disposed on the base to cover the conducting element and the light-emitting element. | 2014-09-18 |
20140264404 | ENGINEERED-PHOSPHOR LED PACKAGES AND RELATED METHODS - In accordance with certain embodiments, a phosphor element at least partially surrounding a light-emitting die is shaped to influence color-temperature divergence. | 2014-09-18 |
20140264405 | VOLUMETRIC THREE-DIMENSIONAL DISPLAY WITH EVENLY-SPACED ELEMENTS - A volumetric three-dimensional light-emitting display, comprising an array of emitters arranged, as defined by the relative positions of the emitters' centerpoints, in a close-packed relationship; and an array of conductors in electrical contact with the array of emitters. The array of emitters may for example comprise conventional RGB stacks or similar full-color assemblages or four different-colored emitters. | 2014-09-18 |
20140264406 | LED MODULE - The invention relates to a light-emitting diode arrangement having the following: a preferably heat-conductive substrate ( | 2014-09-18 |
20140264407 | STRESS RELIEF FOR ARRAY-BASED ELECTRONIC DEVICES - In accordance with certain embodiments, an electric device includes a flexible substrate having first and second conductive traces on a first surface thereof and separated by a gap therebetween, an electronic component spanning the gap, and a stiffener configured to substantially prevent flexing of the substrate proximate the gap during flexing of the substrate. | 2014-09-18 |
20140264408 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 2014-09-18 |
20140264409 | ENGINEERED-PHOSPHOR LED PACKAGES AND RELATED METHODS - In accordance with certain embodiments, a phosphor element at least partially surrounding a light-emitting die is shaped to influence color-temperature divergence. | 2014-09-18 |
20140264410 | LED with IC Integrated Lighting Module - The present disclosure involves a method of packaging light-emitting diodes (LEDs). A carrier having a first side and a second opposite the first side is provided. The carrier includes a plurality of conductive interconnect elements. An integrated circuit (IC) die is bonded to the first side of the carrier. A packaging material having light-reflective properties is molded over the first and second sides of the carrier such that the IC die is sealed by the packaging material. A portion of the packaging material is molded into a reflective cap structure. A light-emitting diode (LED) is bonded to the second side of the carrier. Sidewalls of the reflective cap structure circumferentially surround the LED. The LED and the IC die are electrically coupled together through the conductive interconnect elements in the carrier. A lens is then formed over the LED. | 2014-09-18 |
20140264411 | LIGHT EMITTING DEVICE - This disclosure discloses a light-emitting chip comprises: a light-emitting stack, having a side wall, comprising an active layer emitting light; and a light-absorbing layer having a first portion surrounding the side wall and being configured to absorb 50% light toward the light-absorbing layer. | 2014-09-18 |
20140264412 | SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - A semiconductor light emitting device package includes: a light emitting device; a wavelength conversion unit formed in a path of light emitted from the light emitting device and including a mixture of a wavelength conversion material and a glass material; and a reflective film disposed on an upper surface of the wavelength conversion unit and reflecting a partial amount of light emitted from the light emitting device and allowing a partial amount of light emitted from the light emitting device to be transmitted therethrough. | 2014-09-18 |
20140264413 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes a stacked body, a first metal layer, and a second metal layer. The stacked body includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The second semiconductor layer is separated from the first semiconductor layer in a first direction. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first metal layer is stacked with the stacked body in the first direction to be electrically connected to one selected from the first semiconductor layer and the second semiconductor layer. The first metal layer has a side surface extending in the first direction. The second metal layer covers at least a portion of the side surface of the first metal layer. A reflectance of the second metal layer is higher than a reflectance of the first metal layer. | 2014-09-18 |
20140264414 | PHOSPHOR, LIGHT-EMITTING DEVICE AND METHOD FOR PRODUCING THE PHOSPHOR - The present disclosure provides a phosphor excellent in temperature characteristic and capable of highly efficiently emitting yellow light with a wide half-width in the emission spectrum. This phosphor emits luminescence with a peak wavelength of 500 to 600 nm under excitation by light with a peak wavelength of 250 to 500 nm, and is represented by the following formula (1): | 2014-09-18 |
20140264415 | Group III Nitride Semiconductor Light-Emitting Device and Method for Producing the Same - The present invention provides a Group III nitride semiconductor light-emitting device in which a flat semiconductor layer is grown on a sapphire substrate provided with an uneven shape, and a method for producing the same. When the area ratio R of the flat surface area S on the main surface to the total area K of the sapphire substrate is 0.1 or more to less than 0.5, in formation of the semiconductor layer on the sapphire substrate having an uneven shape on the main surface thereof, at least two types of gases: a raw material gas containing a Group III element and a raw material gas containing Group V element are supplied so as to satisfy the equation 1,000≦Y/(2×R)≦1,200. In the equation, Y is the partial pressure ratio of the raw material gas containing Group V element to the raw material gas containing Group III element. | 2014-09-18 |
20140264416 | Organic Light Emitting Diode With Light Extracting Layer - A light extraction substrate includes a glass substrate having a first surface and a second surface. A light extraction layer is formed on at least one of the surfaces. The light extraction layer is a coating, such as a silicon-containing coating, incorporating nanoparticles. | 2014-09-18 |
20140264417 | WIRING BOARD AND LIGHT EMITTING DEVICE - There is provided a wiring board for mounting a light emitting element thereon. The wiring board includes: an insulating layer; a wiring pattern on the insulating layer; a reflecting layer on the insulating layer to cover the wiring pattern, wherein the light emitting element is to be mounted on a surface of the reflecting layer; and a silica film on the surface of the reflecting layer. | 2014-09-18 |
20140264418 | COLOR STABLE RED-EMITTING PHOSPHORS - A process for synthesizing a color stable Mn | 2014-09-18 |
20140264419 | PHOSPHOR FILM, AND LIGHT EMITTING DEVICE AND SYSTEM USING THE SAME - Phosphor film, and light emitting device and system using the same are provided. The light emitting device comprises a package body, a light emitting element disposed on the package body to generate first light, one or more first quantum dot phosphor layers formed above the light emitting element to perform wavelength conversion of the first light and generate second light, and one or more second quantum dot phosphor layers formed above the light emitting element so as not to overlap with the first quantum dot phosphor layers to perform wavelength conversion of the first light and generate third light different from the second light. | 2014-09-18 |
20140264420 | PHOTOLUMINESCENCE WAVELENGTH CONVERSION COMPONENTS - A photoluminescence wavelength conversion component comprises a first portion having at least one photoluminescence material; and a second portion comprising light reflective material, wherein the first portion is integrated with the second portion to form the photoluminescence wavelength conversion component. | 2014-09-18 |
20140264421 | LIGHT EMITTING DEVICE - A light emitting device including a light emitting structure having a first semiconductor layer, a second semiconductor layer, and an active layer between the first and second semiconductor layers; a first electrode electrically connected to the first semiconductor layer; and a second electrode disposed on the second semiconductor layer. Further, the second electrode include a reflective layer disposed on the second semiconductor layer; a metal layer disposed on a side surface of the reflective layer and on a top surface of reflective layer; a first anti-oxidation layer on the metal layer; and a second anti-oxidation layer on the first anti-oxidation layer. In addition, the second anti-oxidation layer is more than 10 times thicker than the first anti-oxidation layer. | 2014-09-18 |
20140264422 | Optoelectronic Semiconductor Component and Conversion Element - In at least one embodiment, an optoelectronic semiconductor component includes an optoelectronic semiconductor chip. The semiconductor component includes a conversion element that is arranged to convert at least some radiation emitted by the semiconductor chip into radiation of a different wavelength. The conversion element comprises at least one luminescent substance and scattering particles and also at least one matrix material. The scattering particles are embedded in the matrix material. A difference in the refractive index between the matrix material and a material of the scattering particles at a temperature of 300 K is at the most 0.15. The difference in the refractive index between the matrix material and the material of the scattering particles at a temperature of 380 K is greater than at a temperature of 300 K. | 2014-09-18 |
20140264423 | FLEXIBLE LIGHTING DEVICE INCLUDING A PROTECTIVE CONFORMAL COATING - A lighting element is provided, comprising: a substrate; first and second conductive elements located on the substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the light-emitting element emitting light from a second surface opposite the first surface; a first conductive connector located between the first conductive element and the first contact, electrically connecting the first conductive element to the first contact; a second conductive connector located between the second conductive element and the second contact, to electrically connecting the second conductive element to the second contact; a first protective conformal coating located adjacent to the second surface; and an affixing layer located between the flexible substrate and the first protective conformal coating, the affixing layer affixing the first protective conformal coating to the flexible substrate, wherein the first protective conformal coating is substantially transparent to light. | 2014-09-18 |
20140264424 | FLEXIBLE LIGHTING DEVICE INCLUDING A HEAT-SPREADING LAYER - A lighting element, comprising: a first substrate; a first and second conductive elements located on the first substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the first contact being electrically connected to the first conductive element, the second contact being electrically connected to the second conductive element, and the light-emitting element emitting light from a second surface opposite the first surface; a top layer adjacent to the second surface; and an affixing layer located between the first substrate and the top layer, the affixing layer affixing the top layer to the first substrate; and a heat spreading layer having a third surface and a fourth surface opposite the third surface, the heat spreading layer being affixed beneath the first flexible substrate at the third surface, wherein the flexible top layer is substantially transparent to light. | 2014-09-18 |
20140264425 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer. | 2014-09-18 |
20140264426 | LIGHT EMITTING DEVICE MOUNT, LIGHT EMITTING APPARATUS INCLUDING THE SAME, AND LEADFRAME - A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point. | 2014-09-18 |
20140264427 | THERMAL MANAGEMENT IN ELECTRONIC DEVICES WITH YIELDING SUBSTRATES - In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation. | 2014-09-18 |
20140264428 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a body, a first electrode installed in the body and a second electrode separated from the first electrode, a light emitting chip formed on one of the first and second electrodes, and electrically connected to the first and second electrodes, and a protective cap projecting between the first and second electrodes. | 2014-09-18 |
20140264429 | Composite Substrates and Functional Devices - Protrusions | 2014-09-18 |
20140264430 | P-CONTACT WITH MORE UNIFORM INJECTION AND LOWER OPTICAL LOSS - The current distribution across the p-layer ( | 2014-09-18 |
20140264431 | ENHANCEMENT-MODE III-NITRIDE DEVICES - A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact. | 2014-09-18 |
20140264432 | Semiconductor Device - A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center. | 2014-09-18 |
20140264433 | DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD - A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate. | 2014-09-18 |
20140264434 | MONOLITHIC IGNITION INSULATED-GATE BIPOLAR TRANSISTOR - In a general aspect, an apparatus can include an insulated-gate bipolar transistor (IGBT) device disposed in a semiconductor region. The apparatus can further include a plurality of clamping diodes. The plurality of clamping diodes can be coupled in series between a collector terminal of the IGBT device and a gate terminal of the IGBT device. The apparatus can also include a gate pad disposed over at least a portion of the plurality of clamping diodes. The at least a portion of the plurality of clamping diodes can be configured, during operation of the apparatus, to have a voltage of at least 120 V applied across them. | 2014-09-18 |
20140264435 | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor module includes: a first circuit component: a second circuit component; and a third circuit component. The first circuit component includes: an insulating first substrate; a first conductive layer; a first switching element; and a first diode. The second circuit component includes: an insulating second substrate; a second conductive layer; a second switching element; and a second diode. The second circuit component is disposed between the first circuit component and the third circuit component. The third circuit component includes: an insulating third substrate; a third conductive layer provided on the third substrate and including a third element mounting unit; a third switching element provided on the third element mounting unit; and a third diode provided on the third element mounting unit. A direction from the third switching element toward the third diode is an opposite direction to the first direction. | 2014-09-18 |
20140264436 | SOLUTION PROCESSED NEUTRON DETECTOR - A low-cost neutron detector is formed on a substrate includes a sensor formed by an active material layer sandwiched between two electrodes, and a neutron capture layer formed in close proximity to (i.e., over and/or under) the sensor. The sensor active material layer includes a bulk heterojunction or bilayer structure that is formed by depositing particulate solutions incorporating at least one type of high atomic number nanoparticle using low-temperature (i.e., below 400° C.) solution processing techniques. The sensor electrode material and neutron capture material are similarly disposed in associated solutions (e.g., conductive inks) that are also deposited using low-temperature solution processing techniques, whereby the fabrication process can be carried out on low-cost flexible substrate material (e.g., PET) using high efficiency roll-to-roll production techniques. The neutron capture material is optionally patterned as an array of pillars, and the active layer materials are backfilled between the pillars. | 2014-09-18 |
20140264437 | EPITAXIAL STRUCTURE FOR VERTICALLY INTEGRATED CHARGE TRANSFER GATE TECHNOLOGY IN OPTOELECTRONIC MATERIALS - A low noise infrared photo detector with a vertically integrated field effect transistor (FET) structure is formed without thermal diffusion. The FET structure includes a high sensitivity photo detector layer, a charge well layer, a transfer well layer, a charge transfer gate, and a drain electrode. In an embodiment, the photo detector layer and charge well are InGaAs and the other layers are InP layers. | 2014-09-18 |
20140264438 | Heterostructures for Semiconductor Devices and Methods of Forming the Same - Various heterostructures and methods of forming heterostructures are disclosed. A structure includes a substrate, a template layer, a barrier layer, and a device layer. The substrate comprises a first crystalline material. The template layer comprises a second crystalline material, and the second crystalline material is lattice mismatched to the first crystalline material. The template layer is over and adjoins the first crystalline material, and the template layer is at least partially disposed in an opening of a dielectric material. The barrier layer comprises a third crystalline material, and the third crystalline material is a binary III-V compound semiconductor. The barrier layer is over the template layer. The device layer comprises a fourth crystalline material, and the device layer is over the barrier layer. | 2014-09-18 |
20140264439 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a substrate, at least a first N-type germanium (Ge) structure and at least a first P-type Ge structure. The first N-type Ge structure is formed on the substrate and has two end parts and at least a first central part bonded between the two end parts thereof. The first central part is floated over the substrate, and a side surface of the first central part is a {111} Ge crystallographic surface. The first P-type Ge structure is formed on the substrate and has two end parts and at least a second central part bonded between the two end parts thereof. The side surface of the second central part is a {110} Ge crystallographic surface. | 2014-09-18 |
20140264440 | V-SHAPED SIGE RECESS VOLUME TRIM FOR IMPROVED DEVICE PERFORMANCE AND LAYOUT DEPENDENCE - Some embodiments of the present disclosure relates to a method and a device to achieve a strained channel. A volume of a source or drain recess is controlled by a performing an etch of a substrate to produce a recess. An anisotropic etch stop layer is then formed by doping a bottom surface of the recess with a boron-containing dopant, which distorts the crystalline structure of the bottom surface. An anisotropic etch of the recess is then performed. The anisotropic etch stop layer resists anisotropic etching such that the recess comprises a substantially flat bottom surface after the anisotropic etch. The source or drain recess is then filled with a stress-inducing material to produce a strained channel. | 2014-09-18 |
20140264441 | SEMICONDUCTOR DEVICE - The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer. | 2014-09-18 |
20140264442 | Method for Fabricating a Semiconductor Device - A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefore, to enhance carrier mobility and upgrade the device performance. | 2014-09-18 |
20140264443 | SIGE Surface Passivation by Germanium Cap - The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within a semiconductor body at a location between a source region and a drain region. A germanium cap layer is disposed onto the channel layer. A gate dielectric layer is separated from the channel layer by the germanium cap layer, and a gate region is disposed above the gate dielectric layer. Separating the gate dielectric layer from the channel layer allows for the germanium cap layer to prevent diffusion of atoms from the channel layer into the gate dielectric layer, thereby provide for a low interface trap density. | 2014-09-18 |
20140264444 | STRESS-ENHANCING SELECTIVE EPITAXIAL DEPOSITION OF EMBEDDED SOURCE AND DRAIN REGIONS - Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation (STI) spacer is formed on sidewalls of the shallow trench isolation structure around the periphery of the active area. After formation of a gate stack structure and a gate spacer, trenches are formed such that sidewalls of the trenches are vertically coincident with sidewalls of the gate spacer and the STI spacer. Epitaxial semiconductor material can be deposited into the trenches by selective epitaxy to form an embedded source region and an embedded drain region. Because all surfaces of the trenches are semiconductor surfaces, the entire trenches can be filled with the epitaxial semiconductor material, thereby enabling lateral confinement of stress within a channel region of a field effect transistor. | 2014-09-18 |
20140264445 | SOURCE/DRAIN STRUCTURE OF SEMICONDUCTOR DEVICE - The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface. | 2014-09-18 |
20140264446 | III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. | 2014-09-18 |
20140264447 | APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed. | 2014-09-18 |
20140264448 | METHOD OF FORMING A GATE CONTACT - A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device. | 2014-09-18 |
20140264449 | METHOD OF FORMING HEMT SEMICONDUCTOR DEVICES AND STRUCTURE THEREFOR - In one embodiment, a HEMT semiconductor device includes an isolation region that may include oxygen wherein the isolation region may extend thorough an ALGaN and GaN layer into an underlying layer. | 2014-09-18 |
20140264450 | SEMICONDUCTOR DEVICE AND MANUFCTURING METHOD THEREOF - A semiconductor device including a substrate, a heterojunction body, a passivation layer, a source contact, a drain contact, and a gate contact. The heterojunction body disposed on or above the substrate includes a first semiconductor layer, a mask layer, a regrowth layer, and a second semiconductor layer. The first semiconductor layer is disposed on or above the substrate. The mask layer is disposed on or above a portion of the first semiconductor layer. The regrowth layer disposed on the first semiconductor layer and adjacent to the mask layer includes a main portion and at least one inclined portion. The second semiconductor layer is disposed on the mask layer and the regrowth layer. The passivation layer is disposed on the second semiconductor layer. The gate contact is disposed on the passivation layer, between the source contact and the drain contact, and at least above the inclined portion of the regrowth layer. | 2014-09-18 |
20140264451 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME, POWER SUPPLY DEVICE, AND HIGH-FREQUENCY AMPLIFIER - A semiconductor device includes: a nitride semiconductor multilayer; an insulating film disposed on the nitride semiconductor multilayer; and a gate electrode disposed on the insulating film, wherein the nitride semiconductor multilayer has a first oxidized region near an interface with a region of the insulating film below the gate electrode, the first oxidized region having an oxygen concentration higher than an oxygen concentration of a region near an interface with a region of the insulating film other than below the gate electrode. | 2014-09-18 |
20140264452 | METHOD OF FORMING A HEMT SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors. | 2014-09-18 |
20140264453 | METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device. | 2014-09-18 |
20140264454 | OHMIC CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD - In one embodiment, a high electron mobility device structure includes heterostructure with a Group III-nitride channel layer and a Group III-nitride barrier layer that forms a two-dimensional electron gas layer at an interface between the two layers. At least one current carrying electrode includes a recess-structured conductive contact adjoining and making Ohmic contact with the two-dimensional electron gas layer. The recess-structured conductive contact has at least one side surface defined to have a rounded wavy shape. | 2014-09-18 |
20140264455 | CARBON DOPING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×10 | 2014-09-18 |
20140264456 | METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE - In an embodiment, a semiconductor device is formed by a method that includes, providing a base substrate of a first semiconductor material, and forming a layer that is one of SiC or a III-V series material on the base substrate. In a different embodiment, the base substrate may be one of silicon, porous silicon, or porous silicon with nucleation sites formed thereon, or silicon in a (111) plane. | 2014-09-18 |
20140264457 | Heterojunction Bipolar Transistor having a Germanium Raised Extrinsic Base - Disclosed is a heterojunction bipolar transistor (“HBT”) including an intrinsic base in a SiGe layer. The HBT has a raised germanium extrinsic base over the SiGe layer. A base contact is situated over and contacting the raised germanium extrinsic base. An emitter is situated over the intrinsic base, and a collector is situated under the intrinsic base. The raised germanium extrinsic base has a reduced parasitic base-collector capacitance. The raised germanium extrinsic base is situated between a first dielectric layer and a second dielectric layer. Spacers are situated adjacent the second dielectric layer. The first dielectric layer can be a nitride based dielectric, the second dielectric layer can be an oxide based dielectric, and the spacers can be a nitride based dielectric. | 2014-09-18 |
20140264458 | Heterojunction Bipolar Transistor having a Germanium Extrinsic Base Utilizing a Sacrificial Emitter Post - Disclosed is a method for fabricating a heterojunction bipolar transistor (“HBT”), and the resulting structure. The method includes forming a germanium layer over a SiGe layer, the SiGe layer including an intrinsic base. Thereafter, an emitter sacrificial post and a raised germanium extrinsic base are formed by etching away portions of the germanium layer. Then, a conformal dielectric layer is deposited over the raised germanium extrinsic base. The process continues by removing the emitter sacrificial post and forming an emitter over the intrinsic base within an emitter opening defined by the previous removal of the emitter sacrificial post. The resulting structure has a raised germanium extrinsic base with a reduced parasitic base-collector capacitance. | 2014-09-18 |
20140264459 | High Mobility Transport Layer Structures for Rhombohedral Si/Ge/SiGe Devices - An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhomhohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions. | 2014-09-18 |
20140264460 | THREE-TERMINAL PRINTED DEVICES INTERCONNECTED AS CIRCUITS - A layer of microscopic, 3-terminal transistors is printed over a first conductor layer so that bottom electrodes of the transistors electrically contact the first conductor layer. A first dielectric layer overlies the first conductor layer, and a second conductor layer over the first dielectric layer contacts intermediate electrodes on the transistors between the bottom electrodes and top electrodes. A second dielectric layer overlies the second conductor layer, and a third conductor layer over the second dielectric layer contacts the top electrodes. The devices are thus electrically connected in parallel by a combination of the first conductor layer, the second conductor layer, and the third conductor layer. Separate groups of the devices may be interconnected to form more complex circuits. The resulting circuit may be a very thin flex-circuit. | 2014-09-18 |