38th week of 2008 patent applcation highlights part 64 |
Patent application number | Title | Published |
20080229077 | COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER - A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after out-of-order execution when at least one of the plurality of processors is in an Instruction Level Parallelism (ILP) mode and at least one of the plurality of processors has a Thread Level Parallelism (TLP) core; detecting an imbalance in a dispatch of instructions of a first dependence chain compared to a dispatch of instructions of a second dependence chain with respect to dependence chain priority; determining a source of the imbalance; and activating the ILP mode when the source of the imbalance has been determined. | 2008-09-18 |
20080229078 | Dynamic Power Management in a Processor Design - Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power. | 2008-09-18 |
20080229079 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING COMMANDS OF SOLID-STATE STORAGE USING BANK INTERLEAVE - An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave that directs one or more commands to two or more queues, where the one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank. | 2008-09-18 |
20080229080 | ARITHMETIC PROCESSING UNIT - An arithmetic processing unit includes a register file provided with multiple register windows, an arithmetic executor executes an instruction with data retained in the register file as an operand, and a current window pointer which retains address information specifying a register window which becomes a current window, and a controller. The controller controls the address information retained by the current window pointer is updated, when a window switching instruction for indicating switching of the current window has been decoded. The arithmetic executor reads data in a first register window specified by the address information before being updated and data in a second register window specified by the updated address information from the register file, after the decoding of said window switching instruction has been started until commit of the window switching instruction is started. | 2008-09-18 |
20080229081 | RECONFIGURABLE CIRCUIT, RECONFIGURABLE CIRCUIT SYSTEM, AND RECONFIGURABLE CIRCUIT SETTING METHOD - Each cell comprises a first selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; a second selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; an arithmetic and logic unit which accepts selection output of the first selector and selection output of the second selector in N bits (N is a natural number of 2 or more), and performs a logic operation that is selected from a plurality of logic operations on accepted data of N bits; a selection controller which supplies, to the first selector and the second selector, a data selection control signal for indicating data to be selected; and an ALU controller which supplies, to the arithmetic and logic unit, an ALU control signal that designates the logic operation to be executed. The first selector, the second selector, and the arithmetic and logic unit are capable of reconfiguration based on the selection control signal and the ALU control signal. The first selector and the second selector rearranges M[i] bits of i-th data in a prescribed order based on the selection control signal, and outputs the rearranged data (i is a natural number that satisfies i≦K, and M[i] is an integer that satisfies Σ | 2008-09-18 |
20080229082 | CONTROL SUB-UNIT AND CONTROL MAIN UNIT - A sub-unit judges whether an instruction received from an external unit is executable. If the instruction is judged to be executable, the sub-unit executes it. If, on the other hand, the instruction is judged to be unexecutable, the sub-unit notifies the external unit of an executable plan. | 2008-09-18 |
20080229083 | Processor instruction set - The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute thread scheduling instructions which manage said statuses, the thread scheduling instructions including at least: a thread event enable instruction which sets a status to event-enabled to allow a thread to accept events, a wait instruction which sets the status to suspended pending at least one event upon which continued execution of the thread depends, and a thread event disable instruction which sets the status to event-disabled to stop the thread from accepting events. The continued execution comprises retrieval of a continuation point vector for the thread. | 2008-09-18 |
20080229084 | METHOD OF DETERMING REQUEST TRANSMISSION PRIORITY SUBJECT TO REQUEST CHANNEL AND TRANSTTING REQUEST SUBJECT TO SUCH REQUEST TRANSMISSION PRIORITY IN APPLICATION OF FIELDBUS COMMUNICATION FRAMEWORK - A method of determining request transmission priority subject to request channel and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the request channel from which the received requests came have the priority right and whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time. | 2008-09-18 |
20080229085 | Switching Drivers Between Processors - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode. | 2008-09-18 |
20080229086 | Methods and Systems for Firmware Access and Modification - Embodiments of the present invention comprise systems and methods for accessing and modifying device firmware. | 2008-09-18 |
20080229087 | CMOS CLEARING CIRCUIT - A CMOS clearing circuit mounted on a motherboard of a computer includes a south bridge chip and a switch member respectively mounted on the motherboard. The south bridge chip includes a reset terminal and an input terminal. The switch member is configured for controlling one of the reset terminal and the input terminal of the south bridge chip. If the switch member controls the reset terminal, the input terminal is disconnected from the switch member and the switch member is capable of controlling the reset terminal of the south bridge chip to be selectively connected to ground or a voltage source provided by the motherboard. If the switch member controls the input terminal, the reset terminal stays connected to the voltage source and the switch member is capable of controlling the input terminal of the south bridge chip to be selectively connected to ground or the voltage source. | 2008-09-18 |
20080229088 | Method, a device for configuring at least one firewall and a system comprising such device - A method and a device to configure at least one firewall are provided comprising the steps of (i) transmitting at least one mobility report to a firewall controller; (ii) transmitting at least one session report to the firewall controller; and (iii) configuring the at least one firewall according to the information obtained by the at least one mobility report and by the at least one session report. | 2008-09-18 |
20080229089 | Remote network device provisioning - Various embodiments are disclosed relating to remote network device provisioning. A method is disclosed, the method comprising discovering a network address associated with a device on a network based on a discovery response received in response to a discovery request provided to the device. One or more configurable boot options associated with the device may be determined based at least in part on the discovery response. One or more of the configurable boot options may be configured on the device, wherein, upon reboot of the device using the configured boot options, a software image is provided to the device. | 2008-09-18 |
20080229090 | Memory Card, Memory System Including the Same, and Operating Method thereof - Provided is a memory card device. The memory card device includes a flash memory and a controller. The flash memory includes a boot area storing boot data, and a user area storing user data. The controller accesses the boot area or the user area according to an external command. Boot data can be stored in a memory card integrated in an electronic device. Also, when a host requests an access to boot data/user data stored in the memory card, the boot data/user data can be accessed under control of the controller. | 2008-09-18 |
20080229091 | Remote Activation Device For A Computer - A remote activation device for enabling WOL capability in a target computer that is not connected to a wired network is disclosed. The remote activation device is WOL compatible and simulates a network host computer using WOL technology for “waking-up” the target computer. The remote activation device generally comprises a microcontroller and a communications controller. The device is connected to the target computer via the communications controller of the device and a wired network adapter of the target computer. As such, the remote activation device forms a “mini-network” with the target computer. The remote activation device generates and sends a WOL magic packet to the target computer instructing the computer to power ON. Once the computer is powered ON, the computer is able to wirelessly connect to a WLAN in the target computer's work environment. A computer administrator is then able to manage the target computer via network host computer. Alternatively, a computer user is able to commence work on the target computer. | 2008-09-18 |
20080229092 | Secure Boot Across a Plurality of Processors - Boot code is partitioned into a plurality of boot code partitions. Processors of a multiprocessor system are selected to be boot processors and are each provided with a boot code partition to execute in a predetermined boot code sequence. Each processor executes its boot code partition in accordance with the boot code sequence and signals to a next processor the successful and uncompromised execution of its boot code partition. If any of the processors does not signal successful completion and/or uncompromised execution of its boot code partition, the boot operation fails. The processors may be arranged, with regard to the boot operation, in a daisy chain, ring, or master/slave arrangement, for example. | 2008-09-18 |
20080229093 | SYSTEM FOR RECONFIGURING A PROCESSOR ARRAY - Embodiments of the invention are directed to a system for reconfiguring a processor array while it is currently operating. The reconfiguration system uses configuration chains streamed down communication channels that are set for the re-configuration process, then re-set after the reconfiguration process has completed. | 2008-09-18 |
20080229094 | METHOD OF TRANSMITTING CONTENTS BETWEEN DEVICES AND SYSTEM THEREOF - A method of transmitting content between devices and a system therefor are provided. The method of transmitting encrypted content in a state in which the encrypted content and license information is stored and in which an external device is connected, includes: transmitting the license information corresponding to the encrypted content to the external device; transmitting the encrypted content to the external device, when receiving a request for transmitting the encrypted content from the external device; and updating the license information. Accordingly, content can be rapidly and stably transmitted between the devices. Also, it is possible to improve the accuracy and the security in the procedure of updating the license information. | 2008-09-18 |
20080229095 | METHOD AND APPARATUS FOR DYNAMICALLY SECURING VOICE AND OTHER DELAY-SENSITIVE NETWORK TRAFFIC - A method comprises receiving a request for secure network traffic from a device having a private network address at a source node, obtaining the private network address of a requested destination device at a destination node from a route server based on signaling information associated with the request, obtaining the public network address of the destination node associated with the private network address, creating in response to the request a virtual circuit between the source node and the destination node based on the public network address of the destination node, and encrypting network traffic for transporting at least from the source node to the destination node through the virtual circuit. The process is dynamic in that the virtual circuit is created in response to the request. Hence, the process operates as if a fully meshed network exists but requires less provisioning and maintenance than a fully meshed network architecture. Furthermore, the process is readily scalable as if a hub and spoke network exists but is more suitable for delay-sensitive traffic, such as voice and video, than a hub and spoke network architecture. | 2008-09-18 |
20080229096 | Network identity management system and method - Users of Internet services (e.g., SKYPE messaging service, GOOGLETALK messaging service, AOL INSTANT MESSENGER messaging service, and MICROSOFT MESSENGER messaging service) that are initially identified using separate identifiers that may be associated with respective service providers (e.g., email addresses) can manage network identities using a single unified set of account information managed by a registry service. The registry authenticates the user's request(s) to bind a service provider identity to his or her personal registry user record. The registry internally associates the service provider identity to an internal unique identifier that is not exposed to subscribers. When a second user wishes to communicate with a first user, the second user provides any service provider identity that is believed to be associated with the first user to determine if the specified service provider identity appears to match the intended subscriber. If so, the second user may specify a nickname (unique to the second subscriber but not necessarily globally unique) to be associated internally within the registry with the internal unique identifier of the first subscriber as part of the second subscriber's user record. Later, even if the first subscriber has relinquished the service provider identity that was originally used to find the first subscriber, the second subscriber can still find the first subscriber by using the associate nickname without either subscriber ever knowing the internal unique identifier of the first subscriber. | 2008-09-18 |
20080229097 | Privacy-protecting integrity attestation of a computing platform - Systems, apparatus and methods for privacy-protecting integrity attestation of a computing platform. An example method for privacy-protecting integrity attestation of a computing platform (P) has a trusted platform module (TPM), and comprises the following steps. First, the computing platform (P) receives configuration values (PCR | 2008-09-18 |
20080229098 | ON-LINE TRANSACTION AUTHENTICATION SYSTEM AND METHOD - A system and method for authenticating an on-line user by authenticating the computing device being used by the user. The method may comprise reading device information from a computing device, creating a device credential from the device information; and, communicating the device credential to an authenticating body for authentication. The method may additionally comprise receiving personal information from a user; creating a user credential from the personal information and, communicating the user credential along with the device credential to the authenticating body for authentication. | 2008-09-18 |
20080229099 | METHOD FOR GENERATING STANDARD FILE BASED ON STEGANOGRAPHY TECHNOLOGY AND APPARATUS AND METHOD FOR VALIDATING INTEGRITY OF METADATA IN THE STANDARD FILE - An apparatus for validating integrity of metadata in a standard file includes: a metadata acquiring unit for acquiring metadata from a protected file; an integrity evidence value acquiring unit for acquiring an integrity evidence value from a file or a database; a secret information extracting unit for extracting secret information of a file data; and a metadata integrity validating unit for checking if the metadata is correct by using the acquired metadata, the acquired integrity evidence value, and the extracted secret information. | 2008-09-18 |
20080229100 | SECURE DATA MANAGEMENT USING NON-VOLATILE MEMORY - In one embodiment, encrypted data is received from an authenticated remote host at a non-volatile memory. The encrypted data includes received user data, received data volatility information, and received data validity rules. The encrypted data is stored in the non-volatile memory, and a data volatility flag and data valid flag in the non-volatile memory device are set based on the received data volatility information and the received data validity rules. The data may be read from the non-volatile memory by a user if data access is permissible as determined by the data volatility flag and the data valid flag set by the remote host. | 2008-09-18 |
20080229101 | AUTHENTICATED CORRESPONDENT DATABASE - A system that can intelligently drive down false positive rates with regard to identification and/or classification of spam correspondence is disclosed. Authentication information from sending domains can be stored and used to establish confidence and drive down the false positives related to acceptance and/or classification of communications. A correspondent database of known correspondents can be constructed using the authenticated information. Accordingly, decisions (e.g., white and black list) can be better informed by employing relationship and correspondent communication pattern data which is maintained within the correspondent database. | 2008-09-18 |
20080229102 | System and method for platform activation - A platform discrimination indication register is stored in a wireless network card. This register holds a platform discrimination indication that indicates whether the wireless network card can be used to transfer data with notebook computers or whether the wireless network card is restricted to transferring data from a personal digital assistant or defined set of restricted devices. The platform discrimination indication can be upgraded using a key value obtained from at Internet site. This key value is limited to a specific wireless network card because of the use of a unique electronic I.D. An Internet site encrypts the electronic I.D. to produce the first key, such as a platform activation key (PAK). This first key is then decrypted at the personal data device in order to obtain a unique calculated I.D. value. If the calculated I.D. value matches the electronic I.D. value on the wireless network card, then the platform discrimination indication is altered (upgraded), allowing the operation of the wireless network card with notebook computers. | 2008-09-18 |
20080229103 | Private entity authentication for pervasive computing environments - A method is provided for authenticating an entity having a plurality of keys in a digital form residing on a claimant computing device. The method comprises: generating a first code word by applying a hash function to a first key residing on the claimant computing device; encoding the first code word into an array of bits having a Bloom filter format; generating a second code word by applying a hash function to a second key residing on the claimant computing device; encoding the second code word into the array of bits; and broadcasting an authentication message having the array of bits therein from the claimant computing device. | 2008-09-18 |
20080229104 | MUTUAL AUTHENTICATION METHOD BETWEEN DEVICES USING MEDIATION MODULE AND SYSTEM THEREFOR - A mutual authentication method using a mediation module and a system therefor are provided. The method includes: storing a first partial private key obtained by dividing a first private key of a device; storing a second partial private key obtained by dividing a second private key of a host device; receiving unique identifiers (IDs) and random numbers for the device and the host device from the device and determining whether the unique IDs are valid; and generating a first signature value by using the first partial private key and a second signature value by using the second partial private key if the unique IDs are valid, and transmitting the generated first and second signature values to the device | 2008-09-18 |
20080229105 | Efficient Method for Providing Secure Remote Access - A remote user, two-way authentication and password change protocol that also allows parties to optionally establish a session key which can be used to protect subsequent communication. In a preferred embodiment, a challenge token is generated and exchanged which is a one-time value that includes a random value that changes from session to session. The construction and use of the challenge token avoids transmission of the password or even the transmission of a digest of the password itself. Thus the challenge token does not reveal any information about a secret password or a digest of the password. | 2008-09-18 |
20080229106 | Information processing apparatus and data transmission method of information processing apparatus - An apparatus stores first divided trust information which is one portion resulting from division of trust information generated by a transmission target apparatus that is a transmission target for data, receives a transmission request for the data from the target apparatus and receives second divided trust information which is the other portion resulting from division of the trust information of the target apparatus and verification information generated using information indicating a state of the target apparatus that made the request, recovers the trust information using the first divided trust information stored and the received second divided trust information, verifies trustworthiness of the target apparatus using the recovered trust information and the received verification information, transmits the data indicated by the request to the target apparatus when the verification of trustworthiness is successful. | 2008-09-18 |
20080229107 | Token-Based Dynamic Key Distribution Method for Roaming Environments - A method for establishing a new security association between a mobile node and a network source, the method comprising creating a first token comprising a security association between a network source and a mobile node, the first token being encrypted using a first key known to the mobile node and a first trust authority within a home network associated with the mobile node, and creating a second token comprising the same security association between the network source and the mobile node, the second token being encrypted using a second key known to the first trust authority and a second trust authority associated with the network source, wherein the first token and the second token are sent to the second trust authority using a chain of trust infrastructure. | 2008-09-18 |
20080229108 | PRIVATE INFORMATION EXCHANGE IN SMART CARD COMMERCE - A method, system and computer program product for private information exchange in smart card commerce is disclosed. The method includes, in response to determining that an item of biometric data received on a biometric reader corresponds to an authorized user, unlocking a communication channel on a communication port, exchanging public keys between the user and authorized point of sale, receiving an information request from an external point of sale machine across the communication channel, decrypting an information request and parsing a data token. In response to determining that private data has been requested in the information request, a user is prompted for authorization to release the private information, and private information exchange in smart card commerce is performed by, in response to the user pressing a yes button on the smart card, placing an encrypted copy of the private data in the public area of the smart card for transmission across the communication channel to the external point of sale machine. | 2008-09-18 |
20080229109 | HUMAN-RECOGNIZABLE CRYPTOGRAPHIC KEYS - A visual authentication scheme for websites is provided that binds an image to a website so that a user can by visually authenticate whether he/she is viewing an intended/trusted website. An authentication or cryptographic key (associated with a web page) is rendered as a unique key-identifying image or unique sequence of images. This key-identifying image(s) is then displayed to the user. The user associates this key-identifying image with the originator or source of the web page so that the user can easily recognize the originator by glancing at the key-identifying image. The association between the key-identifying image and the cryptographic/authentication key (and thereby the source of the web page) can be achieved similarly to brand awareness. | 2008-09-18 |
20080229110 | FAST AUTHENTICATION OVER SLOW CHANNELS - A method of providing secure communications over a network includes receiving, at a receiving computer, a public key of a sending computer, and a hash of a sending random number over a first communication channel, transmitting, from the receiving computer, a public key of the receiving computer and a receiving random number provided by the receiving computer over the first communication channel, and receiving, at the receiving computer, the sending random number provided by the sending computer over the first communication channel. | 2008-09-18 |
20080229111 | PREVENTION OF UNAUTHORIZED FORWARDING AND AUTHENTICATION OF SIGNATURES - A forwarding signature comprises a modified digital signature, modified using a predetermined parameter between a sender and an intended recipient. An intended recipient of the forwarding signature can verify that the forwarding signature corresponds to the message, but, can neither derive the original digital signature nor generate a new forwarding signature for a different parameter. Generation and verification of the forwarding signature is accomplished with access to the public key of a public/private cryptographic key pair, the original signed message, and the predetermined parameter. Access to the private key is not needed. | 2008-09-18 |
20080229112 | ACCESS CONTROLLER - A deciding unit causes a database, by employing a table joining function, to join a plurality of real tables to generate a virtual table containing target data that can be provided to an authentic user, acquires the target data from the virtual table, and decides data to be displayed on a client device used by the authentic user based on the target data. | 2008-09-18 |
20080229113 | Trusted Time Stamping Storage System - Data stored in a data storage system is hashed to generate a hash value. The hash value and a request for a time stamp are then sent to a time stamping authority. A time stamp token and/or a time stamp certificate is received from the time stamping authority. The time stamp token includes a time stamp and the hash value, and may be encrypted using a private key of the time stamping authority. The time stamp token and/or time stamp certificate is then stored with, for example, a reference to the data being stored in the data storage system. The time stamp token and/or time stamp certificate may then be used to validate the data being stored and the time stamp. | 2008-09-18 |
20080229114 | INFORMATION PROCESSING APPARATUS, SOFTWARE UPDATE METHOD, AND IMAGE PROCESSING APPARATUS - An information processing apparatus, a software update method, and an image processing apparatus capable of encrypting and decrypting information using values uniquely calculated from booted primary modules or booted backup modules with less effort are disclosed. The information processing apparatus includes primary modules and the same kinds of backup modules, and includes a value storage unit storing values calculated from the modules, an encryption information storage unit storing information unique to the modules, an information decryption unit decrypting the information unique to the modules using the values in the value storage unit, and an encryption information update unit, when the module is updated, encrypting the information unique to the modules based on a value calculated from the each kind of the primary modules or the backup modules after the update. | 2008-09-18 |
20080229115 | PROVISION OF FUNCTIONALITY VIA OBFUSCATED SOFTWARE - In an example embodiment, executable files are individually encrypted utilizing a symmetric cryptographic key. For each user to be given access to the obfuscated file, the symmetric cryptographic key is encrypted utilizing a public key of a respective public/private key pair. A different public key/private key pair is utilized for each user. Obfuscated files are formed comprising the encrypted executable files and a respective encrypted symmetric cryptographic key. The private keys of the public/private key pairs are stored on respective smart cards. The smart cards are distributed to the users. When a user wants to invoke the functionality of an obfuscated file, the user provides the private key via his/her smart card. The private key is retrieved and is utilized to decrypt the appropriate portion of the obfuscated file. The symmetric cryptographic key obtained therefrom is utilized to decrypt the encrypted executable file. | 2008-09-18 |
20080229116 | Performing AES encryption or decryption in multiple modes with a single instruction - A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction. | 2008-09-18 |
20080229117 | Apparatus for preventing digital piracy - A method for preventing digital piracy in a computing environment comprises loading an application into the computing environment, wherein the application is encrypted using a cryptographic key; assigning a virtual address space to the application; loading the cryptographic key for the application into a register which is accessible only by a central processing unit; and storing an index value for the key in the register in a page table entry which corresponds to the virtual address space for the application, thereby linking the virtual address space to the key for the application. | 2008-09-18 |
20080229118 | Storage apparatus - Provided is a storage apparatus capable of encrypting data without affecting the business performance. This storage apparatus includes a cache memory, a first controller for controlling the writing of data in the cache memory pursuant to the write command, a second controller for controlling the writing of the data written in the cache into the storage devices, and an encryption engine for encrypting data pursuant to the write command. When the second controller reads the data from the cache memory and writes the data in said storage devices, the encryption engine encrypts the data, and the second controller writes the encrypted data in said storage devices. | 2008-09-18 |
20080229119 | Information Carrier Authentication With a Physical One-Way Function - The present invention relates to a method of enabling authentication of an information carrier ( | 2008-09-18 |
20080229120 | SYSTEM AND METHOD FOR CONTINUAL CABLE THERMAL MONITORING USING CABLE RESISTANCE CONSIDERATIONS IN POWER OVER ETHERNET - A system and method for continual cable thermal monitoring using cable resistance considerations for Power over Ethernet (PoE) applications. Cable heating in PoE applications is related to the resistance of the cable itself. By periodically monitoring the resistance of the cable, it can be determined whether the cable has exceeded certain operating thresholds. The determined resistance as a proxy for cable heating can then be used in adjusting operational characteristics of PoE channels. | 2008-09-18 |
20080229121 | Selectively Powered Data Interfaces - A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits. | 2008-09-18 |
20080229122 | STATE CHANGE SENSING - Application of too much voltage to a memory cell will cause damage to the cell or even destroy the cell. Tracking current that arises from an application of voltage upon a memory cell allows for minimization of damage upon the memory cell. If there is a change in current, then the voltage application can be accordingly changed. | 2008-09-18 |
20080229123 | Power transmission line for power supply clusters - A power transmission line for power supply clusters is electrically connected to a personal computer and a power supply cluster to allow the power supply cluster to receive ON/OFF signals and has a signal delay circuit to generate a time difference for the ON/OFF signals so that the power supply cluster delivers power output in an asynchronous fashion to drive the personal computer. | 2008-09-18 |
20080229124 | Power supply controlling circuit and scanner unit - A power supply controlling circuit includes: power supplied portions, adapted to receive power supply from at least one external apparatus; a first power unit, adapted to be driven by a first power; and a second power unit, adapted to be driven by a second power. In response to a change of the power supply, the second power is varied, while the first power is maintained. | 2008-09-18 |
20080229125 | POWER MANAGING METHOD OF A SCHEDULING SYSTEM AND RELATED SCHEDULING SYSTEM - A scheduling system includes a main processor, a micro control unit and a power supply. The main processor has a first memory module for storing a plurality of scheduled times. The micro control unit has a second memory module for storing a first scheduled time of the plurality of scheduled times provided by the first memory module and a timer for providing a real time. A corresponding power managing method includes: (a) starting the micro control unit; (b) the micro control unit determining whether the first scheduled time is stored in the second memory module according to a schedule flag; (c) the micro control unit determining a correlation between the first scheduled time and the real time; and (d) the micro control unit controlling the power supply to power on or power off the main processor of the scheduling system according to determined results in step (b) and step (c). | 2008-09-18 |
20080229126 | COMPUTER SYSTEM MANAGEMENT AND THROUGHPUT MAXIMIZATION IN THE PRESENCE OF POWER CONSTRAINTS - Methods are provided for maximizing the throughput of a computer system in the presence of one or more power constraints. Throughput is maximized by repeatedly or continuously or periodically optimizing task scheduling and assignment for each of a plurality of components of a computer system. The components include a plurality of central processing units (CPUs) each operating at a corresponding operating frequency. The components also include a plurality of disk drives. The corresponding operating frequencies of one or more CPUs of the plurality of CPUs are adjusted to maximize computer system throughput under one or more power constraints. Optimizing task scheduling and assignment, as well as adjusting the corresponding operating frequencies of one or more CPUs, are performed by solving a mathematical optimization problem using a first methodology over a first time interval and a second methodology over a second time interval longer than the first time interval. The first methodology comprises a short term heuristic solver for adapting to computer system changes that occur on a short time scale, and the second methodology comprises a long term solver having greater accuracy and greater computational complexity than the first methodology. | 2008-09-18 |
20080229127 | Method and System for Estimating Processor Utilization from Power Measurements - A method and system for estimating processor utilization from power measurements provides an estimate of processor utilization that can be computed outside of the processor and operating system. Measurements of the processor power consumption are gathered over short intervals in a histogram. The idle power consumption of the processor is determined, and a threshold value higher than the idle power consumption level is computed from the idle power consumption. The number of histogram counts for bins greater than the threshold is normalized to the total number of measurements, providing a fractional value that corresponds to the processor utilization over the measurement interval. The fractional value can then be used in a power management algorithm that adjusts the frequency and optionally the voltage of the processor or group of processors based on their utilization. | 2008-09-18 |
20080229128 | System and Computer Program Product for Dynamically Managing Power in MicroProcessor Chips According to Present Processing Demands - A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary. | 2008-09-18 |
20080229129 | Remote Control Save and Sleep Override - An approach is provided that handles a power down signal received by a device. Other types of signals, such as suspend or save and sleep, may also be handled. A device, such as a parent device, sends a power down signal to another device, such as a child device. The power down signal is received by the child device and acted upon, based on the activities currently being executed by the child device. Each activity currently being executed by the child device is handled according to its corresponding setting in an activity list. For example, if the child device is currently executing a preferred activity, the power down signal is ignored. A user of the child device may also send an explanation (or explanations) to the parent device. | 2008-09-18 |
20080229130 | Power reduction for system on chip - Disclosed herein are SOC devices with peripheral units having power management logic. | 2008-09-18 |
20080229131 | Storage System and Management Information Acquisition Method for Power Saving - The object of the invention is to control the power consumption in a storage subsystem. In a storage system, when a monitor in a host computer acquires information concerning a storage region to manage the storage region, a monitor in the host computer checks whether or not the power supply state in the storage region is ‘on’ based on a storage region information that stores first information indicating whether or not the power supply state in the storage region is ‘on’ and second information concerning the storage region, and acquires the second information from the storage region information table if the power supply state in the storage region is not ‘on’. | 2008-09-18 |
20080229132 | Image Processing Apparatus and Control Method, and Program and Storage Medium Thereof - An object is to provide an image processing apparatus which can reduce power consumption during the power saving standby mode. The starting factor monitor unit and the power saving standby mode voltage control unit are driven with the USB bus power can be supplied during a shift to the power saving standby mode and the starting factor monitor unit and the power saving standby mode voltage control unit are driven by voltage from the main power supply when the USB bus power cannot be supplied during a shift to the power saving standby mode. | 2008-09-18 |
20080229133 | POWER REDUCTION DEVICE FOR DATA BACKUP - A power reducer for data backup stops a power supply one after another for each memory whose backup has been completed, thereby reducing power consumption for battery during the backup lengthening a data backup time. The power reducer for data backup in a device includes an external power supply unit supplying power to the device, auxiliary power supply unit charging based upon the power supply from the external power supply unit and supplying auxiliary power to the device when the power from the external power supply unit is stopped, a cache memory having first and second memory units and recording a part of data stored in a storage medium, and a controller controlling power from the auxiliary power supply unit to the device and stopping power to the first or second memory unit one after another. | 2008-09-18 |
20080229134 | RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM - In processors having buffers to manage instruction flow referred to as a ReOrder Buffer (ROB) it is shown that these buffers are of the same approximate size of a checkpoint array for architected state. In a particular “morphing mode” in which a pair of processors can be configured to provide different functionalities on demand, a new “High-Reliability” (HR) mode is provided in which the ROB of one of the processors is used for a checkpoint array, and the pair of processors is made to run in lockstep on a single instruction stream under the control of the remaining ROB so as to provide redundant, hence highly-reliable computing. | 2008-09-18 |
20080229135 | SEMICONDUCTOR INTEGRATED CIRCUIT, MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD - Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively. | 2008-09-18 |
20080229136 | Controlling Asynchronous Clock Domains to Perform Synchronous Operations - A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation a manufacturing test sequence, debug operation, or the like. | 2008-09-18 |
20080229137 | SYSTEMS AND METHODS OF COMPRESSION HISTORY EXPIRATION AND SYNCHRONIZATION - Systems and methods of storing previously transmitted data and using it to reduce bandwidth usage and accelerate future communications are described. By using algorithms to identify long compression history matches, a network device may improve compression efficiently and speed. A network device may also use application specific parsing to improve the length and number of compression history matches. Further, by sharing compression histories, compression history indexes and caches across multiple devices, devices can utilize data previously transmitted to other devices to compress network traffic. Any combination of the systems and methods may be used to efficiently find long matches to stored data, synchronize the storage of previously sent data, and share previously sent data among one or more other devices. | 2008-09-18 |
20080229138 | DIRECTLY OBTAINING BY APPLICATION PROGRAMS INFORMATION USABLE IN DETERMINING CLOCK ACCURACY - Information usable in determining the quality of time produced by a clock of a processing environment is obtained. The information is obtained directly by an application program absent use of a supervisor service, such as an operating system or operating system service. The application program invokes an instruction that returns a parameter block that includes the information. | 2008-09-18 |
20080229139 | Space-and Time- Adaptive Nonblocking Algorithms - We explore techniques for designing nonblocking algorithms that do not require advance knowledge of the number of processes that participate, whose time complexity and space consumption both adapt to various measures, rather than being based on predefined worst-case scenarios, and that cannot be prevented from future memory reclamation by process failures. These techniques can be implemented using widely available hardware synchronization primitives. We present our techniques in the context of solutions to the well-known Collect problem. We also explain how our techniques can be exploited to achieve other results with similar properties; these include long-lived renaming and dynamic memory management for nonblocking data structures. | 2008-09-18 |
20080229140 | System and method of disaster recovery - In a DR system, from the viewpoint of device cost, when search is not carried out, a physical application where log recovery is available by inexpensive DB appliance server is adopted. Further, a local mirror operation at a secondary site is not carried out. Furthermore, from the viewpoint of operation, by a log apply function unit, the tendencies of a log application and operations are monitored, and a search process is accepted according to the progress conditions of the log application. When the log application does not catch up sufficiently, the search is not accepted. Moreover, when a consistency guarantee of a secondary DB is made, not transactions in process at the moment of search instruction are undone (rolled back), but only transactions in process at the moment of a search instruction are redone (rolled forward). | 2008-09-18 |
20080229141 | Debugging method - The invention provides a debugging method applicable for an embedded system. The system includes a processor, a main memory and a debugging interface. A debugging program is first provided in the main memory. A debugging interruption is subsequently triggered to cause the processor to read the debugging program from the main memory and execute the debugging program. After execution, an execution result of the debugging program is stored into the main memory. The execution result is read and output via the debugging interface for further analysis. Because the architecture does not require a scan chain of ITR | 2008-09-18 |
20080229142 | SELF-SERVICE RECOVERY OF APPLICATION DATA - Self-service recovery of application data. A list of recoverable objects for the application is generated in response to the receipt of a request for an application recovery from a user. The list of recoverable objects for the application is sent to the user. A selected recoverable object from the user is received. In response, the execution of a recovery job on the backup and restore application is initiated for the selected recoverable object. | 2008-09-18 |
20080229143 | Management of available circuits to repair defective circuits - Systems and methods are provided for management of available, possibly redundant, circuits, in particular memory circuits, possibly found in defective processors, to repair defective circuits, in particular memory circuits, such as shared memory, wherein functional memory of a potentially-deactivated available circuit may be activated and used in place of dysfunctional memory of an enabled circuit. | 2008-09-18 |
20080229144 | FLEXIBLE ROW REDUNDANCY SYSTEM - A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size. | 2008-09-18 |
20080229145 | Method and system for soft error recovery during processor execution - A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting code stage before the write-back stage that checks a value to be written by the processor for any error. The error-correcting code stage may correct any error in the value, and the pipeline may lack a recovery unit pipeline. | 2008-09-18 |
20080229146 | High Availability Multi-Processor System - A method and system are provided for enabling replacement of a failed processor without requiring redundancy of hardware. The system is a multiprocessing computer system that includes one or more processor chips. Each processor chip may include one or more logical processors. During system initialization, one or more logical processors may be reserved in an inactive state. In the event an error is detected on a logical or physical processor, one or more reserved logical processors may have execution context transferred from the processor experiencing the error. Thereafter, the active processor is designated as inactive and replaced by the inactive processor to which the execution context has been transferred. | 2008-09-18 |
20080229147 | DATA PROTECTION SYSTEM - The present invention provides systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format. The present invention also provides systems and methods for protecting data stored on data storage medium so that the data may be recovered without errors. | 2008-09-18 |
20080229148 | ENHANCED ERROR IDENTIFICATION WITH DISK ARRAY PARITY CHECKING - When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented. | 2008-09-18 |
20080229149 | REMOTE TESTING OF COMPUTER DEVICES - In embodiments of the present invention improved capabilities are described for a method and system of software testing that may used on a computer network, the network may include a plurality of computer devices; may use a network management system to transmit test data over the computer network to at least one of the plurality of computer devices; test configuration settings on the at least one computer device using the transmitted test data; and report an actual test result of the at least one computer device back to the network management system. | 2008-09-18 |
20080229150 | Address translation system for use in a simulation environment - Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of physical addresses required for execution of the system definition file in the testable system. The method also includes inputting a memory map file into the translation utility, the memory map representing a virtual memory space for a virtual testable system. The method further includes generating virtual translation information by translating the physical addresses into virtual addresses using the memory map file. | 2008-09-18 |
20080229151 | Electronic control unit - An ECU that controls an engine of a vehicle includes a MPU and an IC that monitors the operation of the MPU. The MPU is programmed to execute a verification result check and test selection function for selecting a test for verifying the function of the MPU. The MPU runs the selected test, and transmits a test result indicating the result of the test to the IC. The IC checks whether the test result from the MPU is correct or incorrect, and transmits a verification result to the MPU. | 2008-09-18 |
20080229152 | On-chip debug emulator, debugging method, and microcomputer - An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of serial communication circuits are commonly provided with a clock signal. The debug communication control unit controls communications with the target device based on commands output from the host device. Each of The plurality of serial communication circuits contains a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal. Namely, the plurality of serial communication circuits communicate in parallel while operating synchronized with the same clock. The on-chip debug emulator can in this way be made utilizing a low-cost microcomputer not containing any parallel communication circuits. | 2008-09-18 |
20080229153 | System and method of network error analysis - Systems and methods for network analysis are provided. A system may include an input to receive communication reports from a plurality of end terminals of a multicast network. The system may also include a memory including multicast network topology data. The system may also include logic to determine a source of at least one communication anomaly based on received communication reports and the multicast network topology data. | 2008-09-18 |
20080229154 | Self-referencing redundancy scheme for a content addressable memory - A self-referencing redundancy scheme in a content addressable memory may use a faulty bit table, populated during manufacturing, to indicate, not only the address of all the defective memory locations, but also the data which they should hold. Then, during read out, a read out state machine may access the faulty bit table, determine the data the faulty location should have held, and write that faulty data onto latches associated with the faulty memory elements. | 2008-09-18 |
20080229155 | ENHANCED ERROR IDENTIFICATION WITH DISK ARRAY PARITY CHECKING - When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented. | 2008-09-18 |
20080229156 | Method and Apparatus for Hardware Awareness of Data Types - A method, apparatus, and computer instructions in a processor for associating a data type with a memory location. The type is associated with a location by means of metadata that is generated and manipulated by hardware instructions that are typically generated by a compiler as it generates the other instructions that comprise the machine code version of a program. A determination is made as to whether a data value about to be stored is of the required data type for that location. The hardware indicates an error condition if the types do not match. | 2008-09-18 |
20080229157 | Performing Externally Assisted Calls in a Heterogeneous Processing Complex - A mechanism is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted call. A data plane processor first constructs a parameter area based on the input and output parameters for the function that requires control processor assistance. The current values for the input parameters are copied into the parameter area. An assisted call message is generated based on a combination of a pointer to the parameter area and a specific library function opcode for the library function that is being called. The assisted call message is placed into the processor's stack immediately following a stop-and-signal instruction. The control plane processor is signaled to perform the library function corresponding to the opcode on behalf of the data plane processor by executing a stop and signal instruction. | 2008-09-18 |
20080229158 | RESTORATION DEVICE FOR BIOS STALL FAILURES AND METHOD AND COMPUTER PROGRAM PRODUCT FOR THE SAME - A restoration device for restoring a system when the BIOS falls in a stall failure includes a first watchdog timer and a second watchdog timer, a setter for setting timer values respectively in the first watchdog timer and in the second watchdog timer, a suspender for suspending the decrement of the timer value of the first watchdog timer when the BIOS is started and also execution of a BIOS process is started, a switch for switching the BIOS data region for starting when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a resetter for resetting the system when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a suspender for suspending the decrement of the timer value of the second watchdog timer when the BIOS of the system starts and a resetter for resetting the system when the timer value of the second watchdog timer becomes equal to 0 or a prescribed number. | 2008-09-18 |
20080229159 | FAILSAFE COMPUTER SUPPORT ASSISTANT - A computer running a host operating system in a host virtual machine includes a support operating system running in a support virtual machine. A support module running in the support operating system identifies and remediates defects associated with the host operating system. A monitoring module running in the support operating system identifies a defect associated with the host operating system and notifies the support module responsive to identification of the defect. A user interface is provided for the support module. The user interface can be through a web server or a support button associated with an input device of the computer. The user interface can be supported through input/output virtualization hardware of the computer. A host agent module executing in the host operating system can interact with the support module to remediate a defect associated with the host operating system. | 2008-09-18 |
20080229160 | CONTROLLING SOFTWARE FAILURE DATA REPORTING AND RESPONSES - User input defines transmission filter rules to be met when sending an error report to a support provider. User input also defines collection filter rules to be met when including failure data within an error report. Error reports corresponding to crash failures at clients are filtered with the transmission filter rules to determine which of the error reports to send to the support provider, and each error report to be sent to the support provider is further filtered to remove any failure data that fails to satisfy the collection filter rules. Each error report that satisfies the transmission filter rules, along with the failure data satisfying the collection filter rules, is sent to the support provider for analysis. Standard and or custom failure responses corresponding to the failures at the clients may be retrieved and sent to the clients in accordance with the collection filter rules. | 2008-09-18 |
20080229161 | MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF - Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure. | 2008-09-18 |
20080229162 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing succeeded. | 2008-09-18 |
20080229163 | TEST APPARATUS, TEST METHOD AND MACHINE READABLE MEDIUM STORING A PROGRAM THEREFOR - The present invention provides a test apparatus that tests a plurality of memories under test. The test apparatus includes a data input-output section that gives and receives data to and from data input-output terminals of the plurality of memories under test, a test data supplying section that parallel supplies test data to the plurality of memories under test, a writing control section that parallel supplies a write enable signal to the plurality of memories under test, a reading control section that sequentially supplies a read enable signal to each of the plurality of memories under test, a comparing section that compares the test data sequentially read from the respective memories under test with an expected value, and a detecting section that detects, on condition that one test data is not identical with the expected value, a writing fail for the memory under test that outputs this test data. | 2008-09-18 |
20080229164 | MEMORY CARD AND MEMORY CONTROLLER - A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card. | 2008-09-18 |
20080229165 | Address translation system for use in a simulation environment - Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of virtual addresses required for execution of the system definition file in a virtual testable system. The method also includes inputting a memory map file into the translation utility, the memory map representing a physical memory space for a testable system. The method further includes generating translation information by translating the virtual addresses into physical addresses using the memory map file. | 2008-09-18 |
20080229166 | Accelerating Test, Debug and Failure Analysis of a Multiprocessor Device - A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault. | 2008-09-18 |
20080229167 | PACKET DATA TRANSMITTING METHOD AND MOBILE COMMUNICATION SYSTEM USING THE SAME - A packet data transmitting method and mobile communication system using the same enables transmission of common ACK/NACK information from each sector of a base station to a user entity in softer handover. The method includes receiving via at least one of the plurality of sectors a data packet from the mobile terminal, the data packet being correspondingly received for each of the at least one of the plurality of sectors; combining the correspondingly received data packets, to obtain a signal having a highest signal-to-noise ratio; decoding the value obtained by the combining; determining a transmission status of the data packet according to the decoding; and transmitting to the mobile terminal a common ACK/NACK signal including one of a common ACK signal and a common NACK signal according to the determining, the common ACK/NACK signal being transmitted via each of the at least one sector. | 2008-09-18 |
20080229168 | Multi-Antenna Transmitting Apparatus, Multi-Antenna Receiving Apparatus, and Data Re-Transmitting Method - In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus ( | 2008-09-18 |
20080229169 | DATA RECOVERY CIRCUIT - A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A second parity generation circuit writes backup data of the actual data with odd parity to the copy region. A read circuit reads data from the actual data region and the copy region. An even parity checker detects a parity error in the actual data based on the data read from the actual data region. An odd parity checker checks whether the data read from the copy region is backup data. | 2008-09-18 |
20080229170 | Parallel arrangement of serial concatenated convolutional code decoders with optimized organization of data for efficient use of memory resources - A decoding system ( | 2008-09-18 |
20080229171 | Serial Concatenated Convolutional Code Decoder - A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder is comprised of an input buffer memory ( | 2008-09-18 |
20080229172 | High Rate Turbo Encoder and Recoder for Product Codes - The invention relates to a Method of decoding a matrix built from concatenated codes, corresponding to at least two elementary codes, with uniform interleaving, this matrix having n | 2008-09-18 |
20080229173 | METHOD AND APPARATUS FOR ERROR CODE CORRECTION - The present invention is related to a method and apparatus for ECC (error code correction). The method of ECC includes a first directional first decoding, a first directional second decoding, a second directional first decoding, a second directional second decoding, wherein the error tolerant ability of first directional second decoding is greater than that of the first directional first decoding, and the error tolerant ability of second directional second decoding is greater than that of the second directional first decoding. The ECC method includes the following steps: read a data to be decoded; and if there exists at least one solution cannot be efficiently solved after continuous executing the first directional first decoding and the second directional second decoding, and execute the decoding action in the ECC decoding of the present invention according to a predetermined flow control rule, if there exists no correction performed during the ECC decoding and switch to the other directional decoding, the un-modified value is added by one; and if the un-modified value reached a maximum unmodified value, an ECC failure is confirmed and then stop the ECC decoding. | 2008-09-18 |
20080229174 | ERROR DETECTION IN A COMMUNICATIONS LINK - An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols. | 2008-09-18 |
20080229175 | METHOD AND APPARATUS FOR PROVIDING HELP UPON USER'S WRONG BUTTON MANIPULATION - A method and apparatus for providing help upon a user's wrong button manipulation, the method including: obtaining information on a user's button manipulation; checking whether an error pattern is detected in the button manipulation, using the information on button manipulation; and if the error pattern is detected, providing help information corresponding to the detected error pattern. According to the present invention, information on a user's button manipulation in a device is obtained, an error or malfunction pattern due to the user's wrong button manipulation is detected, and help information is provided in order to allow the user to return to the right process or prevent the error next time. | 2008-09-18 |
20080229176 | METHOD FOR FAST ECC MEMORY TESTING BY SOFTWARE INCLUDING ECC CHECK BYTE - The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry. | 2008-09-18 |