38th week of 2008 patent applcation highlights part 16 |
Patent application number | Title | Published |
20080224265 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A second insulation film is provided on the high resistance element. A hydrogen diffusion preventing film having a hydrogen diffusion coefficient smaller than that of the second insulation film is provided on the second insulation film. The hydrogen diffusion preventing film covers a part of the high resistance element. | 2008-09-18 |
20080224266 | LATERAL BIPOLAR TRANSISTOR - A lateral bipolar transistor is described, including a semiconductor substrate, a gate structure on the substrate, an emitter and a collector of a first conductivity type in the substrate, and a base of a second conductivity type in the substrate. The gate structure has a structure enclosing one or more closed areas. The emitter and the collector respectively includes a plurality of electrically connected unit emitters and a plurality of electrically connected unit collectors defined by the gate structure, which are arranged laterally intermixing with each other and separated by the substrate under the gate structure. The base includes a part under the gate structure. | 2008-09-18 |
20080224267 | SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer. | 2008-09-18 |
20080224268 | NITRIDE SEMICONDUCTOR SINGLE CRYSTAL SUBSTRATE - To provide a nitride semiconductor single crystal substrate comprising a Si substrate and a nitride semiconductor film which has semi-polar (10-1m) plane (m: natural number) and a thickness of 1 μm or more, the nitride semiconductor single crystal substrate being suitably used for a light-emitting device, the nitride semiconductor single crystal substrate being suitably used for a light-emitting device, this invention provides a nitride semiconductor single crystal substrate comprising a Si substrate having an off-cut angle of 1 to 35° in the <110> direction from the <100> direction, a buffer layer | 2008-09-18 |
20080224269 | Gettering structures and methods and their application - An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation. | 2008-09-18 |
20080224270 | SILICON SINGLE CRYSTAL SUBSTRATE AND MANUFACTURE THEREOF - A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the wafer meet; and a back chamfered part along a circumferential edge where the back face and the side face meet is provided. After a CVD layer formation process is conducted to form a layer at least on the back face and the back chamfered part, a machining process is conducted on the main face to remove a CVD layer at least partially formed thereon so as to polish the main face to a mirror finished surface with a maximum height of profile (Rz) not exceeding 0.3 μm. | 2008-09-18 |
20080224271 | Semiconductor Device and Method of Manufacturing Same, Wiring Board and Method of Manufacturing Same, Semiconductor Package, and Electronic Device - Passivation films | 2008-09-18 |
20080224272 | Active Structure of a Semiconductor Device - An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n) | 2008-09-18 |
20080224273 | CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS - A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method. | 2008-09-18 |
20080224274 | Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device - To achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way. In addition, to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which crystal faces and/or crystal axes of single-crystalline semiconductor layers of a first conductive MISFET and a second conductive MISFET are different. The crystal faces and/or crystal axes are arranged so that mobility of carriers flowing in channel length directions in the respective MISFETs is increased. Such a structure can increase mobility of carriers flowing through channels of the MISFETs and high speed operation of a semiconductor integrated circuit can be achieved. Further, low voltage driving becomes possible, and low power consumption can be realized. | 2008-09-18 |
20080224275 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film. | 2008-09-18 |
20080224276 | Semiconductor device package - The present invention provides a package structure and a method for forming the same; wherein the structure comprises a substrate with certain open through holes filled with conducting metals for performing electrical connection or heat dissipation, a chip with bonding pads attached on the contacting pad by an adhesive with high thermal conductivity, wire bounded the contacting pad and the chip pad, a protection layer covered on the chip, wire and a portion of pad by molding or dispensing and a solder ball disposed on the pad. The advantages of the present invention are: the structure is reduced; the heat dissipation of the structure is enhanced; the structure can form package on package structure; the pads provides better ground shielding, heat dissipation of the structure. | 2008-09-18 |
20080224277 | CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask. | 2008-09-18 |
20080224278 | CIRCUIT COMPONENT AND METHOD OF MANUFACTURE - An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material disposed on the flag. Wire bonds are formed from the conductive strips on one side of the ferrite core to corresponding conductive strips on an opposing side of the ferrite core. The wire bonds and the conductive strips cooperate to form the coil of the inductor. Wire bonds electrically couple one end of the inductor to leadframe leads adjacent the semiconductor die. Wire bonds couple bond pads on the semiconductor die to the leadframe leads coupled to the inductor. An encapsulant is formed around the inductor and the semiconductor die. Alternatively, a stand-alone inductor is manufactured. | 2008-09-18 |
20080224279 | VERTICAL ELECTRICAL INTERCONNECT FORMED ON SUPPORT PRIOR TO DIE MOUNT - A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals. | 2008-09-18 |
20080224280 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted; and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island. | 2008-09-18 |
20080224281 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a forth metal layer which is primarily composed of nickel, ion or cobalt. | 2008-09-18 |
20080224282 | Semiconductor device and method of manufacturing the same - A technique for preventing cracks and residual resin on a semiconductor chip in a molding process in the assembly of semiconductor devices is provided. A distance from a bottom surface of a cavity of a lower mold die to a ceiling surface of a cavity of an upper mold die of a resin molding die is made same as or smaller than a distance from a lower surface of a die pad to an upper surface of a plate terminal, and an U-shape elastic body is arranged on semiconductor elements between the plate terminal and the die pad, thereby mitigating a load due to a clamp pressure of mold dies in the molding process by an elastic deformation of the elastic body. Consequently, a load applied on the semiconductor devices is reduced, thereby preventing formation of cracks on the semiconductor elements. | 2008-09-18 |
20080224283 | Leadframe-based semiconductor package and fabrication method thereof - A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads. | 2008-09-18 |
20080224284 | CHIP PACKAGE STRUCTURE - A chip package structure mainly including a substrate, a chip and a lead frame is provided. The chip is disposed on the substrate, and is electrically connected to the chip by flip-chip or wire-bonding technique. The chip is electrically connected to the lead frame through a redistribution layer on the substrate. Therefore, a problem that the bonding wires may collapse due to a longer distance between the chip and the lead frame may be resolved, thus improving the yield rate thereof. | 2008-09-18 |
20080224285 | Power module having stacked flip-chip and method of fabricating the power module - Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. | 2008-09-18 |
20080224286 | Vertically mountable semiconductor device package - A semiconductor package that includes a die with electrodes on opposite surfaces thereof and respective conductive clip electrically and mechanically coupled to the electrode and configured for vertical mounting of the package. | 2008-09-18 |
20080224287 | OPTOELECTRONIC DEVICE ALIGNMENT IN AN OPTOELECTRONIC PACKAGE - Using one or more reference indicators in die attaching an optoelectronic device to a lead during the assembly of an optoelectronic package. One example method of assembling an optoelectronic package includes detecting a reference indicator included in a first component of an optoelectronic package. The method also includes die attaching a second component to the optoelectronic package at a die attach location. The die attach location is substantially aligned with the reference indicator along a line that intersects the reference indicator and is parallel to either an x-axis or a y-axis of an x-y coordinate system associated with the optoelectronic package. | 2008-09-18 |
20080224288 | Portable Object Connectable Package - A portable object connectable package | 2008-09-18 |
20080224289 | Multi-chip stack structure and fabrication method thereof - A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented. | 2008-09-18 |
20080224290 | LOW COST LEAD-FREE PREPLATED LEADFRAME HAVING IMPROVED ADHESION AND SOLDERABILITY - A leadframe with a structure made of a base metal ( | 2008-09-18 |
20080224291 | PACKAGED SEMICONDUCTOR COMPONENTS HAVING SUBSTANTIALLY RIGID SUPPORT MEMBERS AND METHODS OF PACKAGING SEMICONDUCTOR COMPONENTS - Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die. | 2008-09-18 |
20080224292 | INTERPOSER STRUCTURE WITH EMBEDDED CAPACITOR STRUCTURE, AND METHODS OF MAKING SAME - A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening. | 2008-09-18 |
20080224293 | Method And Apparatus For Fabricating A Plurality Of Semiconductor Devices - A method includes the steps of providing a carrier comprising a plurality of cavities; placing at least one semiconductor element into each of the cavities; filling the plurality of cavities with a packaging material; and removing the carrier. | 2008-09-18 |
20080224294 | MULTI-CHIP PACKAGE WITH A SINGLE DIE PAD - A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage. | 2008-09-18 |
20080224295 | Package structure and stacked package module using the same - A package structure with chip embedded therein is disclosed, which comprises a circuit board having a first surface, an opposite second surface and a through cavity penetrating the circuit board, wherein the first surface of the circuit board has a plurality of first conductive pads and a plurality of wire bonding pads disposed thereon, and the second surface of the circuit board has a plurality of second conductive pads disposed thereon; and a chip embedded in the through cavity of the circuit board, wherein the gap between the through cavity and the chip is filled with a filling material, the chip has an active surface with a plurality of electrode pads and an inactive surface, and the electrode pads electrically connect to the wire bonding pads of the circuit board by a plurality of metal lines. The present invention further provides a package module using the aforementioned package structure. | 2008-09-18 |
20080224296 | Article and Panel Comprising Semiconductor Chips, Casting Mold and Methods of Producing the Same - A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer. | 2008-09-18 |
20080224297 | Apparatus comprising a device and method for producing it - An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure. | 2008-09-18 |
20080224298 | APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR COMPONENTS, METHODS OF MANUFACTURING APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR COMPONENTS - Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals. The apparatus further includes a second board having a first side laminated to the front side of the first board, a second side, openings through the second board aligned with individual package areas that define die cavities, and arrays of front contacts at the second side electrically coupled to the second backside terminals by interconnects extending through the first board and the second board. | 2008-09-18 |
20080224299 | BASE SUBSTRATE FOR CHIP SCALE PACKAGING - A base substrate for chip scale package includes a carrier member made of electrical conductive metals with a first through opening; an active member laminated by a base layer made of electrical conductive metal and an intermediate layer made of electrical insulating or dielectric material, the active member having a through opening with a diameter larger that the diameter of the through opening of the base metal member; the active member being coupled with the carrier member in such a way that the intermediate layer is adhered to an upper surface of the carrier member, and these through openings are aligned to define a shoulder around the through opening of the base metal plate. | 2008-09-18 |
20080224300 | Semiconductor Module With Semiconductor Chips And Method For Producing It - A semiconductor module has at least two semiconductor chips ( | 2008-09-18 |
20080224301 | Lead Structure for a Semiconductor Component and Method for Producing the Same - A lead structure for a semiconductor component includes: external leads for external connections outside a plastic housing composition, internal leads for electrical connections within the plastic housing composition, and a chip mounting island composed of the lead material. While leaving free contact pads of the internal leads, the top sides of the chip mounting island and the internal leads are equipped with nanotubes as an anchoring layer. The plastic housing composition is arranged in the interspaces between the nanotubes arranged on the internal leads, while an adhesive composition for the semiconductor chip is arranged in the interspaces between the nanotubes arranged on the chip mounting island. The adhesive composition and the plastic housing composition fill the interspaces in a manner free of voids. | 2008-09-18 |
20080224302 | Semiconductor Module - A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip. | 2008-09-18 |
20080224303 | Power Semiconductor Module - A power semiconductor module with its thermal resistance and overall size reduced. Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering. Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing. Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders. The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader. | 2008-09-18 |
20080224304 | Physical quantity sensor and semiconductor device having package and cover - A semiconductor device includes: a semiconductor chip; a package for accommodating the chip, wherein the package has a box shape with an opening and a bottom; and a cover for sealing the opening of the package. The semiconductor chip is disposed on the bottom of the package. The cover has a plate shape. The cover includes a protrusion, which is disposed at a center of the plate shape. The protrusion protrudes toward an outside of the package. | 2008-09-18 |
20080224305 | METHOD, APPARATUS, AND SYSTEM FOR PHASE CHANGE MEMORY PACKAGING - According to one embodiment, a die assembly is disclosed, comprising a package substrate and a plurality of stacked die on the package substrate, the plurality of stacked die including at least an uppermost die, a lowermost die, and at least one phase change memory die between the uppermost die and the lowermost die, wherein the uppermost die and lowermost die are non-functional spacer die. | 2008-09-18 |
20080224306 | MULTI-CHIPS PACKAGE AND METHOD OF FORMING THE SAME - The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein terminal pads are formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL. A third dielectric layer is formed under a second die. A second re-distribution conductive layer (RDL) is formed under the third dielectric layer. A fourth dielectric layer is formed under the second RDL. Conductive bumps are coupled to the first RDL and the second RDL. A surrounding material surrounds the second die. The second die is coupled to the first die through the first RDL, second RDL and the conductive bumps. | 2008-09-18 |
20080224307 | Semiconductor die with mask programmable interface selection - According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set of bumps is mask-programmably routed to one of the at least two groups of pads, thereby selecting the preferred interface for the semiconductor die. A non-preferred interface is not routed to any bumps on the active surface of the semiconductor die, thereby reducing bump count on the die. Each of the at least two groups of pads can be situated in a corresponding pad ring on the active surface of said semiconductor die. The at least two groups of pads can be laid out substantially inline. | 2008-09-18 |
20080224308 | SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF - Provided is a semiconductor device including a substrate, an electrode pad disposed on the substrate, an external terminal disposed on the electrode pad, a container extended from the electrode pad into the external terminal, and a conductive liquid disposed inside the container. The conductive liquid solidifies when exposed to air. When a crack forms in the external terminal, the container suppresses propagation of the crack. Further, if the crack breaches the container, the conductive liquid fills the crack, thereby minimizing further crack propagation and recovering the resistance characteristics of the external terminal prior to the crack formation. A method of forming a semiconductor device including a container having a conductive liquid is also provided. | 2008-09-18 |
20080224309 | SEMICONDUCTOR DEVICE MOUNTED ON SUBSTRATE, AND MANUFACTURING METHOD THEREOF - The connection technology is provided in which, at the time of mounting the semiconductor device on the substrate, the thermal load or the stress, which is imposed upon the semiconductor device, is little, a reliability of the semiconductor device is obtained, a stand-off of the semiconductor device mounted on the substrate can be secured appropriately, and moreover the short circuit hardly occurs between the pads of the semiconductor device mounted on the substrate. | 2008-09-18 |
20080224310 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: preparing a wiring board having a base substrate and wiring that is plated on surface with a plating metal; pressing a bump that is formed on the active side of the semiconductor chip against an end part of the wiring of the wiring board, thereby exfoliating the area surrounding the pressed portion of the wiring from the base substrate while keeping the end of the wiring bonded with the base substrate; melting the plating metal that is located on the end part of the wiring, thereby causing the plating metal and the bump to form an alloy that bonds the bump and the wiring and infiltrate the plating metal into a space between the wiring and the base substrate; and judging that the bump and the wiring are well bonded if the plating metal has infiltrated a space between the wiring and the base substrate so as to have an area, width or length of infiltration that exceeds a reference value. | 2008-09-18 |
20080224311 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises. | 2008-09-18 |
20080224312 | DEVICE HAVING A BONDING STRUCTURE FOR TWO ELEMENTS - A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding. | 2008-09-18 |
20080224313 | Method for forming a seed layer for damascene copper wiring, and semiconductor wafer with damascene copper wiring formed using the method - A method for forming a seed layer for damascene copper wiring is provided. The method comprises the step of forming a seed layer, during damascene copper wiring formation, using an electroless plating solution comprising a water-soluble nitrogen-containing polymer and glyoxylic acid as a reducing agent, wherein the weight-average molecular weight (Mw) of the water-soluble nitrogen-containing polymer is 1,000 to less than 100,000. Preferably, the electroless plating solution further comprises phosphinic acid. | 2008-09-18 |
20080224314 | Method and Apparatus for Forming a Noble Metal Layer, Notably on Inlaid Metal Features - A cap layer for a metal feature such as a copper interconnect on a semiconductor wafer is formed by immersion plating a more noble metal (e.g. Pd) onto the copper interconnect and breaking up, preferably by mechanical abrasion, loose nodules of the noble metal that form on the copper interconnect surface. The mechanical abrasion removes plated noble metal which is only loosely attached to the copper surface, and then continued exposure of the copper surface to immersion plating chemicals leads to plating at new sites on the surface until a continuous, well-bonded noble metal layer has formed. The method can be implemented conveniently by supplying immersion plating chemicals to the surface of a wafer undergoing CMP or undergoing scrubbing in a wafer-scrubber apparatus. | 2008-09-18 |
20080224315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device having a bonding wireless structure, a preform material is used for electrically connecting a metal plate serving as a connection with an electrode layer of a semiconductor chip. Thus, a multilayered metal layer needs to be provided in a junction part between the preform material and a first electrode layer, but has a problem of a variation in electrical characteristics and characteristic fluctuations in a temperature cycling test and the like. A metal layer mainly made of titanium is formed with a thickness of 1000 Å, as a bottom layer (a first metal layer in contact with an electrode layer of a semiconductor chip) in a multilayered metal layer with an electron impact heating deposition method. Thus, the film quality of the Ti layer is improved compared with the conventional structure, which minimizes variations in electrical characteristics and characteristic fluctuations in the multilayered metal layer. | 2008-09-18 |
20080224316 | Electronic device and method for producing electronic devices - An explanation is given of, inter alia, an electronic device ( | 2008-09-18 |
20080224317 | STABLE SILICIDE FILMS AND METHODS FOR MAKING THE SAME - Highly thermally stable metal silicides and methods utilizing the metal silicides in semiconductor processing are provided. The metal silicides are preferably nickel silicides formed by the reaction of nickel with substitutionally carbon-doped single crystalline silicon which has about 2 atomic % or more substitutional carbon. Unexpectedly, the metal silicides are stable to temperatures of about 900° C. and higher and their sheet resistances are substantially unaffected by exposure to high temperatures. The metal silicides are compatible with subsequent high temperature processing steps, including reflow anneals of BPSG. | 2008-09-18 |
20080224318 | System and method for integrated circuit arrangement having a plurality of conductive structure levels - An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate. | 2008-09-18 |
20080224319 | Micro electro-mechanical system and method of manufacturing the same - A micro electro-mechanical system, which can be stably formed so as to prevent sticking of a movable part and which has a narrow gap, and a method of manufacturing the same are provided. The micro electro-mechanical system includes at least one fixed electrode formed above a principal surface of a semiconductor substrate and at least one movable electrode formed on the principal surface. The at least one movable electrode includes the movable part separated from the principal surface and the at least one fixed electrode. The movable part is movable with respect to the principal surface and the at least one fixed electrode. The method of manufacturing the micro electromechanical system includes a sacrifical film formation step for forming a sacrifical film above the principal surface, an electrode layer formation step for forming an electrode layer above the principal surface so as to cover over the sacrifical film, an etching step for partially etching the electrode layer via a pattern so as to form the at least one electrode and the at least one fixed electrode, a sacrifical film removal step for removing the sacrifical film, and a conducting film formation step for forming a conducting film on surfaces of the at least one electrode and the at least one fixed electrode. | 2008-09-18 |
20080224320 | SILICON CHIP HAVING INCLINED CONTACT PADS AND ELECTRONIC MODULE COMPRISING SUCH A CHIP - A semiconductor chip has an active face in which an integrated circuit region is implanted. The chip includes an inclined lateral contact pad extending beneath the plane of the active face and electrically linked to the integrated circuit region. An electronic module includes a substrate having a cavity in which the chip is arranged. The module can be applied to the production of thin contactless micro-modules for smart cards and contactless electronic badges and tags. | 2008-09-18 |
20080224321 | CELL DATA FOR SPARE CELL, METHOD OF DESIGNING A SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a cell base design, when a circuit using a spare cell is corrected, a wiring length is shortened as much as possible, and the number of wiring layers which are affected by correction is reduced. Mask pattern data that expresses the configurations of a signal input terminal and a signal output terminal of a spare cell is set to mask pattern data of a wiring layer that is equal to or higher than a second wiring layer. As a result, the length of a wiring that is connected to the spare cell can be shortened as much as possible. | 2008-09-18 |
20080224322 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to offer a semiconductor device having a stacked layer structure and its manufacturing method that bring high yield and reliability. Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. As described above, a process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form. | 2008-09-18 |
20080224323 | Semiconductor Module With Semiconductor Chips And Method For Producing It - A semiconductor module ( | 2008-09-18 |
20080224324 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of one embodiment has a substrate, a semiconductor chip mounted over the substrate by flip-chip bonding, and a semiconductor chip provided over the semiconductor chip, wherein a space resides between the substrate and the semiconductor chip. | 2008-09-18 |
20080224325 | WIRING BOARD, MOUNTING STRUCTURE FOR ELECTRONIC COMPONENTS, AND SEMICONDUCTOR DEVICE - A wiring board includes a main surface where an electronic component is mounted in a face-down manner so that a surface of the electronic component having plurality of external connecting terminals faces the main surface of the wiring board, the electronic component being fixed to the wiring board by an adhesive; an insulating layer formed on the main surface where the electronic component is mounted; an opening part formed in the insulating layer so that a plurality of adjacent wiring patterns are commonly and partially opened, the adjacent wiring patterns having electrodes where electrodes of the electronic component are connected; wherein an outer periphery of the opening part situated at a center side of the wiring board is formed in an oblique direction against extending directions of the wiring patters. | 2008-09-18 |
20080224326 | Chip structure with bumps and testing pads - A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad. | 2008-09-18 |
20080224327 | Microelectronic substrate including bumping sites with nanostructures - A microelectronic substrate and a package including the substrate. The substrate comprises: a wafer; circuitry disposed within the wafer and including a plurality of bonding pads; and a plurality of bumping sites disposed on respective ones of the bonding pads, each of the bumping sites comprising a nanolayer including columnar nanostructures. | 2008-09-18 |
20080224328 | TEMPORARY CHIP ATTACH USING INJECTION MOLDED SOLDER - An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested can then be attached to the IMS column with C4 solder. A slight reflow is then applied to the die, allowing some of the C4 to melt, and form an electrical connection with the corresponding IMS column. After testing, the die can be removed along with the C4 from the IMS column or permanently attached the substrate by performing a full reflow of the C4. | 2008-09-18 |
20080224329 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die. | 2008-09-18 |
20080224330 | Power delivery package having through wafer vias - An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and ground routings, and a substrate attached to the semiconductor die, the substrate having power and ground leads connected to the through wafer vias for transferring power from the substrate to the semiconductor die. | 2008-09-18 |
20080224331 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electronic device includes: a semiconductor chip that includes an integrated circuit, a plurality of electrodes electrically connected to the integrated circuit, and a passivation film formed in a manner that at least a portion of each of the plurality of electrodes is exposed; a resin layer that is formed on the passivation film; a plurality of wirings, each of the plurality of wirings extending from a top surface of each of the plurality of electrodes to a top surface of the resin layer and electrically connected to each of the plurality of electrodes, respectively; a wiring substrate that has a wiring pattern opposing to and electrically connected to portions of the plurality of wirings above the resin layer; and a hardened adhesive resin that is placed between the semiconductor chip and the wiring substrate, wherein the adhesive resin internally has a residual stress that is generated by contraction at the time of hardening the adhesive resin, and a portion of the adhesive resin is disposed between a portion of the resin layer between adjacent ones of the wirings and the wiring substrate. | 2008-09-18 |
20080224332 | Transistor circuit formation substrate and method of manufacturing transistor - A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the testing of a circuit involving a transistor can also be costly, time consuming and a barrier towards efficient circuit development and testing. Accordingly, the present invention provides a pre-fabricated, general-purpose pattern comprising an array of conductive islands. The pattern is used as a source and a drain terminal for the formation of a thin-film transistor and as a conductive source for the formation of other electrical components upon the array. | 2008-09-18 |
20080224333 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed that includes a wiring board having a via formed therein; a semiconductor element provided on the wiring board; a resist layer covering a surface of the wiring board, the resist layer having an opening in a part thereof positioned on the via; and a sealing resin covering the surface of the via in the opening and the resist layer, and sealing the semiconductor device. | 2008-09-18 |
20080224334 | Molded Beam for Optoelectronic Sensor Chip Substrate - A substrate on which a plurality of epoxy over molded integrated circuit dies are formed includes a beam formed on the substrate for providing stiffness to the substrate. The beam includes structure having a cross-sectional shape, for example, substantially in the shape of a trapezoid, “T” or “L”, and may be formed on the top or bottom surface of the substrate. | 2008-09-18 |
20080224335 | CARBURETOR FOR STRATIFIED CHARGE TWO-CYCLE ENGINE - A carburetor for a stratified charge two cycle engine with a choke bore, venturi, and throttle bore configuration matching an irregularly shaped choke valve. The trailing and leading edges of the choke and throttle valves, respectively, preferably overlap during wide open throttle operation to separate a single intake passage bore into an air intake passage above the choke and throttle valves and an air/fuel intake passage below the choke and throttle valves. The choke valve is preferably bent to minimize operational rotation and limit fuel spit back. | 2008-09-18 |
20080224336 | WATER SPIKE SYSTEM - A kit for coupling a container holding a liquid to a fluid path of a humidifier is disclosed. The kit includes a spike configured to pierce the container and to pass the liquid from the container to a vent through a tube. The vent is configured to vent gas from the liquid while retaining the liquid. The vent has a vent body including an inlet configured for coupling to the tube to receive the liquid from the tube and an outlet configured to pass the liquid to the humidifier. A cap opening is positioned to vent the gas. A filter is positioned over the cap opening to prevent the escape of the liquid therethrough. A cap is coupled to the vent body over the cap opening and has at least one opening therein to allow passage of gas from the opening to atmosphere. | 2008-09-18 |
20080224337 | DIFFUSER ASSEMBLY WITH BUOYANCY VESSEL - A diffuser assembly with a buoyancy vessel and a chamber for buoyantly raising the diffuser assembly for maintenance work. The diffuser assembly has a support structure, diffusers connected to the frame, and a buoyancy vessel positioned on the frame, capable of alternating between a state of buoyancy or ballast. | 2008-09-18 |
20080224338 | METHOD FOR PRODUCING A PHOTOCHROMIC PLASTIC ARTICLE - A method for producing a photochromic synthetic resin object, comprising: | 2008-09-18 |
20080224339 | Prismatic Films for Optical Applications - The invention relates to coextruded foils with prism structure, to a process for production of coextruded foils with prism structure and to uses. | 2008-09-18 |
20080224340 | Method of making a polarizing sheet and method of lamination - A method of making a polarizing sheet and a related method of lamination are disclosed. The method of making a polarizing sheet includes steps of forming a surface-modified polarizer having carboxylic groups from a polyvinyl alcohol (PVA) film, and then performing a thermocompression lamination to laminate the polarizer with at least one protective film having hydroxyl groups on a surface thereof to form a polarizing sheet. | 2008-09-18 |
20080224341 | PROCESS AND APPARATUS FOR COMPOUNDING AND INJECTION-MOULDING DESICCANT-FILLED POLYMERS - Disclosed is an injection moulding machine, comprising an extruder for continuously producing a melt of a desiccant-filled polymer; at least one injection device fluidly connected with the extruder by a first conduit to receive melt and including an injection ram movable to a forward position for injection of melt into an injection mould and a rear position for introduction of melt into the injection device; characterized in that the injection moulding machine further comprises a sensor which allows determination of the viscosity or melt flow index of the desiccant-filled polymer. Further disclosed is a method of operating such a compounder-type injection moulding machine. | 2008-09-18 |
20080224342 | Method For Forming Two-Tone Parts For Automotive Interior Applications - The present invention is directed at an improved method for forming two-tone trim panels for automobiles and the like, wherein the color demarcation line between color regions of the panel skin may be hidden in a narrow groove or joint. The groove in the formed skin may be formed by the expansion pressure of foam conforming the skin to a narrow projection in a foam mold. Alternatively, a narrow groove may be formed by skiving or embossing along the color demarcation line. | 2008-09-18 |
20080224343 | OPEN CERAMIC MEDIA STRUCTURE AND METHOD OF MANUFACTURING - A method of producing a porous ceramic media structure is provided. The method comprises preparing an aqueous solution that comprises ceramic fibers in a liquid carrier, adding a pore-forming, fibrous material to the aqueous solution, drying the aqueous solution to form a ceramic web, and removing the fibrous material from the ceramic web to thereby increase the porosity of the ceramic web. | 2008-09-18 |
20080224344 | Method of making a cemented carbide body - The present invention relates to a method of making a cemented carbide body. | 2008-09-18 |
20080224345 | Methods of manufacturing hot mix on site utilizing a composition of pellets of tacky, deformable material dispersed within a flowable fine material - Methods of manufacturing hot mix on site utilizing a composition of discrete substances that are capable of being mixed together to form a composite material are disclosed. The composition includes a plurality of pellets of a tacky, deformable material at an ambient temperature dispersed within a flowable fine material. Stone aggregate is placed in a mixing chamber that has been moved within proximity of the location where the hot mix is to be used. At least a portion of the stone aggregate is heated in the mixing chamber to a temperature sufficient to soften the pellets of the tacky, deformable material. The composition of discrete substances is added into the mixing chamber. The mixture of the composition of discrete substances and the stone aggregate is agitated until the pellets of a tacky, deformable material soften and uniformly coat the stone aggregate. | 2008-09-18 |
20080224346 | Method and Apparatus for Producing Plastic Film | 2008-09-18 |
20080224347 | METHOD FOR MANUFACTURING KEYPAD - In a method for manufacturing compact keypad, a first molding die with bottom surface of smooth face, matted face or patterned layer is prepared. Colloid is injected into the first molding die and a first carrier covers the surface of the colloid. A rolling wheel presses the first carrier and the colloid evenly into the first molding die. The colloid is cured by UV light to form a keypad layer attached on the first carrier. A background color layer, a functional color layer and a textual color layer are formed on the first carrier. A second carrier is prepared and a reflection layer is printed on the surface of the second carrier. The second carrier and silicon rubber are placed into a second molding die and thermally pressed therein to form a resilient layer. The resilient layer is adhered with the keypad layer to form the keypad panel. | 2008-09-18 |
20080224348 | PRESS-MOLDING APPARATUS AND WORK-CONVEYING METHOD IN THE APPARATUS - There are provided a press-molding apparatus and a work-conveying method, which are capable of restraining oxygen from entering the molding apparatus when a work, such as a mold or a material, is carried into the molding apparatus. | 2008-09-18 |
20080224349 | Methods for Manufacturing Multi-Layer Rotationally Molded Parts - This invention relates generally to methods of rotationally molding multi-layer parts. More particularly, in certain embodiments, the invention relates to methods of manufacturing a part having an interior layer of polymerized macrocyclic polyester oligomer and an exterior layer of a substantially non-oligomeric polymer. The invention also relates to methods of manufacturing a part with a scratch resistant surface. | 2008-09-18 |
20080224350 | Fluid dispensing closure and method of manufacturing the same - A method for creating spout assembly for use with a container having an internal chamber in communication with a predefined opening includes molding steps. A hollow body is molded of a first material and includes a passage therethrough. A base member of a second material is molded over the hollow body in a mold using at least a part of the hollow body as at least a part of the mold, The base member is configured to be secured to the container and is configured to cover the predefined opening. The step of molding the base member over the hollow body is carried out such that the hollow body is rotatably mounted to the base member to be movable between an open position and a closed position upon completion of the molding step. | 2008-09-18 |
20080224351 | Method and Apparatus for Incrementally Stretching a Web - A method and apparatus is provided which uses activation members for incrementally stretching a web at a low strain rate. The activation members include an activation belt and a single activation member wherein the activation belt and single activation member comprise a plurality of teeth and grooves that complement and engage one another at a depth of engagement in a deformation zone. The depth of engagement can be controlled to increase linearly over at least a portion of the deformation zone such that a web interposed between the activation belt and the single activation member in the deformation zone is incrementally stretched at a low rate of strain. | 2008-09-18 |
20080224352 | SOLUTION CASTING PROCESS AND SYSTEM - In a solution casting system, a casting die causes dope containing polymer and solvent to flow. A casting support belt is disposed movably under the casting die, for forming cast film from the dope being cast. A stripping roller strips the cast film having a self-supporting property to form self-supporting cast film. A first dryer stretches the self-supporting cast film, and while the self-supporting cast film is stretched, applies first gas with temperature T | 2008-09-18 |
20080224353 | Hydraulic Valve of Molding System - Disclosed is: (i) a molding system having a hydraulic valve, (ii) a molding system having: (a) an extruder, (b) a hydraulic circuit, and (c) a hydraulic valve, (iii) a hydraulic valve of a molding system, (iv) a method of a molding system having a hydraulic valve, and (v) a valve controller performing a method of a molding system having a hydraulic valve. The hydraulic valve includes: (i) a valve sleeve that is configured to convey a pressurized hydraulic fluid, and (ii) a valve spool that is movable relative to the valve sleeve, once the valve spool is made to move from a valve-closed position to a valve-opened position, the valve spool is imparted with a running start before the pressurized hydraulic fluid is permitted to flow out of the valve sleeve. | 2008-09-18 |
20080224354 | Polyethylene Composition For Injection Moulding With Improved Stress Crack/Stiffness Relation and Impact Resistance - The present invention relates to a polyethylene composition wherein (i) the composition has an MFR | 2008-09-18 |
20080224355 | METHOD FOR BOW REDUCTION OF A COMPOSITE SHEET - A method for bow reduction of a composite sheet includes providing a bow composite sheet including a top sheet and a bottom sheet, the top sheet including a non-metal and the bottom sheet including a metal, and either placing the bow composite sheet on a continuous transportation unit including a cooling unit to substantially eliminate the bow through the cooling unit, or placing the bow composite sheet on a fixed cooling unit spraying a cooling fluid to substantially eliminate the bow. | 2008-09-18 |
20080224356 | Method for Producing a Matrix Used for Producing Decorating Dressing - The invention relates to a process for the production of a die for the production of a surface-structured coating which can be bonded to a sheet-like substrate, in particular a leather or a textile material, and which is formed by application of a liquid plastic material to the surface of the die and subsequent solidification of the plastic material, the die having a surface structure corresponding to the surface structure of the coating, wherein the surface structure of the die is produced by laser engraving. | 2008-09-18 |
20080224357 | Method for Producing Foamed Slabs - A process for producing foam moldings from prefoamed foam particles which have a polymer coating under pressure in a mold in the absence of steam, and also foam moldings produced therefrom and their use. | 2008-09-18 |
20080224358 | Nano-Molding Process - A nano-molding process including an imprint process that replicates features sizes less than 7 nanometers. The nano-molding process produces a line edge roughness of the replicated features that is less than 2 nanometers. The nano-molding process including the steps of: a) forming a first substrate having nano-scale features formed thereon, b) casting at least one polymer against the substrate, c) curing the at least one polymer forming a mold, d) removing the mold from the first substrate, e) providing a second substrate having a molding material applied thereon, f) pressing the mold against the second substrate allowing the molding material to conform to a shape of the mold, g) curing the molding material, and h) removing the mold from the second substrate having the cured molding material revealing a replica of the first substrate. | 2008-09-18 |
20080224359 | MANUFACTURING METHOD OF THIN KEYPAD ASSEMBLY - In a method of manufacturing a thin keypad of a keypad panel having a smooth surface, a mist surface or a lines layer, the method includes the steps of: preparing a mold with an internal bottom surface of a coarse surface, a smooth surface or a lines surface; applying an adhesive into the mold and coating a carrier onto the surface of the adhesive; rolling the surface of the carrier by a roller to level the adhesive in the mold; performing a ultraviolet projection to cure the adhesive to form a keypad layer on the carrier; filming a ground color layer, a function color layer and a font color layer sequentially on the carrier as the background of the keypad panel; and hot pressing and combining the keypad layer and silicon to produce the keypad panel. | 2008-09-18 |
20080224360 | METHOD AND DEVICE FOR MANUFACTURING A UNITARY CAUL SHEET - A method and device are provided for manufacturing a unitary caul sheet to be used in creating a composite material fuselage for an airplane. Specifically, a generally tubular shaped tool having a hollow interior cavity defining a fuselage IML surface is provided. In the method, a caul sheet material such as polyurea is applied to the IML surface before an armature is inserted into the interior cavity of the tool. Then, a filler material is introduced between the armature and the caul sheet material. Further, steam is injected to form the filler material into an infrastructure. Then, the caul sheet material is cured before the tool is removed from the caul sheet material to expose the caul sheet to receive composite material. | 2008-09-18 |
20080224361 | IN MOLD MANUFACTURE OF AN OBJECT WITH EMBEDDED DISPLAY PANEL - This invention relates to an object having a display panel embedded in its top surface and processes for its manufacture. The process comprises the steps of: forming an in-mold display transfer film or foil which comprises a temporary carrier layer, a release layer, a display panel, an adhesive layer and optionally a durable layer; feeding said in-mold display transfer film or foil into a mold with the temporary carrier film in contact with the inner surface of the mold; forming an object in the mold and transferring the in-mold display transfer film or foil onto the object; removing the object formed from the mold; and simultaneously removing both temporary carrier layer and release layer. | 2008-09-18 |
20080224362 | DEVICE FOR TREATING CONTAINERS | 2008-09-18 |
20080224363 | Method For Manufacturing a Plastic Fuel Tank - Method for manufacturing a plastic fuel tank by moulding a parison in which, during the moulding operation, a pipe ( | 2008-09-18 |
20080224364 | METHOD FOR FLEXING A SUBSTRATE DURING PROCESSING - A method is provided to cause deformation of a substrate during processing of the substrate. The method comprises supporting a substrate on a substrate support in a vacuum chamber for processing; providing backside gas through inlet ports of each of a plurality of groups of ports lying in a respective plurality of areas across the substrate support to a space between the substrate support and the substrate, each of said areas of the substrate support having at least one backside gas inlet port connected to a supply of backside gas and at least one outlet port connected to a vacuum exhaust system; and separately controlling the pressure of the backside gas at different ones of the ports of the plurality to control separately, in areas around the respective ones of said ports, the local pressure force exerted on the backside of the substrate, by separately dynamically controlling at least one valve affecting gas flow to a port of each of said areas while separately dynamically controlling at least one other valve affecting gas flow from the remaining plurality of ports of each of said areas surrounding said port to which gas is introduced. | 2008-09-18 |