37th week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110221008 | Semiconductor Packaging and Fabrication Method Using Connecting Plate for Internal Connection - A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding. | 2011-09-15 |
20110221009 | METHOD AND APPARATUS FOR REDUCING GATE RESISTANCE - An apparatus has a semiconductor device that includes: a semiconductor substrate having a channel region, a high-k dielectric layer disposed at least partly over the channel region, a gate electrode disposed over the dielectric layer and disposed at least partly over the channel region, wherein the gate electrode is made substantially of metal, and a gate contact engaging the gate electrode at a location over the channel region. A different aspect involves a method for making a semiconductor device that includes: providing a semiconductor substrate having a channel region, forming a high-k dielectric layer at least partly over the channel region, forming a gate electrode over the dielectric layer and at least partly over the channel region, the gate electrode being made substantially of metal, and forming a gate contact that engages the gate electrode at a location over the channel region. | 2011-09-15 |
20110221010 | SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY - A semiconductor includes a plurality of active regions that are separated from each other on a substrate by a device isolation layer and extend in a first direction, the active regions having two opposite ends and a center region; wordlines that are buried in and cross the active regions and extend in a second direction, which is different from the first direction, wherein a wordline that crosses an active region crosses between one of the two opposite ends and the center region of the active region; first contact plugs on the two opposite ends of the active regions, each contact plug overlapping a border between the active region and the device isolation layer; and second contact plugs formed on the first contact plugs. | 2011-09-15 |
20110221011 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING THE SAME - The invention relates to a transistor, in which the electric field is reduced in critical areas using field plates, thus permitting the electric field to be more uniformly distributed along the component. The aim of the invention is to provide a transistor and a production method therefor, wherein the electric field in the active region is smoothed (and field peaks are reduced), thus allowing the component to be made more simply and cost-effectively. The semiconductor component according to the invention has a substrate ( | 2011-09-15 |
20110221012 | HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF - Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen. | 2011-09-15 |
20110221013 | MICROELECTROMECHANICAL DEVICE INCLUDING AN ENCAPSULATION LAYER OF WHICH A PORTION IS REMOVED TO EXPOSE A SUBSTANTIALLY PLANAR SURFACE HAVING A PORTION THAT IS DISPOSED OUTSIDE AND ABOVE A CHAMBER AND INCLUDING A FIELD REGION ON WHICH INTEGRATED CIRCUITS ARE FORMED, AND METHODS FOR FABRICATING SAME - There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide. | 2011-09-15 |
20110221014 | PRESSURE SENSOR AND METHOD FOR MANUFACTURING THE PRESSURE SENSOR - A pressure sensor of the present invention includes a substrate inside which a reference pressure chamber is formed, a closing body filled in a through-hole formed in the substrate such that the closing body penetrates through a portion between the surface of the substrate and the reference pressure chamber, and hermetically closes the reference pressure chamber, and a strain gauge provided inside the substrate between the surface of the substrate and the reference pressure chamber, and the electric resistance thereof being capable of changing by strain deformation of the substrate. | 2011-09-15 |
20110221015 | METHOD FOR PRODUCING AN ELECTRO-MECHANICAL MICROSYSTEM - A production method with release of movable mechanical parts of an electro-mechanical microsystem is disclosed. The method is characterized in that porous zones are formed on the front face of a first water of a semiconductor material. Patterns of a material able to constitute the movable mechanical parts of the electro-mechanical microsystem are then formed on the front face of the first water at the level of the porous zones and encapsulated in a sacrificial layer. Then a layer of a material withstanding an attack by a solvent of the sacrificial layer is deposited. The release of the movable mechanical parts is then executed by the rear face of the first water, through the porous zones, using a solvent of the sacrificial layer. | 2011-09-15 |
20110221016 | FLUX-CLOSED STRAM WITH ELECTRONICALLY REFLECTIVE INSULATIVE SPACER - Flux-closed spin-transfer torque memory having a specular insulative spacer is disclosed. A flux-closed spin-transfer torque memory unit includes a multilayer free magnetic element including a first free magnetic layer anti-ferromagnetically coupled to a second free magnetic layer through an electrically insulating and electronically reflective layer. An electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic element from a reference magnetic layer. | 2011-09-15 |
20110221017 | PHOTOSENSITIVE RESIN COMPOSITION, PHOTOSENSITIVE ADHESIVE FILM, AND LIGHT-RECEIVING DEVICE - A photosensitive resin composition includes (A) an alkali-soluble resin, (B) an epoxy resin, and (C) a photopolymerization initiator, the epoxy resin (B) being an epoxy resin having a naphthalene skeleton and/or an epoxy resin having a triphenylmethane skeleton. A semiconductor device including a semiconductor wafer, a transparent substrate, and a spacer formed by a photosensitive adhesive film produced using the photosensitive resin composition does not suffer from condensation of dew. A light-receiving device having excellent reliability can also be obtained. | 2011-09-15 |
20110221018 | Electronic Device Package and Methods of Manufacturing an Electronic Device Package - An electronic device package comprises a substrate | 2011-09-15 |
20110221019 | Silicon-Based Schottky Barrier Detector With Improved Responsivity - A planar, waveguide-based silicon Schottky barrier photodetector includes a third terminal in the form of a field plate to improve the responsivity of the detector. Preferably, a silicide used for the detection region is formed during a processing step where other silicide contact regions are being formed. The field plate is preferably formed as part of the first or second layer of CMOS metallization and is controlled by an applied voltage to modify the electric field in the vicinity of the detector's silicide layer. By modifying the electric field, the responsivity of the device is “tuned” so as to adjust the momentum of “hot” carriers (electrons or holes, depending on the conductivity of the silicon) with respect to the Schottky barrier of the device. The applied potential functions to align with the direction of momentum of the “hot” carriers in the preferred direction “normal” to the silicon-silicide interface, allowing for an increased number to move over the Schottky barrier and add to the generated photocurrent. | 2011-09-15 |
20110221020 | WAFER LENS ARRAY AND METHOD FOR MANUFACTURING THE SAME - A wafer lens array comprising a plurality of lens sections arranged one-dimensionally or two-dimensionally, a substrate section connecting the lens sections, and gap sections, wherein the lens surfaces in the lens section each have one or more curved surfaces; the gap section is a part projecting from outside than the inner edge of the lens section; and the inner surfaces of the gap sections are spread from a side near the lens section to the other side. | 2011-09-15 |
20110221021 | Solid state image pickup device and method of producing solid state image pickup device - Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed. | 2011-09-15 |
20110221022 | OPTICAL MEMBER, SOLID-STATE IMAGING DEVICE, AND MANUFACTURING METHOD - An optical member including high refractive index layers having a great refractive index and low refractive index layers having a small refractive index, which are each relatively thin as compared with an optical length, disposed alternately in the lateral direction as to an optical axis. Each width of the high refractive index layers and the low refractive index layers is equal to or smaller than the wavelength order of incident light. | 2011-09-15 |
20110221023 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING PATTERNED RADIATION BLOCKING ON A SEMICONDUCTOR DEVICE - Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer. | 2011-09-15 |
20110221024 | ALUMINUM INDIUM ANTIMONIDE FOCAL PLANE ARRAY - In one embodiment, a detector includes an Al | 2011-09-15 |
20110221025 | ALUMINUM INDIUM ANTIMONIDE FOCAL PLANE ARRAY - In one embodiment, a detector includes an Al | 2011-09-15 |
20110221026 | PHOTOVOLTAIC DEVICE INCLUDING A SUBSTRATE OR A FLEXIBLE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a photovoltaic device. The photovoltaic device of the present invention includes: a first electrode and a second electrode, which are sequentially placed on a substrate; a first photoelectric conversion layer being placed between the first electrode and the second electrode, and including an n-type semiconductor layer, an intrinsic semiconductor layer and a p-type semiconductor layer, which are sequentially stacked; a second photoelectric conversion layer being placed between the first photoelectric conversion layer and the second electrode, and including an n-type semiconductor layer, an intrinsic semiconductor layer and a p-type semiconductor layer, which are sequentially stacked; and light transmitting particles placed within the second electrode. | 2011-09-15 |
20110221027 | Using Alloy Electrodes to Dope Memristors - Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode ( | 2011-09-15 |
20110221028 | SEMICONDUCTOR DEVICE - In a lamination type semiconductor device, in the case where a power source plane is wrapped by a closed area to prevent the needless radiation from being leaked to the outside of the semiconductor package, a planar conductor for shield having an area intersecting with the respective layers is required. However, in a device for manufacturing the lamination type semiconductor device, a process for manufacturing the above-mentioned conductor cannot be realized ordinarily. In order to make the process possible, it is required to modify or replace a manufacturing apparatus of the semiconductor device, and accordingly a manufacturing cost will be considerably increased. In the present invention, a guard ring is arranged in an surrounding area of a power source plane. The guard ring is connected to a GND plane of another layer through a via. Consequently, the RF radiation occurs between the power source plane and the guard ring. | 2011-09-15 |
20110221029 | BALANCED ADAPTIVE BODY BIAS CONTROL - Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator. | 2011-09-15 |
20110221030 | CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD - A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. | 2011-09-15 |
20110221031 | SYSTEM AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ANTI-FUSE IN CONJUNCTION WITH A TUNGSTEN PLUG PROCESS - A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse. | 2011-09-15 |
20110221032 | BIAS CIRCUIT AND METHOD OF MANUFACTURING THE SAME - A bias circuit according to the present invention includes a resistor layer | 2011-09-15 |
20110221033 | HIGH POWER SEMICONDUCTOR DEVICE FOR WIRELESS APPLICATIONS AND METHOD OF FORMING A HIGH POWER SEMICONDUCTOR DEVICE - A high power semiconductor device for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate including an active area of the high power semiconductor device, contact regions formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer formed over a part of the semiconductor substrate, a lead for providing an external connection to the high power semiconductor device and an impedance matching network formed on the semiconductor substrate between the active area of the high power semiconductor device and the lead. The impedance matching network includes conductor lines formed on the dielectric layer. The conductor lines are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching. | 2011-09-15 |
20110221034 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a peripheral circuit region including a wiring layer having wiring patterns, a cavity formed in a non-wiring region between the wiring patterns of the wiring layer, and an insulating film forming at least a part of a wall defining the cavity, and a memory cell region. | 2011-09-15 |
20110221035 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING A METAL-INSULATOR-METAL CAPACITOR AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit is fabricated by producing metallization levels in insulating regions, the insulating region being formed of a first material having a first dielectric constant. At least one metal-insulator-metal capacitor is formed by providing metal electrodes in the metallization level, and locally replacing the first material, which is located between the metal electrodes, with a second material having a second dielectric constant greater than the first dielectric constant. | 2011-09-15 |
20110221036 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC | 2011-09-15 |
20110221037 | Electronic Component Arrangement Comprising a Varistor and a Semiconductor Component - An electric component arrangement is described, comprising a semiconductor component ( | 2011-09-15 |
20110221038 | Electrically Actuated Devices - An electrically actuated device comprises an active region ( | 2011-09-15 |
20110221039 | DEFECT CAPPING FOR REDUCED DEFECT DENSITY EPITAXIAL ARTICLES - An epitaxial article includes a substrate having a substrate surface having a substrate surface composition including crystalline defect or amorphous regions and crystalline non-defect regions. The crystalline defect or amorphous regions are recessed from the substrate surface by surface recess regions. A capping material fills the surface recess regions to provide capped defects that extend from a top of the defect regions to the substrate surface. The capping material is compositionally different from the substrate surface composition. An epitaxial layer over the substrate surface provides an average crystalline defect density in at least one area having a size ≧0.5 μm | 2011-09-15 |
20110221040 | Composite Semiconductor Substrates for Thin-Film Device Layer Transfer - Described herein are composite semiconductor substrates for use in semiconductor device fabrication and related devices and methods. In one embodiment, a composite substrate includes: (1) a bulk silicon layer; (2) a porous silicon layer adjacent to the bulk silicon layer, wherein the porous silicon layer has a Young's modulus value that is no greater than 110.5 GPa; (3) an epitaxial template layer, wherein the epitaxial template layer has a root-mean-square surface roughness value in the range of 0.2 nm to 1 nm; and (4) a set of silicon nitride layers disposed between the porous silicon layer and the epitaxial template layer. | 2011-09-15 |
20110221041 | Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die - A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. | 2011-09-15 |
20110221042 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A wafer structure ( | 2011-09-15 |
20110221043 | Semiconductor device and manufacturing method therefor - Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region ( | 2011-09-15 |
20110221044 | TUNGSTEN BARRIER AND SEED FOR COPPER FILLED TSV - Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described. | 2011-09-15 |
20110221045 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device with a high breakdown voltage yield of a bipolar transistor and a high bandwidth and quantum efficiency of a light receiving element. An optical semiconductor device includes monolithically integrated transistor and light receiving element. The light receiving element includes a p-type semiconductor layer, an n-type epitaxial layer formed on the p-type semiconductor layer, and an n-type diffusion layer formed on the n-type epitaxial layer. An n-type impurity concentration of the n-type diffusion layer is 3×10 | 2011-09-15 |
20110221046 | SEMICONDUCTOR ASSEMBLY PACKAGE HAVING SHIELDING LAYER AND METHOD THEREFOR - A semiconductor assembly package includes a package unit, a shielding layer and a protection layer. The package unit includes a semiconductor assembly, a daughter substrate and a mold compound. The semiconductor assembly is disposed on and electrically connected to the daughter substrate. The daughter substrate includes a metal portion grounded. The mold compound encapsulates the semiconductor assembly and the daughter substrate to expose the metal portion out of the package unit. The shielding layer is applied to the package unit and electrically connected to the metal portion, to provide electromagnetic shielding for the semiconductor assembly. The non-conductive protection layer is covered on the shielding layer. | 2011-09-15 |
20110221047 | FLIP CHIP PACKAGE STRUCTURE WITH HEAT DISSIPATION ENHANCEMENT AND ITS APPLICATION - A flip chip package structure includes a chip placed under a lead frame, a bump on the upper surface of the chip that is electrically connected to the lead of the lead frame, and a backside metal on the lower surface of the chip that is exposed outside an encapsulant encapsulating the chip and a portion of the lead frame. | 2011-09-15 |
20110221048 | Package Having Spaced Apart Heat Sink - An integrated circuit (IC) package that includes a lead frame, and a die affixed to a first surface of a pad of the lead frame. The die is wire bonded to the lead frame. The package includes a heat sink spaced apart from a second surface of the pad, where the second surface opposes the first surface. Molding compound encapsulates the lead frame and the die. The molding compound is disposed between the heat sink and the second surface of the pad and is enabled access between the heat sink and the second surface through protruding features disposed on the heat sink, the second surface, and/or some combination of the two. | 2011-09-15 |
20110221049 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield. | 2011-09-15 |
20110221050 | Electronic device, relay member, and mounting substrate, and method for manufacturing the electronic device - The relay member is at least partly positioned between the semiconductor chip and lead in the plan view, and metal pieces insulated from one another are arranged on the surface. At least either of the first wire and the second wire has their respective other ends and joined to at least one of the metal pieces arranged on the surface of the relay member. Also, the first wire and the second wire have their respective other ends and joined to each other at that part of the relay member which is between the semiconductor chip and the lead. The foregoing structure is highly reliable and versatile for wire connection. | 2011-09-15 |
20110221051 | LEADFRAME BASED MULTI TERMINAL IC PACKAGE - A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound. | 2011-09-15 |
20110221052 | LEAD FRAME FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING OF THE SAME - Provided are a semiconductor device lead frame and a method of manufacturing of the same that improve adhesive properties between plating layers when a plurality of plating layers are laminated, that control deterioration in wire bonding properties during the manufacturing process of a semiconductor device and worsening of solderability during packaging, and that effectively reduce manufacturing cost. Specifically, the lead frame ( | 2011-09-15 |
20110221053 | PRE-PROCESSING TO REDUCE WAFER LEVEL WARPAGE - A method for packaging a stacked integrated circuit (IC) includes pre-processing the stacked IC before releasing the stacked IC from the carrier wafer. Pre-processing reduces wafer warpage and simplifies the packaging process by dicing materials separately. Pre-processing may be performed on the first tier wafer of a stacked IC during manufacturing to partially or completely dice the first tier wafer into first tier dies before release from the carrier wafer. Pre-processing may also be performed by laser cutting the mold compound surrounding the first tier wafer and second tier dies before releasing the stacked IC from the carrier wafer. Openings in the first tier wafer and/or mold compound allows balancing of stresses in the packaging process and reduction of wafer warpage. | 2011-09-15 |
20110221054 | Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP - A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure. | 2011-09-15 |
20110221055 | Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. | 2011-09-15 |
20110221056 | ELECTRODE STRUCTURE AND MICRODEVICE PACKAGE PROVIDED THEREWITH - An electrode structure has a Cu electrode that provided in a surface of a substrate, a diffusion preventing film that is made of a material in which a diffusion coefficient of Sn is equal to or lower than 3×10 | 2011-09-15 |
20110221057 | Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. | 2011-09-15 |
20110221058 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first conductive layer is formed in the first patterned photoresist layer. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed over the substrate. A second conductive layer is formed in the second patterned photoresist layer. The height of the second conductive layer, for example 25 micrometers, is greater than the height of the first conductive layer which is 5 micrometers. The first and second conductive layers are interposed between each other close together to minimize pitch and increase I/O count while maintaining sufficient spacing to avoid electrical shorting after bump formation. An interconnect structure is formed over the first and second conductive layers. | 2011-09-15 |
20110221059 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A QFN package includes a chip-mounting base; electrically connecting pads disposed around the periphery of the chip-mounting base, the bottom surfaces of the chip-mounting base and the electrically connecting pads being covered by a copper layer; a chip mounted on the top surface of the chip-mounting base; bonding wires electrically connecting to the chip and the electrically connecting pads; an encapsulant encapsulating the chip-mounting base, the electrically connecting pads, the chip and the bonding wires while exposing the copper layer; and a dielectric layer formed on the bottom surfaces of the encapsulant and the copper layer and having a plurality of openings exposing a portion of the copper layer. The copper layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the interface between the chip-mounting base, the electrically connecting pads and the dielectric layer, thereby avoiding solder extrusion and enhancing product yield. | 2011-09-15 |
20110221060 | Process for Fabricating Electronic Components Using Liquid Injection Molding - A process for fabricating an electronic component includes a liquid injection molding method for overmolding a semiconductor device. The liquid injection molding method includes: i) placing the semiconductor device in an open mold, ii) closing the mold to form a mold cavity, iii) heating the mold cavity, iv) injection molding a curable liquid into the mold cavity to overmold the semiconductor device, v) opening the mold and removing the product of step iv), and optionally vi) post-curing the product of step v). The semiconductor device may have an integrated circuit attached to a substrate through a die attach adhesive. | 2011-09-15 |
20110221061 | ANODE FOR AN ORGANIC ELECTRONIC DEVICE - There is provided an anode for an organic electronic device. The anode has (a) a first layer which is a conducting inorganic material and (b) a second ultrathin layer which is a metal oxide | 2011-09-15 |
20110221062 | METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 2011-09-15 |
20110221063 | Manufacturing Method of Semiconductor Device - A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer. | 2011-09-15 |
20110221064 | ELECTROMIGRATION RESISTANT ALUMINUM-BASED METAL INTERCONNECT STRUCTURE - A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl | 2011-09-15 |
20110221065 | METHODS OF FORMING SEMICONDUCTOR CHIP UNDERFILL ANCHORS - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side. | 2011-09-15 |
20110221066 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to an aspect of the present invention includes the steps of: forming a metallic film; forming plural connecting conductors including engaging portions on the metallic film; forming a first resin; curing a second resin; forming a wiring pattern; forming a second external electrode; and cutting the second resin. The step of forming the first resin is the step of inserting and bringing a projected first external electrode provided in each of plural semiconductor chips in and into contact with each of the engaging portions of the plural connecting conductors, and forming a first resin between the plural semiconductor chips and the metallic film. The step of curing the second resin is the step of covering the plural semiconductor chips with the second resin to cure the second resin. | 2011-09-15 |
20110221067 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary. | 2011-09-15 |
20110221068 | INTERCONNECT STRUCTURE COMPRISING BLIND VIAS INTENDED TO BE METALIZED - An interconnect structure including:
| 2011-09-15 |
20110221069 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor element having a first surface on which an electrode terminal is formed, and a second surface located opposite to the first surface. The semiconductor device further includes a first insulating layer in which the semiconductor element is buried, and second insulating layers and wiring layers formed in such a manner that at least one insulating layer and at least one wiring layer are formed on each of both surfaces of the first insulating layer. The electrode terminal of the semiconductor element is connected to a first wiring layer located on the first surface side through a first via formed in the first insulating layer, and the first wiring layer is connected to a second wiring layer located on the second surface side through a second via formed in the first insulating layer. | 2011-09-15 |
20110221070 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads. | 2011-09-15 |
20110221071 | ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - In an electronic device having multilayer resin interconnection layers, it is desired to reduce the warp of its support substrate. It is manufactured by: forming a lower layer including a via and a first insulating part on the support substrate; and forming an intermediate layer including a first interconnection and a second insulating part covering the first interconnection on the lower layer. The lower layer is formed by: forming the first insulating part on a first circuit region and a first region surrounding it; and forming the via on the first circuit region. The intermediate layer is formed by: forming the first interconnection on the first circuit region; forming a film of the second insulation part to cover the lower layer; and removing the second insulating part on the first region such that an outer circumferential part of an upper surface of the lower layer part is exposed. | 2011-09-15 |
20110221072 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier. | 2011-09-15 |
20110221073 | Layered chip package with wiring on the side surfaces - A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number. | 2011-09-15 |
20110221074 | Board on chip package - A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip. | 2011-09-15 |
20110221075 | METHOD OF MANUFACTURING ELECTRONIC DEVICE AND ELECTRONIC DEVICE - Provided is a method of manufacturing an electronic device comprising a first electronic component having a first terminal and a second electronic component having a second terminal, wherein said first electric component is electrically connected to said second electronic component by connecting said first terminal to said second terminal with solder, | 2011-09-15 |
20110221076 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a power semiconductor element that is a semiconductor element; bonding parts provided for bonding of an upper surface and a lower surface of the semiconductor element; and metal plates bonded to the power semiconductor element from above and below through the bonding parts, wherein the bonding part includes a mesh metal body disposed between the semiconductor element and the metal plate, and a bonding member in which the mesh metal body is embedded. | 2011-09-15 |
20110221077 | WATER REPELLANT COMPOSITION FOR SUBSTRATE TO BE EXPOSED, METHOD FOR FORMING RESIST PATTERN, ELECTRONIC DEVICE PRODUCED BY THE FORMATION METHOD, TREATMENT METHOD FOR IMPARTING WATER REPELLENCY TO SUBSTRATE TO BE EXPOSED, WATER REPELLANT SET FOR SUBSTRATE TO BE EXPOSED, AND TREATMENT METHOD FOR IMPARTING WATER REPELLENCY TO SUBSTRATE TO BE EXPOSED USING THE SAME - It is an object of the present invention to provide a water repellant composition for a substrate to be exposed which inhibits the back side of a substrate to be exposed from being contaminated by an immersion liquid, can improve adhesion between a film to be processed and an organic film directly overlying that film to inhibit film peeling, and has excellent workability, a method for forming a resist pattern, an electronic device produced by the formation method, a treatment method for imparting water repellency to a substrate to be exposed, a water repellent set for a substrate to be exposed, and a treatment method for imparting water repellency to a substrate to be exposed using the same. A water repellent composition for a substrate to be exposed including at least an organosilicon compound represented by the following general formula (1) and a solvent is used. | 2011-09-15 |
20110221078 | HUMIDIFIER - A humidifier includes a main body having a hollow interior, the main body including a fluid reservoir for receiving a fluid therein, wherein the fluid reservoir is formed from a material which at least one of minimizes impurities in the fluid and militates against an emergence of impurities in the fluid, and a discharge vent coupled to the main body, wherein the discharge vent includes a removable tray for receiving a fragrance therein and a compartment for receiving a heat source therein for heating the fragrance, wherein the discharge vent emits a mist to humidify the surrounding air and an aroma of the fragrance. | 2011-09-15 |
20110221079 | BLOWER TYPE CHEMICAL DIFFUSING APPARATUS WITH FUEL CELL POWER SUPPLY - A blower type chemical diffusing apparatus is disclosed which can be of service for an extended period of time and does not give rise to refuse disposal problems. The blower type chemical diffusing apparatus of the invention has an air blower, a chemical retainer and a fuel cell included in the apparatus body whereby powering the air blower to drive it with the fuel cell causes chemical from the chemical retainer to be emitted into an environmental atmosphere. | 2011-09-15 |
20110221080 | EMISSION PURIFIYING SYSTEM AND DEVICE FOR SLOWING GLOBAL WARMING - An emission purifying system and device for slowing global warming is provided herein which may eliminate the pollutant gases produced by combustion. The system uses a pump with waterfall, bubbling, airing, lubricating and liquefying sub-systems to catch and store the combustion gases, thus reducing the temperature of the combustion, potentially preventing global warming effects and acid rain, eliminating the noise produced by combustion as well as the characteristic odors, while utilizing the produced thermal energy to transform it into steam and kinetic energy for a variety of uses. | 2011-09-15 |
20110221081 | MANUFACTURING METHOD OF A HIGH-RELIABILITY OPTICAL FIBER COUPLER - A manufacturing method of a high-reliability optical fiber coupler includes (1) manufacturing the optical fiber coupler by a fused biconical tapering process employing a parallel sintering process, and detecting via a tension test the strength of the optical fiber resulting from the sintering process, securing the strength thereof being greater than or equal to 1N; (2) fixing both ends of the sintered optical fiber coupler in a U-shaped quartz groove via hardening adhesive, and filling inside of the U-shaped quartz groove around the coupling arm at both ends thereof with adhesive to shorten the suspending length of the optical fiber; (3) inserting the U-shaped groove containing the optical fiber coupler into a circular quartz tube, and fixing both ends of the circular quartz tube via hardening adhesive; and (4) sleeving a stainless steel tube around the circular quartz tube, and sealing both ends of the stainless steel tube. | 2011-09-15 |
20110221082 | LIPOSOME MANUFACTURING DEVICE - Provided is a liposome manufacturing device which is a relatively small, multipurpose liposome manufacturing device that uses a motor, and that can reliably manufacture various types of liposomes and reconfigured liposomes. The multipurpose liposome manufacturing device is provided with an eccentric motor ( | 2011-09-15 |
20110221083 | POLYMER-BASED MICROSTRUCTURES - The present invention relates to the fields of controlled release of drugs, proteins, nucleic acids, and other pharmaceuticals. It also relates to delivery systems for these agents and other compounds. The invention also relates to stable encapsulation of cells and molecules. The invention provides a population of microstructures comprising a permeable polymer shell, wherein the standard variance in the volume of the microstructures is usually less than or equal to 20%, preferably 10%, of the mean, and wherein the diffusion characteristics of the polymer shell vary within the population of microstructures. It also provides for an apparatus and a method of forming a population of microstructures, which method for making microstructures by introducing drops of a polymer solution into a receiving solution under conditions that permit cross-linking of the polymer in the receiving solution. Microstructures of calcium-cross-linked alginate with a chitosin capsule are disclosed. | 2011-09-15 |
20110221084 | Honeycomb composite silicon carbide mirrors and structures - Honeycomb silicon carbide composite mirrors and a method of making the mirrors. In a preferred embodiment the mirror is made from a carbon fiber preform molded into a honeycomb shape using a rigid mold. The carbon fiber honeycomb is densified using polymer infiltration pyrolysis or reaction with liquid silicon. A chemical vapor deposited or chemical vapor composite process is utilized to deposit a polishable silicon or silicon carbide cladding on the honey comb structure. Alternatively, the cladding may be replaced by a free standing replicated CVC SiC facesheet that is bonded to the honeycomb. | 2011-09-15 |
20110221085 | METHOD AND APPARATUS FOR FEEDING A POLYURETHANE MIXTURE INTO HOLLOW BODIES - A method and apparatus for feeding a polyurethane mixture suitable to form a thermally insulating layer inside hollow bodies, such as hollow walls of a refrigerator cabinet, freezer, display counter or insulating panel. A polyurethane mixture resulting from chemically reactive components, supplied by a high-pressure mixing device, is injected into a cavity of a hollow body extending in a horizontal plain. The mixture is injected at a first flow-rate and a first injection speed, to be poured into a first deposition zone farthest from the injection point. Subsequently, the flow-rate and the injection speed of the polyurethane mixture are gradually reduced in a controlled manner, to be poured in successive deposition zones towards the injection point of the polyurethane mixture, along a distribution strip, allowing the injected mixture to spread out throughout the cavity of the hollow body along isometric expansion lines. | 2011-09-15 |
20110221086 | TIRE UNIFORMITY CORRECTION - Improved methods and apparatus are disclosed for correcting one or more uniformity characteristics in a tire and particularly to correction in a low profile tire or a tire having a projection along the sidewall. The uniformity characteristic may be a radial force variation, conicity, or both. Correction is accomplished by stretching portions of the tire architecture to create permanent deformation. | 2011-09-15 |
20110221087 | Molding die and method for molding a molded article - A molding die and a method for molding a molded article including a foam layer made up of faces extended in a plurality of directions are provided, by which all of the faces can grow up to a predetermined expansion ratio or more. To this end, a molding die | 2011-09-15 |
20110221088 | HOT-MELT MOLDING APPARATUS - A hot-melt molding apparatus includes an apparatus body, a cylinder, a molding head, a heating device, a conveyor screw, a heat transport section, a thermoelectric element, and a power storage section. The cylinder communicates with the apparatus body and is configured to receive thermoplastic material. The molding head is provided at one end of the cylinder. The heating device is configured to heat the cylinder and the molding head to melt thermoplastic material therein. The conveyor screw is provided inside the cylinder to convey thermoplastic material to the molding head. The heat transport section has a first end connected to at least one of the cylinder and the molding head. The thermoelectric conversion element is connected to a second end of the heat transport section. The power storage section is connected to the thermoelectric conversion element and is configured to store power generated by the thermoelectric conversion element. | 2011-09-15 |
20110221089 | RAPID ROTATIONAL FOAM MOLDING PROCESS - The nature of the rotational molding process is cyclic. It requires the temperature of the rotating mold and the plastic it is charged with to be elevated from room temperature to beyond its melting temperature and then cooled back to room temperature. Consequently, rotational molding cycle times are lengthy, which is often considered as the fundamental drawback of this plastic fabrication process. The motivation and objectives of this disclosure are twofold. The presently proposed invention focuses on developing an innovative extrusion-assisted rotational foam molding processing technology for the manufacture of integral-skin cellular composite moldings having adjacent, but clearly distinct, layers of non-cellular and cellular structures, consisting of identical or compatible polymeric grades. Its primary goal is to significantly reduce the processing cycle time in comparison with respective currently implemented technologies by employing melt extrusion in order to maximize the speed of controlled polymer melting. | 2011-09-15 |
20110221090 | Systems and Methods For Deforming An Outer Wall Of Pipe - A method of deforming an outer wall of polymer pipe is provided. The method includes: forming dual-wall pipe having a smooth wall and a corrugated wall; extruding an outer wall of pipe onto the corrugated wall of the dual-wall pipe; penetrating the outer wall of pipe with a vacuum punch; and drawing a vacuum between the corrugated wall and the outer wall via the vacuum punch; wherein the vacuum drawn between the corrugated wall and the outer wall causes the outer wall to deform in a direction towards the corrugated wall. An apparatus for forming an outer wall of pipe and a mold configured to form a coupling preform in a segment of continuously-extruded and molded polymer pipe are also provided. | 2011-09-15 |
20110221091 | METHOD AND MOULD FOR THERMOFORMING AND FOLDING A PLASTIC SHEET - A method for producing a thermo formed part includes closing in a mould a heated sheet (L) made of thermoplastic material in such a manner as to deform the latter, then cooling it inside the mould until complete consolidation is achieved. During cooling, the sheet is cut along at least one edge portion (E) thereof, this cutting operation causing a bending of the edge portion against an abutment surface ( | 2011-09-15 |
20110221092 | Grooved, Corner-Ready Wall Base - A resilient wall base member manufactured with pre-scored grooves to allow relatively short, straight lengths to be used for both flat walls and wall corner junctures without on site scoring operations or equipment. The lengths can either be pre-cut during manufacturing to convenient lengths or can be cut after manufacturing from coils. | 2011-09-15 |
20110221093 | METHOD AND SYSTEM FOR MANUFACTURING WIND TURBINE BLADES - A method and system for making and forming turbine blades. The method and system can include steps for determining stress loads on amore turbine blades; constructing one or more molds for components of the turbine blade in which a turbine-forming substance is injected; applying a resin to an interior portion of the one or more molds; forming one or more partitions within the one or more molds; coupling the one or more molds; injecting the blade-forming substance into the coupled one or more molds; regulating the pressure in the coupled one or more molds; voiding any excess air or resin in the coupled one or more molds; and allowing the blade-forming substance injected into the coupled one or more molds to harden. | 2011-09-15 |
20110221094 | PROCESS FOR MAKING AN EMBOSSED WEB - A process for making an embossed web includes providing a precursor web a first forming structure having a plurality of discrete first forming elements and a first pressure source and applying pressure between the first pressure source and the first forming structure to force the precursor web to conform to the first forming elements of to form a first embossed web having a plurality of first discrete extended elements. The first embossed web is then provided between a second forming structure having a plurality of discrete second forming elements and a second pressure source and pressure is applied between the second pressure source and the second forming structure to force the first embossed web to conform to the second forming elements to form a second embossed web having a plurality of second discrete extended elements. The resulting embossed web has a plurality of first and second discrete extended elements. | 2011-09-15 |
20110221095 | Step and Repeat Imprint Lithography Process - The present invention is directed to methods for patterning a substrate by imprint lithography. Imprint lithography is a process in which a liquid is dispensed onto a substrate. A template is brought into contact with the liquid and the liquid is cured. The cured liquid includes an imprint of any patterns formed in the template. In one embodiment, the imprint process is designed to imprint only a portion of the substrate. The remainder of the substrate is imprinted by moving the template to a different portion of the template and repeating the imprint lithography process. | 2011-09-15 |
20110221096 | Thin Collagen Tissue for medical device applications - This invention relates to processes of preparing heterogeneous graft material from animal tissue. Specifically, the invention relates to the preparation of animal tissue, in which the tissue is cleaned and chemically cross-linked using both vaporized and liquid cross-linking agents, resulting in improved physical properties such as thin tissue and lowered antigenicity, thereby increasing the ease of delivering the tissue during surgery and decreasing the risk of post-surgical complication, respectively. | 2011-09-15 |
20110221097 | METHOD OF MANUFACTURING SHEET FOR FOOD CONTAINERS - This invention relates to a method of manufacturing sheet for food containers, which comprises:
| 2011-09-15 |
20110221098 | METHODS OF MANUFACTURING ALIGNMENT SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE ALIGNMENT SUBSTRATE - A method of manufacturing an alignment substrate includes preparing a first substrate on which an alignment film aligned in a first alignment direction is formed; forming a plurality of fluoro-polymer patterns on the first substrate; changing the alignment direction of regions of the alignment film on which the fluoro-polymer patterns are not formed; and removing the fluoro-polymer patterns by using a fluoro-solvent. | 2011-09-15 |
20110221099 | METHOD AND DEVICE FOR MANUFACTURING A THREE-DIMENSIONAL OBJECT THAT IS SUITABLE FOR APPLICATION TO MICROTECHNOLOGY - The present invention relates to a method and a device for manufacturing a three-dimensional object, wherein the object is generated by successively solidifying single layers of fluid or powdery solidifiable building material by the action of electromagnetic radiation. The method comprises steps for emitting a first pulsed electromagnetic radiation onto a first area of a layer of the building material, and for emitting a second continuous electromagnetic radiation onto a second area of the layer of the building material. | 2011-09-15 |
20110221100 | PRODUCTION METHOD FOR A PAINT PLANT COMPONENT AND CORRESPONDING PAINT PLANT COMPONENT - Exemplary production methods for producing a paint plant component, e.g., for producing a component of a colour changer, a colour valve, or a spray device, are disclosed. According to the exemplary illustrations, the paint plant component may be produced in a rapid prototyping method. The exemplary illustrations also include a paint plant component that is produced accordingly. | 2011-09-15 |
20110221101 | Resin-based molding of electrically conductive structures - A method for resin-based molding of electrical structures which possess desired properties of electrical conductivity, radio frequency (RF) energy reflectivity, and electromagnetic interference (EMI) shielding, while still retaining the basic physical and structural properties of the base (plastic) material. | 2011-09-15 |
20110221102 | Injection stretch blow-molding process for the preparation of polymer containers - Injection stretch blow-molding process for preparing polymer containers, comprising the following steps:
| 2011-09-15 |
20110221103 | METHOD AND APPARATUS FOR PRODUCING A LINER OF A CONTAINER - A method and apparatus for manufacture of a liner of a container is disclosed. The apparatus includes an elongate shaft having a first end and a second end, wherein at least one of the first end and the second end receives a container penetration element thereon. | 2011-09-15 |
20110221104 | Process for manufacturing a fuel tank - Process for manufacturing a plastic fuel tank equipped with a component, by molding a parison using a mold comprising two cavities and a core, the process comprising the mounting of a component around a needle or an oblong object attached to the core, the displacement of the needle or oblong object so as to deform the parison and pierce an opening into it, the needle or oblong object carrying the component with it in order to position the component in the opening, and the withdrawal of the needle/oblong object, leaving the component lodged in the opening. | 2011-09-15 |
20110221105 | LEAF SPRING ATTACHMENT - A leaf spring attachment for connecting a leaf spring to an axle or frame of a motor vehicle includes a clamp to maintain the leaf spring under tension between elastomer bodies. At least one of the elastomer bodies is connected to the leaf spring by a material joint. The clamp is split to define an upper clamp member and a lower clamp member in opposition to the upper clamp member. The upper clamp member has a U-shaped configuration to embrace a topside and opposite length sides of the leaf spring. The lower clamp member includes a plurality of retention plates in spaced-apart relationship for connection with the axle by material joint. Screw fasteners are provided to secure legs of the upper clamp member to the lower clamp member. | 2011-09-15 |
20110221106 | Hydromount - A hydromount ( | 2011-09-15 |
20110221107 | Liquid Sealed Mount - A hydraulic mount includes: a container in which a high-viscosity fluid is liquid-tightly sealed; a rubber mount that is provided on an upper side of the container; a rod that slidably penetrates through the rubber mount; a damper plate that is provided to an end of the rod; a damping force generator that is provided by a clearance between the container and the damper plate; a main fluid chamber that includes an upper fluid chamber and a lower fluid chamber provided by dividing an interior of the container by the damper plate; a volume-variable secondary fluid chamber that communicates with the main fluid chamber; and a pressurizer that generates a differential pressure between the upper fluid chamber and the lower fluid chamber during the movement of the rod. | 2011-09-15 |