37th week of 2015 patent applcation highlights part 56 |
Patent application number | Title | Published |
20150255596 | LDMOS TRANSISTOR AND METHOD OF FORMING THE LDMOS TRANSISTOR WITH IMPROVED RDS*CGD - The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region. | 2015-09-10 |
20150255597 | Semiconductor Device and Method of Making the Same - A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate. | 2015-09-10 |
20150255598 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode. | 2015-09-10 |
20150255599 | VERTICAL MEMORY DEVICES, MEMORY ARRAYS, AND RELATED METHODS - Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a second direction different from the first direction. Portions of the word lines in a word line end region have a first vertical length greater than a second vertical length of portions of the word lines in the array region. Apparatuses including vertical transistors in an array region, buried digit lines extending in a first direction, and word lines are also disclosed. Each of the word lines extends in a second direction perpendicular to the first direction, is formed over at least a portion of a sidewall of at least some of the vertical transistors, and vertically has a depth in a word line end region about equal to or greater than a depth thereof in the array region. | 2015-09-10 |
20150255600 | JUNCTION-LESS TRANSISTORS - A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer. The method also includes etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and a portion of the dielectric layer; and removing the portion of the dielectric layer between the adjacent trenches to form a chamber. Further, the method includes forming a gate structure around the portion of the semiconductor layer between the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure. | 2015-09-10 |
20150255601 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure includes a substrate and an epitaxy region that is partially disposed in the substrate. A doping concentration of the epitaxy region increases from a bottom portion to a top portion of the epitaxy region. The present disclosure also provides a method for manufacturing the semiconductor structure, including forming a recess in a substrate; forming an epitaxy region in the recess; and in situ doping the epitaxy region to form a doping concentration profile increasing from a bottom portion to a top portion of the epitaxy region. | 2015-09-10 |
20150255602 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH DISLOCATIONS - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes proving a substrate. The substrate includes a gate stack over the substrate and source/drain regions separated by the gate stack. A first dislocation with a first pinch-point is formed within the source/drain region with a first depth. A second dislocation with a second pinch-point is formed within the source/drain region at a second depth. The second depth is substantial smaller than the first depth. | 2015-09-10 |
20150255603 | DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material. | 2015-09-10 |
20150255604 | WRAP AROUND CONTACT - Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a “finned” field-effect transistor (FinFET). An epitaxial material is formed over the source or drain region, which includes a diamond-shaped cross-section with top and bottom surfaces. A capping layer is formed over the top and bottom surfaces. The source or drain region is subjected to a first etch to remove the capping layer surrounding the top surfaces of the diamond-shaped cross-section. A protective layer is formed within the top surfaces. A second etch of the capping layer is performed to remove the capping layer surrounding the bottom surfaces of the diamond-shaped cross-section, while using the protective layer to prevent etching of the top surfaces by the second etch. A contact is formed to the source or drain region, which surrounds the source or drain region on the top and bottom surfaces. | 2015-09-10 |
20150255605 | METHOD TO ENHANCE STRAIN IN FULLY ISOLATED FINFET STRUCTURES - Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET. | 2015-09-10 |
20150255606 | STRUCTURE AND METHOD TO MAKE STRAINED FINFET WITH IMPROVED JUNCTION CAPACITANCE AND LOW LEAKAGE - A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type. | 2015-09-10 |
20150255607 | SEMICONDUCTOR DEVICE HAVING STRESSOR AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a stressor. A device isolation layer is formed on a substrate to define an active region. A gate electrode is formed on the active region. A trench is formed in the active region adjacent to the gate electrode and has first and second sidewalls. A stressor is formed within the trench. The first sidewall of the trench is near the gate electrode and relatively far away from the device isolation layer. The second sidewall of the trench is near the device isolation layer and relatively far away from the gate electrode. The second sidewall of the trench has a step shape. | 2015-09-10 |
20150255608 | METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material. | 2015-09-10 |
20150255609 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions. | 2015-09-10 |
20150255610 | SEMICONDUCTOR TRANSISTOR STRUCTURE AND FABRICATION METHOD THEREOF - FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions. | 2015-09-10 |
20150255611 | OXIDE SPUTTERING TARGET, AND THIN FILM TRANSISTOR USING THE SAME - An oxide sputtering target includes at least one of indium (In), zinc (Zn), tin (Sn), and gallium (Ga), and tungsten (W) in an amount from 0.005 mol % to 1 mol %. | 2015-09-10 |
20150255612 | Semiconductor Device, Display Device, Input/Output Device, and Electronic Device - A self-aligned transistor including an oxide semiconductor film, which has excellent and stable electrical characteristics, is provided. A semiconductor device is provided with a transistor that includes an oxide semiconductor film, a gate electrode overlapping with part of the oxide semiconductor film, and a gate insulating film between the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a first region and second regions between which the first region is positioned. The second regions include an impurity element. A side of the gate insulating film has a depressed region. Part of the gate electrode overlaps with parts of the second regions in the oxide semiconductor film. | 2015-09-10 |
20150255613 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - The display device includes a gate electrode, a gate insulating film provided over the gate electrode, a semiconductor film provided over the gate insulating film to overlap with the gate electrode, an island-shaped first insulating film provided over the semiconductor film to overlap with the gate electrode, a first conductive film provided over the semiconductor film, a pair of second conductive films which is provided over the semiconductor film and between which the first insulating film is sandwiched, and a second insulating film provided over the first insulating film, the first conductive film, and the pair of second conductive films. In the second insulating film and the semiconductor film, an opening portion which is positioned between the first conductive film and the one or the other of the pair of second conductive films is provided. | 2015-09-10 |
20150255614 | SPLIT GATE FLASH MEMORY AND MANUFACTURING METHOD THEREOF - A split gate flash memory is provided. A device isolation structure is disposed in a substrate to define an active area. A first doping region and a second doping region are respectively disposed in an active area of the substrate. A select gate is disposed in a trench in the substrate, and a side of the select gate is adjacent to the first doping region. A gate dielectric layer is disposed between the select gate and the substrate. A floating gate is disposed on the substrate, a side of the floating gate overlaps to the second doping region, and a portion of the floating gate is disposed on the select gate. An inter-gate dielectric layer is disposed between the floating gate and the select gate and between the floating gate and the substrate. | 2015-09-10 |
20150255615 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed. | 2015-09-10 |
20150255616 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - This semiconductor device is provided with: a semiconductor film that comprises an oxide semiconductor film, and has a channel region; a protective film that is formed on the semiconductor film in a form that covers the channel region; a first inorganic insulating film that is formed on the protective film in a form having an area that overlaps with the channel region; and an organic insulating film that comprises a resin film formed on the first inorganic insulating film, and has a first opening that exposes the first inorganic insulating film in the area that overlaps with the channel region. | 2015-09-10 |
20150255617 | SEMICONDUCTOR DEVICE - A semiconductor device of stable electrical characteristics, whose oxygen vacancies in a metal oxide is reduced, is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, a first metal oxide film over the gate insulating film, a source electrode and a drain electrode which are in contact with the first metal oxide film, and a passivation film over the source electrode and the drain electrode. A first insulating film, a second metal oxide film, and a second insulating film are stacked sequentially in the passivation film. | 2015-09-10 |
20150255618 | THIN-FILM TRANSISTOR (TFT), PREPARATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - A thin-film transistor (TFT), a preparation method thereof, an array substrate and a display device are disclosed. The TFT disclosed in the present invention includes a source electrode, a drain electrode, a semiconductor layer, a gate electrode and a gate insulating layer and further includes: a source conductive layer and a drain conductive layer which are disposed on the surface of the semiconductor layer and spaced from each other. The source conductive layer is connected with the source electrode; the drain conductive layer is connected with the drain electrode; and the minimum distance between the source conductive layer and the drain conductive layer is less than the minimum distance between the source electrode and the drain electrode. The TFT is applicable to a display device, in particular, to a LCD or OLED. | 2015-09-10 |
20150255619 | Vertical Thin Film Transistor Selection Devices And Methods Of Fabrication - Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath each gate, a single gap fill dielectric layer extends vertically from a lower surface of the gate, at least partially separating the gate from the underlying global bit line. Between horizontally adjacent pillars, this same dielectric layer extends from its same lower level beneath the gates vertically to a level of the upper source/drain region. | 2015-09-10 |
20150255620 | VTFTS INCLUDING OFFSET ELECTRODES - A device with multiple vertical transistors includes a substrate and an electrically conductive gate structure including first and second edges opposite each other and including first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the reentrant profiles and is in contact with the gate. A conformal semiconductor layer maintains the reentrant profiles and is in contact with the insulating layer. First and second electrodes are in contact with first and second portions of the semiconductor and adjacent to the first and second reentrant profiles, respectively. A third electrode is in contact with a third portion of the semiconductor on a top of the gate structure. The first and third electrodes and the second and third electrodes define ends of first and second channels of first and second transistors, respectively. First and second lines, extending between the ends of the first and second channels, are not parallel. | 2015-09-10 |
20150255621 | VTFT WITH POLYMER CORE - A transistor includes a polymeric material post on a substrate. An inorganic material cap, covering the post, extends beyond an edge of the post to define a reentrant profile. A conformal conductive material gate layer is over the edge of the post in the reentrant profile. A conformal insulating material layer is on the gate layer in the reentrant profile. A conformal semiconductor material layer is on the insulating material layer in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer over the cap. A second electrode is in contact with a second portion of the semiconductor layer over the substrate and not over the post, and adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface. | 2015-09-10 |
20150255622 | VTFT WITH EXTENDED ELECTRODE - A thin film transistor includes a polymeric material post on a substrate. An inorganic material cap, covering the top of the post, extends beyond first and second edges of the post to define first and second reentrant profiles, respectively. A conformal conductive gate layer is over the edge of the post, a conformal insulating layer is on the gate layer, and a conformal semiconductor layer is on the insulating layer in the first reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer over the cap and extends to a location adjacent to the second edge. A second electrode is in contact with a second portion of the semiconductor layer not over the post, and adjacent to the first edge such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface. | 2015-09-10 |
20150255623 | VTFT WITH POST, CAP, AND ALIGNED GATE - A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top, and an edge along the height dimension. A cap covers the top of the post and extends to a distance beyond the edge of the post to define a reentrant profile. A conformal conductive gate layer is located on the edge of the post in the reentrant profile and not over the cap, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with a first portion of the semiconductor layer over the cap and a second portion of the semiconductor layer not over the post, respectively. | 2015-09-10 |
20150255624 | VTFT INCLUDING OVERLAPPING ELECTRODES - A vertical transistor includes a substrate and an electrically conductive gate structure having a top surface and including a reentrant profile. A conformal electrically insulating layer that maintains the reentrant profile is in contact with the electrically conductive gate structure and at least a portion of the substrate. A conformal semiconductor layer that maintains the reentrant profile is in contact with the conformal electrically insulating layer. An electrode that extends into the reentrant profile is in contact with a first portion of the semiconductor layer. Another electrode is vertically spaced apart from the electrode, overlaps a portion of the electrode that extends into the reentrant profile, is in contact with a second portion of the semiconductor material layer over the top surface of the electrically conductive gate structure, and is within the reentrant profile. | 2015-09-10 |
20150255625 | OFFSET INDEPENDENTLY OPERABLE VTFT ELECTRODES - A multiple vertical transistor device includes a polymeric material post on a substrate. An inorganic material cap extends beyond first and second edge of the post to define first and second reentrant profiles. First and second portions of a conformal conductive gate layer define first and second gates in the first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the first and second reentrant profiles and is in contact with the first and second gates. First and second portions of a semiconductor layer, maintaining the first and second reentrant profiles, are in contact with the conformal electrically insulating layer that is in contact with the first and second gates, respectively. The first and second portions of the semiconductor layer are electrically independent from each other. First and second electrodes are associated with the first gate. Third and fourth electrodes are associated with the second gate. | 2015-09-10 |
20150255626 | VTFT WITH GATE ALIGNED TO VERTICAL STRUCTURE - A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top portion of the post which extends a distance beyond a bottom portion of the post in a direction parallel to the substrate to define a reentrant profile. A conformal conductive gate layer is located on an edge of the post in the reentrant profile and not over the top portion of the post, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with first and second portions of the semiconductor layer over the top portion of the post and not over the top portion of the post, respectively. | 2015-09-10 |
20150255627 | THIN FILM TRANSISTOR - A thin film transistor containing at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate containing a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 8% or more and 30% or less; In: 25% or less, excluding 0%; Zn: 35% or more to 65% or less; and Sn: 5% or more to 30% or less. | 2015-09-10 |
20150255628 | BIDIRECTIONAL ZENER DIODE - A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode. | 2015-09-10 |
20150255629 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductive type having a first side and an opposed second side; a second semiconductor layer of a second conductive type formed on the first side; a third semiconductor layer of a second conductive type partially formed in the second semiconductor layer; a fourth semiconductor layer of a first conductive type formed between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer facing the third semiconductor layer, the fourth semiconductor layer including a first region which has a first dopant concentration and a second region which has a second dopant concentration higher than the first dopant concentration; a fifth semiconductor layer of a first conductive type formed on the second side; and a conductor contacting the first semiconductor layer, the second semiconductor layer and the third semiconductor layer via an insulation film. | 2015-09-10 |
20150255630 | VARACTOR STRUCTURE - A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad. | 2015-09-10 |
20150255631 | QUANTUM CAPACITANCE GRAPHENE VARACTORS AND FABRICATION METHODS - A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included. | 2015-09-10 |
20150255632 | SOLAR CELL ELECTRICALLY CONDUCTIVE STRUCTURE AND METHOD - Some aspects of the invention are related to a solar cell, for producing electricity from solar radiation. The solar cell may include a substrate, for example, polycrystalline silicon and an electrically conductive structure disposed on the substrate. The electrically conductive structure may include a bus bar and one or more finger electrodes positioned such that at least a portion of a finger electrode overlaps the bus bar. | 2015-09-10 |
20150255633 | ELECTRICALLY CONDUCTIVE ADHESIVE COMPOSITION, CONNECTION STRUCTURE, SOLAR BATTERY MODULE, AND METHOD FOR PRODUCING SAME - An electrically conductive adhesive composition comprising electrically conductive particles containing a metal of which melting point is 220° C. or less, a thermosetting resin, and a thermal cationic polymerization initiator. | 2015-09-10 |
20150255634 | SEMICONDUCTOR DEVICE HAVING A TRANSPARENT WINDOW FOR PASSING RADIATION - Method of encapsulating a semiconductor structure comprising providing a semiconductor structure comprising an opto-electric element located in a cavity formed between a substrate and a cap layer, the cap layer being made of a material transparent to light, and having a flat upper surface; forming at least one protrusion on the cap layer; bringing the at least one protrusion of the cap layer in contact with a tool having a flat surface region, and applying a opaque material to the semiconductor structure where it is not in contact with the tool; and removing the tool thereby providing an encapsulated optical semiconductor device having a transparent window integrally formed with the cap layer. | 2015-09-10 |
20150255635 | DETACHABLE PACKAGE STRUCTURE - A detachable package structure that includes an assembly substrate, a first semiconductor substrate, a second semiconductor substrate, and a combination element is provided. The first semiconductor substrate is disposed on the assembly substrate and has a first alignment portion. The second semiconductor substrate has a second alignment portion. The combination element allows the first semiconductor substrate and the second semiconductor substrate to be detachably combined together, such that the first alignment portion and the second alignment portion are aligned and combined. | 2015-09-10 |
20150255636 | RADIATION DETECTOR - A radiation detector ( | 2015-09-10 |
20150255637 | PHOTOVOLTAIC DEVICES INCORPORATING THIN CHALCOGENIDE FILM ELECTRICALLY INTERPOSED BETWEEN PNICTIDE-CONTAINING ABSORBER LAYER AND EMITTER LAYER - The present invention provides strategies for improving the quality of the insulating layer in MIS and SIS devices in which the insulator layer interfaces with at least one pnictide-containing film The principles of the present invention are based at least in part on the discovery that very thin (20 nm or less) insulating films comprising a chalcogenide such as i-ZnS are surprisingly superior tunnel barriers in MIS and SIS devices incorporating pnictide semiconductors. In one aspect, the present invention relates to a photovoltaic device, comprising: a semiconductor region comprising at least one pnictide semiconductor; an insulating region electrically coupled to the semiconductor region, wherein the insulating region comprises at least one chalcogenide and has a thickness in the range from 0.5 nm to 20 nm; and a rectifying region electrically coupled to the semiconductor region in a manner such that the insulating region is electrically interposed between the collector region and the semiconductor region. | 2015-09-10 |
20150255638 | method of modifying an n-type silicon substrate - A method of modifying a silicon substrate which is intended for use in a photovoltaic device, comprising the steps of providing an n-type silicon substrate having a bulk and exhibiting a front surface and a rear surface; and forming by liquid phase application dielectric layers on said front and rear surfaces. The dielectric layer formed at the rear surface is capable of acting as a reflector to enhance reflection of light into the bulk of the silicon substrate, and the dielectric layer formed at the front comprises oxygen, hydrogen and at least one metal or semimetal and is capable of releasing hydrogen into the bulk as well as onto the surfaces of the silicon substrate in order to provide hydrogenation and passivation. The present invention provides a low cost method of improving the electrical or optical performance, or both, of photovoltaic devices: an increase in the efficiency of the current extraction and reduction of recombination occur within the device. | 2015-09-10 |
20150255639 | PHOTOVOLTAIC COMPONENT WITH A HIGH CONVERSION EFFICIENCY - A photovoltaic component that includes at least one first array of photovoltaic nano-cells is disclosed. Each photovoltaic component includes an optical nano-antenna exhibiting an electromagnetic resonance in a first resonant spectral band, at least one lateral dimension of the optical nano-antenna being subwavelength in size, and a spectral conversion layer allowing at least part of the solar spectrum to be converted to said first resonant spectral band. | 2015-09-10 |
20150255640 | Nanostructured Solar Cell - Systems and methods for fabrication of nanostructured solar cells having arrays of nanostructures are described, including nanostructured solar cells having a repeating pattern of pyramid nanostructures, providing for low cost thin-film solar cells with improved PCE. | 2015-09-10 |
20150255641 | THREE-DIMENSIONAL CONDUCTIVE ELECTRODE FOR SOLAR CELL - A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack. | 2015-09-10 |
20150255642 | SOLAR CELL AND TEXTURING METHOD THEREOF - The present invention relates to a solar cell. The solar cell includes a substrate of a first conductive type, the substrate having a textured surface on which a plurality of projected portions are formed, and surfaces of the projected portions having at least one of a plurality of particles attached thereto and a plurality of depressions formed thereon; an emitter layer of a second conductive type opposite the first conductive type, the emitter layer being positioned in the substrate so that the emitter layer has the textured surface; an anti-reflection layer positioned on the emitter layer which has the textured surface and including at least one layer; a plurality of first electrodes electrically connected to the emitter layer; and at least one second electrode electrically connected to the substrate. | 2015-09-10 |
20150255643 | ELECTRODE FORMING PASTE COMPOSITION, AND METHOD OF MANUFACTURING ELECTRODE AND SOLAR CELL EACH USING THE SAME - An electrode forming paste composition (EFPC) which even when not fired at a high temperature at which a BSF layer is formed, is able to provide an electrode showing satisfactory adhesiveness to a silicon substrate and excellent electrical characteristics, a method of manufacturing an electrode using the EFPC, and a solar cell using the EFPC. The EFPC includes an aluminum-silicon alloy powder, an organic polymer, a silicon-containing polymer, and an adherence agent composed of an amine-based compound and/or an amide-based compound. The manufacturing method includes forming a composition layer including the EFPC on a silicon substrate; and firing the composition layer at a temperature of 577° C. or lower. The solar cell includes an electrode formed on a silicon substrate using the EFPC. | 2015-09-10 |
20150255644 | SOLAR CELL - A solar cell has a texture and is equipped with an electrode formed on the texture and including flakes in addition to conductive particulates, wherein an average value of the longest axis diameters of the flakes is larger than an average value of the distances between the vertices of the texture. | 2015-09-10 |
20150255645 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell and a method for manufacturing the same are discussed. The solar cell can include a semiconductor layer containing first impurities and having a front surface and a back surface, the front surface being a light incident surface, a first portion on the back surface of the semiconductor layer, the first portion being more heavily doped with second impurities different from the first impurities than the semiconductor layer, and forming a p-n junction with the semiconductor layer, a second portion on the back surface of the semiconductor layer, the second portion being more heavily doped with the first impurities than the semiconductor layer, a third portion on the back surface of the semiconductor layer between the first portion and the second portion, a first electrode on the back surface of the semiconductor layer and connected to the first portion, a second electrode on the back surface of the semiconductor layer and connected to the second portion, and a passivation layer on the back surface of the semiconductor layer and contacting the first portion. | 2015-09-10 |
20150255646 | SHALLOW JUNCTION PHOTOVOLTAIC DEVICES - A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 10 | 2015-09-10 |
20150255647 | SILVER BASED TRANSPARENT ELECTRODE - A transparent conducting electrode is disclosed having a coating stack structure, including a dielectric layer, a functional layer based on silver, a barrier layer and a further dielectric layer. The unique coating stack offers an electrode having requisite electrical properties and the ability to withstand elevated temperatures associated with further treatment, e.g. in the manufacture of photovoltaic devices. | 2015-09-10 |
20150255648 | ABSORBER LAYER FOR PHOTOVOLTAIC DEVICE, AND METHOD OF MAKING THE SAME - A photovoltaic device includes a substrate, a back contact layer disposed above the substrate, and an absorber layer disposed above the back contact layer. The absorber layer includes at least two regions at respectively different horizontally locations. Each respective region has a respectively different concentration profile of an ingredient at a respective depth of the absorber layer. | 2015-09-10 |
20150255649 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first semiconductor layer including a recess region and protrusions defined by the recessed region, first insulating patterns provided on the protrusions and extending to sidewalls of the protrusions, and a second semiconductor layer to fill the recess region and cover the first insulating patterns. The protrusions includes a first group of protrusions spaced apart from each other in a first direction to constitute a row and a second group of protrusions spaced from the first group of protrusions in a second direction intersecting the first direction and spaced from each other in the first direction to constitute a row. The second group of protrusions are shifted from the first group of protrusions in the first direction. | 2015-09-10 |
20150255650 | COST-EFFICIENT HIGH POWER PECVD DEPOSITION FOR SOLAR CELLS - A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer. | 2015-09-10 |
20150255651 | WAVELENGTH-SELECTIVE PHOTOVOLTAIC FOR A DISPLAY OR FOR A DEVICE WITH A DISPLAY - Described herein is an apparatus and method used to provide power or photovoltaic functionality to a display or device containing a display without impacting the visual perception of the display. The wavelength-selective photovoltaic (WPV) element is visibly transparent, in that it absorbs selectively around the visible emission (or reflection) peaks generated by the display. The photovoltaic material is able to cover a portion or the entire surface area of the display, without substantially blocking or perceptually impacting the emission (or reflection) of content from the display. The incident light that is absorbed by the photovoltaic element is then converted into electrical energy to provide power to the device, for example. | 2015-09-10 |
20150255652 | PHOTO-VOLTAIC DEVICE HAVING IMPROVED SHADING DEGRADATION RESISTANCE - An article of manufacture includes an active solar area having a number of photovoltaic (PV) cell sets. Each of the PV cell sets includes one or more PV cells, and has a PV cell set area. Each of the PV cell sets includes a spacing distribution, where the spacing distribution is such that a geometric shape having a predetermined characteristic area value cannot be positioned to cover an area greater than a reverse biasing fraction of the PV cell set area corresponding to the PV cell set. | 2015-09-10 |
20150255653 | SOLAR CELL MODULE WITH A NANOFILLED ENCAPSULANT LAYER - A solar cell module comprising a solar cell layer and a sheet comprising at least one layer of a nanofilled ionomer composition, wherein the nanofilled ionomer composition comprises (1) an ionomer that is derived from a precursor α-olefin carboxylic acid copolymer wherein (a) the precursor α-olefin carboxylic acid copolymer comprises (i) copolymerized units of an α-olefin and (ii) about 20 to about 25 weight % of copolymerized units of an α,β-ethylenically unsaturated carboxylic acid; and (b) at least a portion of the total content of the carboxylic acid groups present in the precursor α-olefin carboxylic acid copolymer have been neutralized to form metal salts of the carboxylic acid groups; and (2) one or more nanofillers. | 2015-09-10 |
20150255654 | SOLAR POWER CELL MATRIX - A solar cell array including a matrix of solar cells arranged on a substrate in rows and columns; and a plurality of conductor elements connecting the solar cells within each column in parallel and the solar cells of each row in series. The conductor elements are arranged on the substrate in an optical path of light to the solar cells. The conductor elements are physically dimensioned to reduce interference with the optical path and have current-carrying capacity configured to conduct current within a predetermined range of anticipated operating currents. | 2015-09-10 |
20150255655 | FLEXIBLE PRINTED WIRING BOARD AND PHOTOVOLTAIC MODULE - A flexible printed wiring board includes a first strip-shaped member and a second strip-shaped member each including a conductive part and an insulating part covering the conductive part; and a first connecting member including a conductive part and an insulating part covering the conductive part, the first connecting member connecting a first end of the first strip-shaped member and a first end of the second strip-shaped member to each other. The conductive parts of the first strip-shaped member, the second strip-shaped member, and the first connecting member are continuous with each other. The first strip-shaped member and the second strip-shaped member are capable of being linearly arranged when the first connecting member is bent and the first end of the first strip-shaped member and the first end of the second strip-shaped member face each other. | 2015-09-10 |
20150255656 | SOLAR CELL AND SOLAR MODULE INCLUDING THE SAME - A solar cell includes a substrate having an incident surface and a back surface, an emitter layer formed on the incident surface, an anti-reflective layer formed on the emitter layer opposite to the substrate, a passivation unit formed on the back surface of the substrate, a plurality of metallic nanoparticles capable of reflecting light and disposed in the passivation unit, a first electrode disposed on and electrically connected to the emitter layer, and a second electrode disposed on the passivation unit and electrically connected to the substrate. A solar module including the aforesaid solar cell is also disclosed. | 2015-09-10 |
20150255657 | WAVEGUIDE ASSISTED SOLAR ENERGY HARVESTING - A photovoltaic (PV) system includes a fiber optical waveguide comprising an active core that hosts material configured to absorb and emit light, a cladding layer surrounding the active core, the cladding layer being configured to allow ambient light to pass through the cladding layer, and an exit port located proximate an end of the waveguide. The PV system further comprises one or more solar cells disposed at the exit port of the waveguide. The waveguide is configured to guide light to the one or more solar cells. Another photovoltaic (PV) system includes a waveguide comprising an active cladding layer hosting material configured to absorb and emit light, and a core layer configured to confine light emitted by the active cladding layer. The PV system further includes one or more solar cells disposed proximate the waveguide. The core layer is configured to guide light to the one or more solar cells. | 2015-09-10 |
20150255658 | LIGHT-GUIDE SOLAR PANEL AND METHOD OF FABRICATION THEREOF - The present invention is that of a solar energy system that uses a light-guide solar panel (LGSP) to trap light inside a dielectric or other transparent panel and propagates the light to one of the panel edges for harvesting by a solar energy collector such as a photovoltaic cell. This allows for very thin modules whose thickness is comparable to the height of the solar energy collector. This eliminates eliminating the depth requirements inherent in traditional concentrated photovoltaic solar energy systems. A light guide solar panel has a deflecting layer, a light guide layer and a solar cell in optical communication with the light guide layer. The deflecting layer receives light at a first surface and inputs the light into the light guide layer. The light guide layer propagates the light to the solar cell, which is aligned generally parallel to the input surface. | 2015-09-10 |
20150255659 | SOLAR MODULE - A tandem solar module includes first and second thin film solar cell circuits and a transparent coupling layer disposed between the first and second thin film circuits for securing the first and second thin film circuits together in a stack. Each solar cell circuit includes a multi-layer structure, the multi-layer structure including a substrate, a first conductive layer formed over the substrate, a buffer layer, an absorber layer formed between the first conductive layer and the buffer layer, and a second conductive layer formed over the buffer layer. The first thin film solar cell circuit and second thin film solar cell circuit are oriented with respect to one another such that the absorber layers are disposed between the substrates of the circuits. The first and second solar cell circuits have different bandgap profiles. | 2015-09-10 |
20150255660 | MAGNETIC EFFECTS SENSOR, A RESISTOR AND METHOD OF IMPLEMENTING SAME - A system of having a circuit having an electrical coil configured to generate a magnetic field based on properties of a surrounding space and an object presented to the electrical coil and a sensor configured to sense inductance and resistance of the electrical coil and to discriminate the object presented to the electrical coil in accordance with the sensing. A precision variable resistor to control resistance of an in-loop photoresistor with an out-loop photoresistor that are located parallel to each other. | 2015-09-10 |
20150255661 | PLASMA-ASSISTED TECHNIQUES FOR FABRICATING SEMICONDUCTOR DEVICES - Plasma-assisted techniques are provided for fabricating semiconductor devices. In one aspect, a plasma is applied to a substrate before exfoliating layers of a multi-layer structure of atomically thin two-dimensional sheets onto the substrate. The exfoliated layers serve as the basis for constructing a semiconductor device. In another aspect, a p-n junction is formed by applying a plasma to top layers of a multi-layer structure of atomically thin two-dimensional sheets and then exfoliating a portion of the multi-layer structure onto a bottom electrode. | 2015-09-10 |
20150255662 | METHOD OF IN-LINE DIFFUSION FOR SOLAR CELLS - A method is provided for the simultaneous diffusion of dopants of different types on respective sides of a solar cell wafer in a single stage process. The dopants are applied to respective sides of the wafer in wet chemical form preferably by pad printing. The doping materials can be applied to the entire wafer surface or effective area thereof, or can be applied in a pattern to suit the intended solar cell configuration. In a typical embodiment, the dopants are boron and phosphorus. | 2015-09-10 |
20150255663 | PHOTOVOLTAIC CELLS HAVING ELECTRICAL CONTACTS FORMED FROM METAL NANOPARTICLES AND METHODS FOR PRODUCTION THEREOF - Photovoltaic cells having copper contacts can be made by using copper nanoparticles during their fabrication. Such photovoltaic cells can include a copper-based current collector located on a semiconductor substrate having an n-doped region and a p-doped region. The semiconductor substrate is configured for receipt of electromagnetic radiation and generation of an electrical current therefrom. The copper-based current collector includes an electrically conductive diffusion barrier disposed on the semiconductor substrate and a copper contact disposed on the electrically conductive diffusion barrier. The copper contact is formed from copper nanoparticles that have been at least partially fused together. The electrically conductive diffusion barrier limits the passage of copper therethrough. | 2015-09-10 |
20150255664 | HETEROJUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate. | 2015-09-10 |
20150255665 | LASER HEATING TREATMENT METHOD AND METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE - According to one embodiment, a laser heating treatment method includes forming a film having a higher melting point than a structural body provided on a substrate so as to cover the structural body, and heating the structural body by irradiating the film and the structural body with laser. | 2015-09-10 |
20150255666 | MONOLITHIC INTEGRATION OF HETEROJUNCTION SOLAR CELLS - A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure. | 2015-09-10 |
20150255667 | APPARATUS AND METHODS FOR MANUFACTURING THIN-FILM SOLAR CELLS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web. | 2015-09-10 |
20150255668 | THIN FILM INP-BASED SOLAR CELLS USING EPITAXIAL LIFT-OFF - Methods of producing single-junction or multi-junction InP-based solar cells grown latticed-matched on a InP substrate or grown on metamorphic layers on a GaAs substrate, with the substrate subsequently removed in a nondestructive manner via the epitaxial lift-off (ELO) technique, and devices produced using the methods are described herein. | 2015-09-10 |
20150255669 | LIGHT EMITTING ELEMENT - Embodiments of the present invention include a light emitting element, a method for manufacturing the light-emitting element according to one embodiment of the present invention, comprises: a first conductive semiconductor layer | 2015-09-10 |
20150255670 | NITRIDE SEMICONDUCTOR STACKED BODY AND SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, the n-side electron barrier layer is provided at a region close to an end of the active layer on the n-type cladding layer side. The region is located within a range of an electron diffusion length from the active layer. The n-side electron barrier layer prevents electrons having energy which is not more than predetermined energy from being injected into the active layer. | 2015-09-10 |
20150255671 | LIGHT-EMITTING DEVICE - The present disclosure provides a light-emitting device. The light-emitting device comprises a substrate; a light-emitting stack which emits infrared (IR) light on the substrate; and a semiconductor window layer comprising AlGaInP series material disposed between the substrate and the light-emitting stack. | 2015-09-10 |
20150255672 | Device with Transparent and Higher Conductive Regions in Lateral Cross Section of Semiconductor Layer - A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range. | 2015-09-10 |
20150255673 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR PRODUCING THE SAME - A nitride semiconductor light-emitting device has a first conductive-type nitride semiconductor layer, a superlattice layer provided on the first conductive-type nitride semiconductor layer, an active layer provided on the superlattice layer, and a second conductive-type nitride semiconductor layer provided on the active layer. An average carrier concentration of the superlattice layer is higher than an average carrier concentration of the active layer. | 2015-09-10 |
20150255674 | POINT SOURCE LIGHT-EMITTING DIODE - The present invention relates to a point source light-emitting diode containing a support substrate, a metal layer, a first conduction-type layer, an active layer, a second conduction-type layer containing a current-narrowing structure, and a topside electrode having an aperture, stacking in this order, in which the metal layer is provided locally in an area corresponding to the aperture and has a metal reflection face by which a light generated in the active layer is reflected towards the aperture side, and the point source light-emitting diode further contains a light-reflection reduction face having a lower reflectivity and/or a higher absorptivity than the metal reflection face, provided around the metal reflection face. | 2015-09-10 |
20150255675 | LIGHT-EMITTING DEVICE - A light-emitting device, according to one embodiment, comprises a light-emitting structure having a silicon substrate, a first conductive type semiconductor layer disposed on the silicon substrate, an active layer, and a second conductive type semiconductor layer, a conductive layer facing the active layer between the silicon substrate and the first conductive type semiconductor layer, a first electrode which is disposed on the first conductive type semiconductor layer, penetrates or bypasses the first conductive type semiconductor layer, and is electrically connected to the conductive layer, and a second electrode disposed on the second conductive type semiconductor layer. | 2015-09-10 |
20150255676 | LIGHT-EMITTING ELEMENT - A light-emitting element comprises a light-emitting semiconductor stack comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a plurality of extensions formed on the first semiconductor layer; and a first conductive part and a second conductive part formed on the light-emitting semiconductor stack and respectively electrically connected to the first semiconductor layer and the second semiconductor layer, wherein one of the plurality of extensions is formed beyond a projected area of the second conductive part and not covered by the first conductive part. | 2015-09-10 |
20150255677 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME - An optoelectronic device comprises a substrate; pads on a surface of the substrate; semiconductor elements, each element resting on a pad; a portion covering at least the lateral sides of each pad, the portion preventing the growth of the semiconductor elements on the lateral sides; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair. A method of manufacturing an optoelectronic device is also disclosed. | 2015-09-10 |
20150255678 | Method For Producing Group III Nitride Semiconductor Light-Emitting Device - The present invention provides a Group III nitride semiconductor exhibiting reduced contact resistance. A first p-type contact layer of GaN doped with Mg is formed on a p-type cladding layer, using hydrogen as a carrier gas at a growth temperature of 850° C. to 1,050° C., so as to have a thickness of 10 nm to 300 nm. The Mg concentration is 1×10 | 2015-09-10 |
20150255679 | LIGHT-EMITTING DIODE AND METHOD OF FABRICATING THE SAME - A light-emitting diode (LED) including a semiconductor stack structure including a first semiconductor layer, an active layer, and a second semiconductor layer, the semiconductor stack disposed on a substrate, a conductive substrate disposed on the semiconductor stack structure, and an electrode disposed on the conductive substrate and in ohmic contact with the conductive substrate, wherein the electrode comprises grooves penetrating the electrode and a portion of the conductive substrate. | 2015-09-10 |
20150255680 | LIGHT-EMITTING DIODE, LIGHT-EMITTING DIODE LAMP, AND ILLUMINATION DEVICE - In a light-emitting diode, a plurality of dot-shaped ohmic contact electrodes are provided between a metal reflective film and a compound semiconductor layer, an ohmic electrode and a surface electrode composed of a pad portion and a plurality of linear portions connected to the pad portion are provided in that order on the opposite side of the compound semiconductor layer from the semiconductor substrate, the surface of the ohmic electrode is covered with the linear portions, the ohmic contact electrodes and the ohmic electrode are formed in positions that do not overlap with the pad portion in plane view, and among the plurality of ohmic contact electrodes, 5% or more and 40% or less of the ohmic contact electrodes are disposed in positions that overlap with the linear portions in plane view. | 2015-09-10 |
20150255681 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode (LED) chip is disclosed. The chip includes a light-emitting diode and an electrode layer on the light-emitting diode. The electrode layer includes a reflective metal layer. The reflective metal layer includes a first composition and a second composition. The first composition includes aluminum or silver, and the second composition includes copper, silicon, tin, platinum, gold or a combination thereof. The weight percentage of the second composition is greater than 0% and less than 20%. | 2015-09-10 |
20150255682 | Light Emitting Diode and Fabrication Method Thereof - A light emitting diode includes: a substrate; a light-emitting epitaxial layer, from bottom to up, laminated by semiconductor material layers of a first confinement layer, a light-emitting layer and a second confinement layer over the substrate; a current blocking layer over partial region of the light-emitting epitaxial layer; a transparent conducting structure over the current blocking layer that extends to the light-emitting epitaxial layer surface and is divided into a light-emitting region and a non-light-emitting region, in which, the non-light-emitting region corresponds to the current blocking layer with thickness larger than that of the light-emitting region, thus forming a good ohmic contact between this structure and the light-emitting epitaxial layer and reducing light absorption; and a P electrode over the non-light-emitting region of the transparent conducting structure, which guarantees current spreading performance and reduces working voltage and light absorption. | 2015-09-10 |
20150255683 | Method for Fixing a Matrix-Free Electrophoretically Deposited Layer on a Semiconductor Chip for the Production of a Radiation-Emitting Semiconductor Component, and Radiation-Emitting Semiconductor Component - A method can be used for fixing a matrix-free electrophoretically deposited layer on a semiconductor chip. A semiconductor wafer has a carrier substrate-and at least one semiconductor chip. The at least one semiconductor chip has an active zone for generating electromagnetic radiation. At least one contact area is formed on a surface of the at least one semiconductor chip facing away from the carrier substrate. A material is electrophoretically deposited on the surface of the at least one semiconductor chip facing away from the carrier substrate in order to form the electrophoretically deposited layer. Deposition of the material on the at least one contact area is prevented. An inorganic matrix material is applied to at least one section of a surface of the semiconductor wafer facing away from the carrier substrate in order to fix the material on the at least one semiconductor chip. | 2015-09-10 |
20150255684 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device includes: a laminated structure, a first electrode, a second electrode and a dielectric laminated film. The laminated structure includes, a first semiconductor layer, a second semiconductor layer, and a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer, in which the second semiconductor layer and the light-emitting layer are selectively removed and a part of the first semiconductor layer is exposed to a first main surface on the side of the second semiconductor layer. The first electrode is provided on the first main surface of the laminated structure and connected to the first semiconductor layer and has a first region including a first metal film provided on the first semiconductor layer of the first main surface, and a second region including a second metal film provided on the first semiconductor layer and having a higher reflectance for light emitted from the light-emitting layer than the first metal film and having a higher contact resistance with respect to the first semiconductor layer than the first metal film. The second electrode is provided on the first main surface of the laminated structure and connected to the second semiconductor layer. The dielectric laminated film is provided on the first and second semiconductor layer being not covered with the first and second electrode and has a plurality of dielectric films having different refractive indices being laminated. | 2015-09-10 |
20150255685 | METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - The invention relates to an optoelectronic component and a method for producing an optoelectronic component, wherein a layer structure having a positively doped semiconductor layer ( | 2015-09-10 |
20150255686 | WAFER-LEVEL LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emitting diode (LED) package includes a plurality of light emitting cells each including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a plurality of contact holes arranged in the second conductive type semiconductor layer and the active layer of each of the light emitting cells, the contact holes exposing the first conductive type semiconductor layer of each of the light emitting cells; a connector located arranged on a first side of the light emitting cells and electrically connecting two adjacent light emitting cells to each other; a first bump arranged on the first side of the light emitting cells; and a second bump arranged on the first side of the light emitting cells. | 2015-09-10 |
20150255687 | LED Lens Design with More Uniform Color-Over-Angle Emission - An LED device with improved angular color performance has a silicone lens shaped as a portion of a sphere. The lens is molded over an array of LED dies disposed on the upper surface of a substrate. Phosphor particles are disbursed throughout the material used to mold the lens. The distance between farthest-apart edges of the LED dies is more than half of the length that the lens extends over the surface of the substrate. The distance from the top of the lens dome to the surface of the substrate is between 57% and 73% of the radius of the sphere. Shaping the lens as the top two thirds of a hemisphere reduces the non-uniformity in the emitted color such that neither of the CIE color coordinates x or y of the color changes more than 0.004 over all emission angles relative to the surface of the substrate. | 2015-09-10 |
20150255688 | Converter Material, Method for Producing a Converter Material, and Optoelectronic Component - A converter material includes a porous inorganic matrix material having a multiplicity of pores. A multiplicity of inorganic nanoparticles are applied on the surface of the matrix material. The nanoparticles are suitable for converting electromagnetic radiation in a first wavelength range into electromagnetic radiation in a second wavelength range. A method for producing such a converter material and an optoelectronic component that includes such a converter material are furthermore specified. | 2015-09-10 |
20150255689 | Comprehensive Light-Emitting Diode Device and Lighting-Module - A comprehensive light-emitting diode device including a translucent substrate, a light-emitting diode chip, a reflective layer, a first wavelength conversion layer, and a second wavelength conversion layer. The translucent substrate includes a first surface and a second surface opposite to the first surface. The light-emitting diode chip is disposed on the first surface. The reflective layer is disposed on the first surface. The light-emitting diode chip is surrounded by the reflective layer. The first wavelength conversion layer is disposed on the first surface. The light-emitting diode chip and the reflective layer are covered by the first wavelength conversion layer. | 2015-09-10 |
20150255690 | Methods for fabricating quantum dot polymer films - The addition of a chain transfer agent (CTA) or a reversible-addition fragmentation chain transfer agent (RAFT CTA) such as (2-(dodecyl-thiocarbonothioylthio)-2-methylpropionic acid) during the formation of quantum dot polymer films yields films characterized by high and stable quantum yields. | 2015-09-10 |
20150255691 | OPTOELECTRONIC COMPONENT - An optoelectronic component comprises:—at least one semiconductor chip suitable for generating electromagnetic radiation,—a beam shaping element ( | 2015-09-10 |
20150255692 | Method for Producing an Optoelectronic Semiconductor Chip with Reflective Electrode - A method for producing an optoelectronic semiconductor chip is disclosed. In some embodiment the method includes arranging a metallic mirror layer on a top side of a semiconductor layer sequence, arranging a mirror protection layer at least on exposed lateral surfaces of the mirror layer in a self-aligning manner, wherein the mirror layer has openings toward the semiconductor layer sequence, and wherein the openings are framed in lateral directions by the mirror protection layer and partially removing the semiconductor layer sequence in a region of the openings of the mirror layer. | 2015-09-10 |
20150255693 | OPTOELECTRONIC COMPONENT DEVICE AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT DEVICE - An optoelectronic component device includes first and second electrodes; a first optoelectronic component electrically coupled to the first and second electrodes; and a first electrically conductive section electrically coupled to the first electrode, and a second electrically conductive section electrically coupled to the second electrode; wherein the first and second electrically conductive sections are arranged electrically in parallel with the first optoelectronic component; wherein the first and second electrically conductive sections are arranged and configured relative to one another such that, beyond a response voltage applied over the first and second conductive sections, a discharge path is formed between the first and second conductive sections; and wherein the response voltage has as its value a value formed greater than the threshold voltage value of the first optoelectronic component and less than or equal to the value of the breakdown voltage of the first optoelectronic component. | 2015-09-10 |
20150255694 | LIGHT EMITTING DEVICE PACKAGE - The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device. | 2015-09-10 |
20150255695 | (Zr,Hf)3Ni3Sb4-BASED n-TYPE THERMOELECTRIC CONVERSION MATERIAL - An n-type thermoelectric conversion material expressed in a chemical formula X | 2015-09-10 |