37th week of 2015 patent applcation highlights part 52 |
Patent application number | Title | Published |
20150255196 | Magneto-Dielectric Polymer Nanocomposites and Method of Making - In accordance with the present invention, novel superparamagnetic magneto-dielectric polymer nanocomposites are synthesized using a novel process. The tunability of the dielectric/magnetic properties demonstrated by this novel highly-viscous solvent-free polymer nanocomposite that is amenable to building 3D electromagnetic structures/devices by using processes such as 3D printing, compression molding or injection molding, when an external DC magnetic field is applied, exceeds what has been previously reported for magneto-dielectric polymer nanocomposite materials. | 2015-09-10 |
20150255197 | SINTERED FERRITE MAGNET AND MOTOR PROVIDED THEREWITH - A sintered ferrite magnet comprises a main phase of an M type Sr ferrite having a hexagonal crystal structure. An amount of Zn is 0.05 to 1.35 mass % in terms of ZnO, the sintered ferrite magnet does not substantially include a rare-earth element (R), and the following Formula (1) is satisfied, where a total amount of Sr, Ba and Ca is M3 in terms of mol, a total amount of Fe, Co, Mn, Zn, Cr and Al is M4 in terms of mol, and an amount of Si is M5 in terms of mol. | 2015-09-10 |
20150255198 | SINTERED FERRITE MAGNET AND MOTOR PROVIDED THEREWITH - A sintered ferrite magnet comprises a main phase of an M type Sr ferrite having a hexagonal crystal structure. An amount of Zn is 0.05 to 1.35 mass % in terms of ZnO and M1/M2 is 0.43 or less when an amount of a rare-earth element (R) is M1 in terms of mol and the amount of Zn is M2 in terms of mol. | 2015-09-10 |
20150255199 | IRON COBALT TERNARY ALLOY NANOPARTICLES WITH SILICA SHELLS AND METAL SILICATE INTERFACE - Superparamagnetic core-shell nanoparticles having a core of an iron cobalt ternary alloy, a shell of a silicon oxide on the core and a metal silicate interface layer between the core and the shell layer are provided. Methods to prepare the nanoparticles are also provided. | 2015-09-10 |
20150255200 | Fast Superconducting Switch for Superconducting Power Devices - A superconducting magnetic energy storage device that can maintain a large ratio of the stored energy to the static energy loss, and has the ability to by-pass the current through a fast, high-voltage superconducting switch. More particularly, this invention relates to the design and application of novel high-voltage superconducting switch provided with a direct heating of the active superconducting layer through a metal substrate either by transport or by inductive current, and the protection of the superconducting layer by cryogenically-cooled metal-oxide-semiconductor field-effect transistors. | 2015-09-10 |
20150255201 | VARIABLE-CYCLE PERMANENT-MAGNET UNDULATOR - A variable-period permanent-magnet undulator which is applicable not only to a planar undulator but also to a helical undulator, in which permanent-magnets and ferromagnetic substances are alternately arranged, and the ferromagnetic substance interposed between the permanent-magnets is saturated to thus enable the magnets to be effectively spaced apart from each other by the repulsive force between the permanent-magnets, thereby adjusting the period of the magnetic field in an easy and precise manner. | 2015-09-10 |
20150255202 | SYSTEM AND METHOD FOR IMPACT ON THE- STRUCTURE OF SUBSTANCES BY MEANS OF LOW ENERGY MODULATED MAGNETIC FIELD - System and method for impact on the structure of substances by means of low energy modulated magnetic field ( | 2015-09-10 |
20150255203 | MAGNET CORE, IN PARTICULAR FOR A CURRENT TRANSFORMER, AND METHOD FOR PRODUCING SAME - Magnet core comprising a nanocrystalline alloy based on iron which has a permeability μ of between 1000 and 3500 and a magnetostriction of less than 1 ppm, which magnet core has a core mass of less than 4.7 g in the case of a maximum tolerance to unipolar current amplitudes of 60 A or a core mass of less than 5.3 g in the case of a maximum tolerance to unipolar current amplitudes of 100 A. | 2015-09-10 |
20150255204 | CHOKE COIL - Disclosed herein is a choke coil including: a core composed of first and second legs, a first flat plate connecting an upper end portion of the first leg and that of the second leg, and a second flat plate connecting a lower end portion of the first leg and that of the second leg; a primary coil wound around the first leg; and a secondary coil wound around the second leg, wherein a width of at least any one of the first flat plate and the second flat plate is greater than widths of the first leg and the second leg. | 2015-09-10 |
20150255205 | ELECTRIC VEHICLE INDUCTION COIL HOUSING WITH INTERENGAGEMENT STRUCTURE FOR FERRITE TILE ASSEMBLIES - Systems and methods for implementing interengagement structures for a ferrite tile assembly of an induction coil housing are described herein. One aspect of the subject matter described in the disclosure is a housing. The housing includes a base forming a receptacle. The housing further includes a ferrite tile assembly. The housing further includes an interengagement structure extending from the base and configured to secure the ferrite tile assembly relative to the base within the receptacle. | 2015-09-10 |
20150255206 | CHIP ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - The manufacturing method of a chip electronic component may include: forming a coil pattern part on at least one surface of an insulating substrate; forming a thin polymer insulating film to follow a surface shape of the coil pattern part; forming a primer insulating layer on one surface of a magnetic sheet; disposing the magnetic sheet on which the primer insulating layer is formed on an upper portion and a lower portion of the insulating substrate on which the coil pattern part is formed and pressing the magnetic sheet to form a magnetic body in which an additional insulating film is formed on the coil pattern part; and forming an external electrode on at least one end surface of the magnetic body so as to be connected to the coil pattern part. | 2015-09-10 |
20150255207 | STRUCTURE AND METHOD FOR A TRANSFORMER WITH MAGNETIC FEATURES - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 2015-09-10 |
20150255208 | CHIP ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - A chip electronic component may include an internal coil structure for preventing the occurrence of short-circuits between coil patterns and may have a high aspect ratio (AR) by increasing a thickness of the coil with respect to a width of the coil. The chip electronic component may include a magnetic body including an insulating substrate; an internal coil part formed on at least one surface of the insulating substrate; external electrodes formed on at least one end surface of the magnetic body and connected to the internal coil part. Insoluble films may be formed on side portions of coil patterns forming the internal coil part, and the internal coil part may have an aspect ratio of 1.5 or greater. | 2015-09-10 |
20150255209 | INTEGRATED CAPACITOR AND INDUCTOR HAVING CO-LOCATED MAGNETIC AND ELECTRICAL ENERGY STORAGE VOLUMES - A combination capacitor and inductor employ a common volume for energy storing electrical and magnetic fields thereby reducing the bulk of these components with respect to separate components of comparable value. | 2015-09-10 |
20150255210 | Electron-Coupled Transformer - An Electron-coupled transformer for generating a high voltage output pulse as an amplified version of an input pulse comprises a cylindrical triode electron tube with a central anode along main axis and a grid and cathode radially spaced from the anode. The anode has a first end connected to ground and a second end insulated with respect to said ground. The cathode and the grid form a traveling wave electron gun that produces a wave of ground potential in the Transverse Electric Mode, which causes electrons stored in the cathode-grid gap to be extracted from said gap. The extracted electrons form a radially symmetric collapsing traveling wave that sweeps as a wave along the anode at the speed of light, causing a voltage output pulse on the second end of the anode whose magnitude is an amplified version of an input pulse applied to the cathode. | 2015-09-10 |
20150255211 | Manufacturing Method of Common Grain-Oriented Silicon Steel with High Magnetic Induction - A manufacturing method of oriented silicon steel with magnetic induction B8 of not less than 1.88 T, comprising the following steps: 1) smelting and continuous casting to obtain a slab, wherein the content of N is controlled at 0.002-0.014 wt % in the smelting stage; 2) hot-rolling; 3) cold-rolling; 4) decarbonizing and annealing; 5) nitriding treatment, wherein infiltrated nitrogen content [N] | 2015-09-10 |
20150255212 | LAMINATED FILM CAPACITOR, FILM CAPACITOR MODULE, AND POWER CONVERSION SYSTEM - A laminated film capacitor that includes a laminated body of first capacitance electrodes and second capacitance electrodes stacked to be opposed to each other with dielectric films interposed therebetween. A first external electrode is electrically connected to the first capacitance electrodes and a second external electrode is electrically connected to the second capacitance electrodes. The laminated film capacitor includes heat dissipators that are connected to the external electrodes, and higher in heat dissipation performance than at least one of the first capacitance electrodes and second capacitance electrodes. The heat dissipators are larger in thickness than at least one of the first capacitance electrodes and second capacitance electrodes. | 2015-09-10 |
20150255213 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND ASSEMBLY BOARD HAVING THE SAME - The present application describes a multilayer ceramic electronic component including a ceramic body having a thickness greater than a width and includes a dielectric layers, and has upper and lower surfaces opposing each other in a thickness direction. First and second side surfaces oppose each other in a width direction, and first and second end surfaces oppose each other in a length direction. First and second internal electrodes are stacked with at least one of the dielectric layers interposed therebetween within the ceramic body in the width direction. A volume increasing part is disposed in a lower portion of the ceramic body in the thickness direction to allow a volume of a lower margin portion of the ceramic body to be greater than that of an upper margin portion thereof. | 2015-09-10 |
20150255214 | CERAMIC POWDER AND MULTI-LAYER CERAMIC CAPACITOR - A multi-layer ceramic capacitor is made by alternately layering a dielectric layer constituted by a sintered body of a ceramic powder, and an internal electrode layer. The ceramic powder contains, as a main composition, barium titanate powder having a perovskite structure with a median size of 200 nm or smaller as measured by SEM observation, wherein the barium titanate powder is such that the percentage of barium titanate particle having twin defects in the barium titanate powder is less than 10% as measured by TEM observation and that its crystal lattice c/a is 1.0075 or more. | 2015-09-10 |
20150255215 | ELECTRONIC COMPONENT - An electronic component comprises an element body, an external electrode, and an insulating resin coating layer. The element body has a pair of end faces opposed to each other, a pair of principal faces extending so as to connect the pair of end faces and opposed to each other, and a pair of side faces extending so as to connect the pair of principal faces and opposed to each other. The external electrode is formed so as to cover at least a partial region of the principal face and/or a partial region of the side face and has a plating layer comprised of Sn or an Sn alloy. The insulating resin coating layer covers at least the portion of the external electrode formed so as to cover the side face. | 2015-09-10 |
20150255216 | CAPACITOR WITH LOW EQUIVALENT SERIES INDUCTANCE - A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding. | 2015-09-10 |
20150255217 | LAMINATED FILM CAPACITOR, CAPACITOR MODULE, AND POWER CONVERSION SYSTEM - A laminated film capacitor that includes a laminated body having alternately stacked first dielectric films with respective first internal electrodes and second dielectric films with respective second internal electrodes, a first metallikon part connected to the first internal electrodes, and a second metallikon part connected to the second internal electrodes, and the laminated body has principal surfaces in the shape of a trapezoid as viewed from the stacking direction of the first dielectric films and the second dielectric films. | 2015-09-10 |
20150255218 | Power Factor Correction Capacitors - An apparatus includes a case capable of receiving a plurality of capacitive elements, each capacitor element having at least two capacitors, and each capacitor having a capacitive value. The apparatus also includes a cover assembly with a peripheral edge secured to the case. The cover assembly includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly generally at a central region of the cover assembly. Each cover terminal is connected to one of the at least two capacitors of the respective one of the plurality of capacitive elements. The cover assembly also includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly at a position spaced apart from the cover terminal generally at the central region of the cover assembly. | 2015-09-10 |
20150255219 | CAPACITOR CIRCUIT FOR A QUASI-BROADBAND DOHERTY AMPLIFIER - An amplifier provides a first amplifier circuit, a second amplifier circuit, a first hybrid-coupler circuit and a termination. The hybrid-coupler circuit provides an output terminal and an insulation terminal. In this context, the termination is connected to the insulation terminal of the hybrid-coupler circuit. The termination comprises a first capacitor and/or an inductance, which is disposed directly at the insulation terminal of the hybrid-coupler circuit. | 2015-09-10 |
20150255220 | SOLID ELECTROLYTE CAPACITOR AND MANUFACTURING METHOD FOR SAME - A solid electrolyte capacitor includes an anode foil on a surface of which an oxide film is formed, a cathode foil, and a separator. A gap between the anode foil and the cathode foil is filled with a solid electrolyte which contains a conductive fine particles containing a conductive polymer compound and a hydrophilic polymer compound. The hydrophilic polymer compound has a structure expressed by a following chemical formula (I) and a structure expressed by a following chemical formula (II). | 2015-09-10 |
20150255221 | Use of Mixtures of Self-Doped and Foreign-Doped Conductive Polymers in a Capacitor - Described are methods for the production of a capacitor, comprising the process steps:
| 2015-09-10 |
20150255222 | POLYMERIZATION LIQUID, CONDUCTIVE POLYMER FILM OBTAINED FROM POLYMERIZATION LIQUID, AND SOLID ELECTROLYTIC CAPACITOR - Provided is a polymerization liquid for electropolymerization, which uses a solvent that is mainly composed of water, which is greatly increased in the amount of a monomer contained therein, and which is capable of quickly forming a conductive polymer layer having high conductivity and heat resistance, A polymerization liquid for electropolymerization of the present invention contains: a solvent that is composed of 100-80% by mass of water and 0-20% by mass of an organic solvent; at least one monomer having a pi-conjugated double bond; at least one supporting electrolyte; and at least two nonionic surfactants. The at least two nonionic surfactants are composed of at least one acetylenol surfactant and at least one water-soluble nonionic surfactant other than the acetylenol surfactant. Due to the combination of the two nonionic surfactants, the amount of the monomer emulsified with the solvent can be greatly increased. | 2015-09-10 |
20150255223 | Method for Manufacturing Solid Electrolytic Capacitor, and Solid Electrolytic Capacitor - A method for manufacturing a solid electrolytic capacitor with excellent ESR properties and a solid electrolytic capacitor. A method for manufacturing a solid electrolytic capacitor, wherein an anode body is obtained by forming a dielectric oxide film on the surface of a sintered body that is formed by sintering a molded body formed of a valve acting metal powder or on the surface of a roughened valve acting metal foil, and a solid electrolyte layer is formed on the surface of the anode body. This method for manufacturing a solid electrolytic capacitor is characterized by steps for forming a solid electrolyte layer including a protrusion forming process where protrusions formed of manganese dioxide and having an average diameter of 10-102 nm are formed on the surface of the dielectric oxide coating film so that the protrusions are scattered about like islands and the surface coverage is 1˜and a conductive polymer layer forming process where a conductive polymer layer is formed on the surfaces of the projections and the dielectric oxide coating film. | 2015-09-10 |
20150255224 | METHOD FOR IMPROVING EFFICIENCY OF ELECTROLYTE HAVING LONG TERM STABILITY AND DYE SENSITIZED SOLAR CELL FOR VEHICLE USING THE SAME - Disclosed is a nonvolatile electrolyte and a method for manufacturing a dye sensitized solar cell using the nonvolatile electrolyte. In particular, the electrolyte may maintain stability during a durability test of a solar cell module. Moreover, sealing breakage of a module occurring in the related arts may be prevented, and ion mobility may be improved thereby improving efficiency. | 2015-09-10 |
20150255225 | ELECTRIC STORAGE APPARATUS - An electric storage apparatus includes a plurality of electric storage elements, a bus bar electrically connecting the plurality of electric storage elements, and a case housing the plurality of electric storage elements. Each of the electric storage elements extends in a predetermined direction and has a positive electrode terminal and a negative electrode terminal at both ends in the predetermined direction. The plurality of electric storage elements are aligned in a plane orthogonal to the predetermined direction. The case has an opening portion configured to pass a heat exchange medium therethrough and extending in the predetermined direction. A portion of the bus bar extends in the predetermined direction and is disposed along a wall face of the case having the opening portion formed therein, the portion being disposed at a position different from a position of the opening portion. | 2015-09-10 |
20150255226 | Apparatus and Methods for Electrical Energy Harvesting and/or Wireless Communication - Apparatus including an electric double layer capacitor having a first surface and a second surface, the first surface being opposite the second surface; a first conductor positioned adjacent the first surface and configured to function as a current collector for the electric double layer capacitor, and having a first electrical length to resonate in a first operational frequency band; and a second conductor positioned adjacent the second surface and configured to function as a current collector for the electric double layer capacitor. | 2015-09-10 |
20150255227 | SELF-HEALING COMPOSITE, SELF-HEALING SUPERCAPACITOR AND METHODS OF FABRICATION THEREOF - There is provided a self-healing composite including a supramolecular polymeric network of molecules cross-linked through reversible bonds, and nanostructures incorporated into the supramolecular polymeric network, the nanostructures and the supramolecular polymeric network being cross-linked through reversible bonds. In particular, the supramolecular network has a glass transition temperature (Tg) of about 10° C. to about 50° C. There is also provided a self-healing supercapacitor incorporating the self-healing composite and an electrode incorporating the self-healing composite. | 2015-09-10 |
20150255228 | MINITYPE BREAKER WITH HIGH STABILITY - A high-stability miniature circuit breaker includes an operating mechanism, wherein a pivotal shaft of the operating mechanism fixed on a shell includes a first shaft section, a second shaft section and a shaft shoulder; the diameter of the second shaft section is larger than that of the first shaft section, and the diameter of the shaft shoulder is larger than that of the second shaft section. A lever is installed on the first shaft section through a first shaft hole in a pivoting way and used for limiting the axial position of a protruding mesa relative to the pivotal shaft through contact fit between the protruding mesa disposed on the lever and a thrust surface on the second shaft section. A latch assembly is installed on the second shaft section through a second shaft hole in a pivoting way; a first end face fitted with a support surface on the shaft shoulder is disposed at one end of the second shaft hole; and a second end face fitted with the protruding mesa is disposed at the other end of the second shaft hole. A first hasp fitted with a second hasp of the latch assembly is disposed on a connecting rod, the connecting rod is engaged with each other with the latch assembly in the first and second hasp contact and withhold state, and the latch assembly controls a drive rod and the lever not to move relatively; the connecting rod is separated from the latch assembly when the first and second hasps are separated and unbuckled, and the latch assembly is separated from the drive rod, so that the drive rod can slide along a groove of the lever. | 2015-09-10 |
20150255229 | Switch Device with Erroneous Operation Preventer and the Erroneous Operation Preventer - A switch device with an erroneous operation preventer, including: a switch main body having a switch member supported by a shaft with respect to a casing and configured such that pushing a first end portion of the switch member causes a second end portion thereof to protrude and such that an on state and an off state of the switch main body are changed by pushing one of the first and second end portions; and a frame-shaped erroneous operation preventer disposed around the switch member for preventing an erroneous operation on the first end portion that takes a protruding posture when the switch main body is in one of the on and off states, the preventer having side protective walls extending in a longitudinal direction of the switch member so as to cover a surface of a flange portion of the casing on both sides of the first end portion. | 2015-09-10 |
20150255230 | INDICATOR LAMP - An indicator lamp is disclosed, in particular for an electromechanical command device. The indicator lamp includes a housing and a light source, which is arranged in the housing and emits light when supplied with energy. Furthermore, a lens arrangement is provided, including a first lens unit, which is arranged in the propagation direction of the light emitted by the light source and is built such that light beams emitted by the light source exit substantially parallel from a side of the first lens unit that faces away from the light source. The lens arrangement includes a second lens, which is arranged on the side of the first lens unit that faces away from the light source and is built such that some of the light beams exiting from the first lens unit are directed with respect to the propagation direction towards a transparent side surface of the housing. | 2015-09-10 |
20150255231 | FLOATING SWITCH ASSEMBLIES AND METHODS FOR MAKING THE SAME - Switch assemblies that mitigate stack up variations and methods of making the same are provided. The stack up variations are mitigated by embodiments that use a floating switch design. The floating switch design may eliminate height variations in the stack up by directly mounting an activation assembly to a support bracket. This ensures that the stack up height of the activation assembly and support bracket remain fixed, independent of a flexible printed circuit board (PCB) that may also be secured to the activation assembly. This way, regardless of the thickness of the flexible PCB and any height variations in solder used to secure the flexible PCB to the activation assembly, the stack up height of the activation assembly and support bracket remains fixed. | 2015-09-10 |
20150255232 | KEYBOARD WITH GEL CONTAINING CHAMBERS IN KEY CAP - A device is provided. The device includes a first T-shaped structure defined via a first leg and a first platform. The device further includes a key cap with an interior open chamber. The cap is mounted onto the first structure such that the chamber contains the first platform. The device also includes a second T-shaped structure defined via a second leg and a second platform. The first leg vertically moves within the second leg such that the cap travels between a depressed position and a pressed position. The cap is raised above the second platform in the depressed position. The cap is in contact with the second platform in the pressed position. | 2015-09-10 |
20150255233 | FLIP SWITCH TIMER DECORATOR SWITCH CLIP - A clip member that attaches to the actuator of a flip switch timer for a toggle switch to allow the flip switch timer to actuate a decorator switch between on and off positions. The clip member may include a connector or fastener including a pair of arms having clips for engaging a slot on the actuator. A lever arm on the switch engages the raised end of a decorator switch when the actuator, and thus the clip member, are moved linearly within the flip switch timer. | 2015-09-10 |
20150255234 | MULTIDIRECTIONAL SWITCH - There is provided a multidirectional switch in which, when a knob in a neutral position is operated to be tilted with respect to a reference axis at the time the knob is in the neutral position, a pressing part positioned in an operating direction side of the knob moves in an axial direction of the reference axis to selectively close a switch element corresponding to the moved pressing part. The switch element and the pressing part respectively comprise four switch elements and four pressing parts that are respectively provided at intervals each having 90 degrees in the circumferential direction around the reference axis, and one pressing part is connected to another pressing part adjacent thereto in the circumferential direction around the reference axis by a flexible connecting element formed in a wave shape as viewed in a radial direction of the reference axis. | 2015-09-10 |
20150255235 | CONTACT DEVICE - In a contact device, rotational movement of a movable contactor with a yoke attached is regulated by the fact that the yoke abuts against a wall surface of a wall portion. In an event where the movable contactor with the yoke attached moves rotationally, the yoke is allowed to abut against only a wall surface in one region obtained by dividing the wall surface by a virtual line passing through a rotation center of the yoke. | 2015-09-10 |
20150255236 | CONTACT APPARATUS - A contact apparatus is provided and includes fixed terminals having fixed contacts, a movable contact member having the movable contacts provided on one surface thereof so as to come into contact or out of contact with the fixed contacts, a first yoke arranged at one side of said one surface of the movable contact member, and a second yoke arranged at a side of the other surface of the movable contact member, the second yoke having one surface facing the first yoke through the movable contact member. The first yoke is larger in volume than the second yoke. | 2015-09-10 |
20150255237 | Electrical Component and Method for Establishing Contact with an Electrical Component - An electrical component includes at least one external contact having a first metallization and a second metallization. The metallizations are fired and the second metallization only partly covers the first metallization. Furthermore, an electrical component includes at least one frame-shaped metallization. Furthermore, an electrical component includes a first and second metallization that have a different wettability with solder material. | 2015-09-10 |
20150255238 | CONTROLLABLE ELECTRONIC SWITCH - A controllable electronic switch for, e.g., controlling power distribution comprises a deformable member such as a bimetal arm that can be deformed to break an electrical path. The deformable member may be anchored at one end and in controllable contact with an electrical conductor at the other end. A heating element, such as a coil, can be used to selectively heat the deformable member. The controllable electronic switch can alternatively comprise a deformable member that is terminated in a wedge-shaped member. When the deformable member bends in response to being heated, the wedge-shaped member forces apart a pair of contacts thus breaking an electrical path. The wedge-shaped member and/or associated structures may be configured as a cam mechanism with multiple latching positions. | 2015-09-10 |
20150255239 | NANO GRANULAR MATERIALS (NGM) MATERIAL, METHODS AND ARRANGEMENTS FOR MANUFACTURING SAID MATERIAL AND ELECTRICAL COMPONENTS COMPRISING SAID MATERIAL - Nano granular materials (NGM) are provided that have the extraordinary capability to conduct current in a 100 fold current density compared to high Tc superconductors by charges moving in form of Bosons produced by Bose-Einstein-Condensation (BEC) in overlapping excitonic surface orbital states at room temperature and has a light dependent conductivity. The material is disposed between electrically conductive connections and is a nano-crystalline composite material. Also provided are electrical components comprising NGM and methods and arrangements for making it by corpuscular-beam induced deposition applied to a substrate, using inorganic compounds being adsorbed on the surface of the substrate owing to their vapor pressure, and which render a crystalline conducting phase embedded in an inorganic insolating matrix enclosing the material. | 2015-09-10 |
20150255240 | Method for Manufacturing Electron Source - A conventional method to process a tip fails to designate the dimension of the shape of the end of the tip, and so fails to obtain a tip having any desired diameter. Impurities may be attached to the tip. Based on a correlation between the voltage applied or the time during processing of the end of the tip and the diameter of the tip end, the applied voltage is controlled so as to obtain a desired diameter of the tip end for processing of the tip. This allows a sharpened tip made of a tungsten monocrystal thin wire to be manufactured to have any desired diameter in the range of 0.1 μm or more and 2.0 μm or less. | 2015-09-10 |
20150255241 | INTEGRATED PHOTOEMISSION SOURCES AND SCALABLE PHOTOEMISSION STRUCTURES - A scalable, integrated photoemitter device and method of manufacture using conventional CMOS manufacturing techniques. The photoemitter device has a first semiconductor substrate having a plurality of photonic sources formed on top in a first material layer, the plurality of photonic sources and the material layer forming a planar surface. A second substrate is bonded to the planar surface, the second substrate having a plurality of photoemitter structures formed on top in a second material layer, each photoemitter structure in alignment with a respective photonic source of the first substrate and configured to generate particle beams responsive to light from a respective light source. Additionally provided is a multi-level photoemitter of tapered design for implementation in the scalable, integrated photoemitter device. Conventional CMOS manufacturing techniques are also implemented to build the multi-level photoemitter of tapered design. | 2015-09-10 |
20150255242 | PLASMA-BASED MATERIAL MODIFICATION USING A PLASMA SOURCE WITH MAGNETIC CONFINEMENT - A plasma-based material modification system for material modification of a work piece may include a plasma source chamber coupled to a process chamber. A support structure, configured to support the work piece, may be disposed within the process chamber. The plasma source chamber may include a first plurality of magnets, a second plurality of magnets, and a third plurality of magnets that surround a plasma generation region within the plasma source chamber. The plasma source chamber may be configured to generate a plasma having ions within the plasma generation region. The third plurality of magnets may be configured to confine a majority of electrons of the plasma having energy greater than 10 eV within the plasma generation region while allowing ions from the plasma to pass through the third plurality of magnets into the process chamber for material modification of the work piece. | 2015-09-10 |
20150255243 | GRAZING ANGLE PLASMA PROCESSING FOR MODIFYING A SUBSTRATE SURFACE - Embodiments of the disclosure provide apparatus and methods for modifying a surface of a substrate using a plasma modification process. In one embodiment, a process generally includes the removal and/or redistribution of a portion of an exposed surface of the substrate by use of an energetic particle beam while the substrate is disposed within a particle beam modification apparatus. Embodiments may also provide a plasma modification process that includes one or more pre-planarization processing steps and/or one or more post-planarization processing steps that are all performed within one processing system. Some embodiments may provide an apparatus and methods for planarizing a surface of a substrate by performing all of the plasma modification processes within either the same processing chamber, the same processing system or within processing chambers found in two or more processing systems. | 2015-09-10 |
20150255244 | Sample Storage Container, Charged Particle Beam Apparatus, and Image Acquiring Method - A sample storage container of the present invention includes: a storage container ( | 2015-09-10 |
20150255245 | Charged Particle Beam System - A charged particle beam system capable of suppressing drift of a functional component used in association with a sample is offered. The charged particle beam system ( | 2015-09-10 |
20150255246 | SAMPLE MICROMOTION MECHANISM, METHOD OF USING THE SAME, AND CHARGED PARTICLE DEVICE - Provided is a sample micromotion mechanism adapted to minimize an influence of a disturbance and adjust a sample drift rapidly and with high accuracy, and designed so as to be a compact, easy-to-place sample micromotion mechanism of a side-entry type that suppresses the occurrence of the sample drift and generates/displays high-resolution monitoring images and precisely drawn patterns. A charged particle device employing the sample micromotion mechanism is also provided. | 2015-09-10 |
20150255247 | ANALYSIS APPARATUS AND ANALYSIS METHOD - In accordance with an embodiment, an analysis apparatus includes a secondary electron optical system, at least one detector, and a composition analysis unit. The secondary electron optical system includes a charged particle beam source and a lens. The charged particle beam source generates a charged particle beam and irradiates a sample with it. The lens controls a focal position and a trajectory of the charged particle beam using an electric field or a magnetic field. The detector detects a characteristic X-ray from the sample. The composition analysis unit analyzes a composition of a material constituting the sample from the detected characteristic X-ray. Each detector is arranged in such a manner that at least part of a detection surface thereof is placed on the same plane as an exit surface of the secondary electron optical system, or placed on the charged particle beam side of the same plane. | 2015-09-10 |
20150255248 | Methods, Apparatuses, Systems and Software for Treatment of a Specimen by Ion-Milling - Methods, apparatuses, systems and software for ion beam milling or machining are disclosed. The apparatus includes a specimen holder, a table, one or more ion sources, rotatable ion optics, and an imaging device. The specimen holder is configured to hold a specimen in a stationary position during milling or machining. The table is configured to change the stationary position of the specimen holder in any of three orthogonal linear directions and an angular direction. The rotatable ion optics are configured to emit an ion beam towards a predetermined location on the specimen from any of the one or more ion sources at any angle around an axis that is orthogonal to a horizontal surface of the table when the angular direction of the table is 0°. The imaging device is configured to generate an image of the specimen including the predetermined location, thereby enabling real-time monitoring of the milling or machining process. | 2015-09-10 |
20150255249 | MULTI CHARGED PARTICLE BEAM WRITING APPARATUS - A multi charged particle beam writing apparatus includes an aperture member to form multiple beams, a blanking plate in which there are arranged a plurality of blankers to respectively perform blanking deflection for a corresponding beam in the multiple beams having passed through a plurality of openings of the aperture member, a blanking aperture member to block each beam having been deflected to be in OFF state by at least one of the plurality of blankers, a first grating lens, using the aperture member as gratings, to correct spherical aberration of the charged particle beam, and a correction lens configured to correct high order spherical aberration produced by the first grating lens. | 2015-09-10 |
20150255250 | Charged Particle Beam Device and Sample Preparation Method - Provided is a charged particle beam device provided with: a charged particle source; an objective lens for focusing a charged particle beam emitted from the charged particle source onto a sample; a detector for detecting a secondary charged particle emitted from the sample; a probe capable of coming into contact with the sample; a gas nozzle for emitting conductive gas to the sample; and a control unit for controlling the drive of the probe and gas emission from the gas nozzle, wherein before bringing the probe into contact with the sample after applying the charged particle beam to the sample to machine the sample, the control unit emits gas toward a machining position from the gas nozzle and applies the charged particle beam to form a conductive film on a machining portion of the sample, and the charged particle beam device is provided with a contact detection unit for determining that the conductive film formed on the machining portion and the probe have come into contact with each other. | 2015-09-10 |
20150255251 | HALL EFFECT ENHANCED CAPACITIVELY COUPLED PLASMA SOURCE - Embodiments disclosed herein include a plasma source for abating compounds produced in semiconductor processes. The plasma source has a first plate and a second plate parallel to the first plate. An electrode is disposed between the first and second plates and an outer wall is disposed between the first and second plates surrounding the cylindrical electrode. The plasma source has a first plurality of magnets disposed on the first plate and a second plurality of magnets disposed on the second plate. The magnetic field created by the first and second plurality of magnets is substantially perpendicular to the electric field created between the electrode and the outer wall. In this configuration, a dense plasma is created. | 2015-09-10 |
20150255252 | Apparatus and Method for Applying Surface Coatings - The present invention provides a method for applying a surface coating on, for example, a sheet of fabric and further provides a plasma chamber ( | 2015-09-10 |
20150255253 | VACUUM CHAMBER ELEMENTS MADE OF ALUMINUM ALLOY - The invention relates to a vacuum chamber element obtained by machining and surface treatment of a plate of thickness at least equal to 10 mm of aluminum alloy, composed as follows (as a percentage by weight), Si: 0.4-0.7; Mg: 0.4-0.7; Ti 0.01-<0.15, Fe<0.25; Cu<0.04; Mn<0.4; Cr 0.01-<0.1; Zn<0.04; other elements <0.05 each and <0.15 in total, the rest aluminum. The invention also relates to a manufacturing method for a vacuum chamber element wherein successively a plate with a thickness of at least 10 mm of aluminum alloy of series 5XXX or series 6XXX is provided, said plate is machined to a vacuum chamber element, said element is degreased and/or pickled, it is anodized at a temperature of between 10 and 30° C. with a solution comprising 100 to 300 g/l of sulfuric acid and 10 to 30 g/l of oxalic acid and 5 to 30 g/l of at least one polyol, optionally the anodized product is hydrated in deionized water at a temperature of at least 98° C. preferably for a period of at least about 1 h. Products according to the invention have an improved property homogeneity and an advantageous resistance to corrosion. | 2015-09-10 |
20150255254 | APPARATUS AND METHOD FOR THE PLASMA COATING OF A SUBSTRATE, IN PARTICULAR A PRESS PLATEN - An apparatus ( | 2015-09-10 |
20150255255 | PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD AND STORAGE MEDIUM FOR STORING PROGRAM FOR EXECUTING THE METHOD - There is provided a plasma processing apparatus including a susceptor, having a substrate mounting portion for mounting thereon a substrate; a focus ring including an outer ring and an inner ring; a dielectric ring; a dielectric constant varying device for varying a dielectric constant of the dielectric ring; a grounding body positioned at an outside of the dielectric ring with a gap from a bottom surface of the focus ring; and a controller for controlling a top surface electric potential of the focus ring by controlling a current flowing from the susceptor to the substrate. | 2015-09-10 |
20150255256 | HALL EFFECT ENHANCED CAPACITIVELY COUPLED PLASMA SOURCE, AN ABATEMENT SYSTEM, AND VACUUM PROCESSING SYSTEM - Embodiments disclosed herein include an abatement system for abating compounds produced in semiconductor processes. The abatement system includes a plasma source that has a first plate and a second plate parallel to the first plate. An electrode is disposed between the first and second plates and an outer wall is disposed between the first and second plates surrounding the electrode. The plasma source has a first plurality of magnets disposed on the first plate and a second plurality of magnets disposed on the second plate. The magnetic field created by the first and second plurality of magnets is substantially perpendicular to the electric field created between the electrode and the outer wall. In this configuration, a dense plasma is created. | 2015-09-10 |
20150255257 | SUBSTRATE COOLING MEMBER, SUBSTRATE PROCESSING DEVICE, AND SUBSTRATE PROCESSING METHOD - An objective of the present invention is to simplify a configuration of a processing chamber for cooling a substrate in a substrate processing device. In a plasma processing device ( | 2015-09-10 |
20150255258 | PLASMA PROCESSING APPARATUS AND SUBSTRATE PROCESSING APPARATUS PROVIDED WITH SAME - Provided is a plasma processing apparatus including: a rotary mounting table supported by a rotatory shaft arranged rotatably within a processing chamber and including multiple substrate placement units arranged side by side in a circumferential direction; a processing gas supplying section for supplying processing gas into the processing chamber; a plasma generating section wherein multiple microwave introducing mechanisms, each provided on the ceiling of the processing chamber so as to face the rotary mounting table and used for generating a plasma of the processing gas, are arranged in multiple rows spaced apart from each other from the inside of the movement path of the substrates when the rotary mounting table is rotated to the outside, each row of microwave introducing mechanisms being formed by arranging the microwave introducing mechanisms annularly side by side along the circumferential direction; and an exhaust unit that evacuates an inside of the processing chamber. | 2015-09-10 |
20150255259 | WAFERLESS CLEAN IN DIELECTRIC ETCH PROCESS - A system and method for a waferless cleaning method for a capacitive coupled plasma system. The method includes forming a protective layer on a top surface of an electrostatic chuck, volatilizing etch byproducts deposited on one or more inner surfaces of the plasma process chamber, removing volatilized etch byproducts from the plasma process chamber and removing the protective layer from the top surface of the electrostatic chuck. A capacitive coupled plasma system including a waferless cleaning recipe is also described. | 2015-09-10 |
20150255260 | NbO2 Sintered Compact, Sputtering Target Comprising the Sintered Compact, and Method of Producing NbO2 Sintered Compact - The present invention relates to a NbO | 2015-09-10 |
20150255261 | APPARATUS AND METHODS FOR MICROBIOLOGICAL ANALYSIS - Methods and systems for identification of microorganisms either after isolation from a culture or directly from a sample. The methods and systems are configured to identify microorganisms based on the characterization of proteins of the microorganisms via high-resolution/mass accuracy single-stage (MS) or multi-stage (MS | 2015-09-10 |
20150255262 | Apparatus and Method for Improving Throughput in Spectrometry - The invention provides a method and apparatus for improving throughput in spectrometry, the method comprising the steps of loading sample-containing liquid into a liquid injection device through a first outlet in the injection device, and ejecting at least some of the sample-containing liquid from the liquid injection device either in the form of droplets or in the form of a jet which subsequently breaks up into droplets due to instability; characterized by the sample ejection being through the first outlet of the liquid injection device in a direction such that the sample-containing fluid enters an inlet of a torch. | 2015-09-10 |
20150255263 | ION SELECTION METHOD IN ION TRAP AND ION TRAP SYSTEM - Provided is an ion selection method capable of isolating and leaving a target ion in an ion trap within a short period of time and with high separating power. In a digital ion trap, after ions over a wide range of m/z near a target ion are selectively retained by rough isolation using an FNF signal or the like (S | 2015-09-10 |
20150255264 | METHOD OF EXTRACTING IONS WITH A LOW M/Z RATIO FROM AN ION TRAP - In a mass spectrometer, a method for trapping ions includes providing at least first and second multipole rod sets positioned in tandem, introducing a plurality of ions into the first rod set, applying an RF potential to at least one of said rod sets to generate a radial trapping potential within said rod sets, applying a radial DC potential to said first rod set so as to modulate said radial trapping potential set as a function of m/z of said ions, and applying a DC potential between said two rod sets to provide an axial bias potential between said two rod sets. The method can further comprise selecting an axial barrier potential to selectively extract ions having an m/z ratio less than a threshold from said first rod set into said second rod set. | 2015-09-10 |
20150255265 | ION TRAP-BASED APPARATUS AND METHOD FOR ANALYZING AND DETECTING BIPOLAR ION - An ion trap-based device and method for analyzing and detecting bipolar ions is provided. The device includes multiple electrodes of an ion trap; a radio frequency voltage source configured to form a radio frequency electric field; a direct current voltage source configured to form a bias electric field, positive and negative ions in the ion trap being separated by the bias electric field; a first and second detectors, configured to detect the positive and negative ions, respectively. A bipole and quadrupole field direct current voltage detection modes may be employed. A single positive ion or negative ion operation mode in a conventional biological mass spectrometry method is improved, so that the positive and negative ion modes are performed simultaneously; without any resolution loss, the analysis speed is increased, the sample consumption is reduced, and the accuracy of quantitative analysis of the samples is improved. | 2015-09-10 |
20150255266 | ETCHING DEVICE, ETCHING METHOD AND PATTERNING APPARATUS - The present invention provides an etching device, which comprises a treatment solution tank for containing treatment solution; and a grabbing unit for putting the substrate in the treatment solution tank and moving the treated substrate out of the treatment solution tank. Accordingly, the present invention further provides an etching method for treating a substrate by using the above etching device. The present invention further provides a patterning apparatus comprising the above etching device. According to the present invention, the uniformity of a reaction between the treatment solution and a corresponding material on the substrate can be improved, and damages which may be caused to the pattern by the existing spray mode can be avoided. | 2015-09-10 |
20150255267 | Atomic Layer Deposition of Aluminum-doped High-k Films - Embodiments of the invention describe methods for forming a semiconductor device. According to one embodiment, the method includes depositing an aluminum-doped high-k film on a substrate by atomic layer deposition (ALD) that includes: a) pulsing a metal-containing precursor gas into a process chamber containing the substrate, b) pulsing an aluminum-containing precursor gas into the process chamber, where a) and b) are sequentially performed without an intervening oxidation step, and c) pulsing an oxygen-containing gas into the process chamber. The method can further include heat-treating the aluminum-doped high-k film to crystallize or increase the crystallization of the film. | 2015-09-10 |
20150255268 | METHOD FOR FABRICATING OXIDES/SEMICONDUCTOR INTERFACES - By depositing a layer of metal on the semiconductor surface where the metal is deposited in a non-oxidized state first and then depositing a layer of the high-k oxide material over the layer of metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface. | 2015-09-10 |
20150255269 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device is provided. The method includes treating a surface of an insulating film formed on a substrate by supplying a first gas containing a halogen group to the substrate, and forming a thin film containing a predetermined element on the treated surface of the insulating film by performing a cycle a predetermined number of times. The cycle includes supplying a second gas containing the predetermined element and a halogen group to the substrate, and supplying a third gas to the substrate. | 2015-09-10 |
20150255270 | INTEGRATED PLATFORM FOR IMPROVED WAFER MANUFACTURING QUALITY - The present disclosure relates to a method and apparatus for performing a dry plasma procedure, while mitigating internal contamination of a semiconductor substrate. In some embodiments, the apparatus includes a semiconductor processing tool having a dry process stage with one or more dry process elements that perform a dry plasma procedure on a semiconductor substrate received from an input port. A wafer transport system transports the semiconductor substrates from the dry process stage to a wet cleaning stage located downstream of the dry process stage. The wet cleaning stage has one or more wet cleaning elements that perform a wet cleaning procedure to remove contaminants from a surface of the semiconductor substrates before the semiconductor substrate is provided to an output port, thereby improving wafer manufacturing quality. | 2015-09-10 |
20150255271 | SUBSTRATE TREATMENT METHOD, COMPUTER STORAGE MEDIUM, AND SUBSTRATE TREATMENT SYSTEM - The present invention is configured to: form, on a substrate, a neutral layer having an intermediate affinity to a hydrophilic polymer and a hydrophobic polymer; form a resist pattern by performing exposure processing on a resist film formed on the neutral layer and then developing the resist film after the exposure processing; perform a surface treatment on the resist pattern by supplying an organic solvent having a polarity to the resist pattern; apply the block copolymer onto the neutral layer; and phase-separate the block copolymer on the neutral layer into the hydrophilic polymer and the hydrophobic polymer. | 2015-09-10 |
20150255272 | SYSTEM, METHOD AND RETICLE FOR IMPROVED PATTERN QUALITY IN EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY AND METHOD FOR FORMING THE RETICLE - A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained. | 2015-09-10 |
20150255273 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a die including a first surface, a recess extended from an aperture disposed on the first surface and including a sidewall disposed within the die, and a polymeric member configured for filling and sealing the recess and including a first outer surface and a second outer surface, wherein the first outer surface is interfaced with the sidewall of the recess. | 2015-09-10 |
20150255274 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A technique includes forming a film containing a first element, a second element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: forming a first layer containing the first element and carbon by supplying a precursor gas having a chemical bond of the first element and carbon from a first supply part to the substrate in a process chamber, and forming a second layer by supplying a reaction gas containing the second element from a second supply part to the substrate in the process chamber and supplying a plasma-excited inert gas from a third supply part to the substrate in the process chamber to modify the first layer, the third supply part being different from the second supply part. | 2015-09-10 |
20150255275 | High Performance Self Aligned Contacts and Method of Forming Same - A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region. | 2015-09-10 |
20150255276 | ORGANOMETALLIC PRECURSORS AND METHODS OF FORMING THIN LAYERS USING THE SAME - An organometallic precursor is represented by a chemical formula of Xn(M)(R1)m(R2)k. M is a central metal. X is a ligand of M and one of 6,6-dimethylfulvenyl, indenyl, cyclopentadienyl and cyclopentadienyl substituted with an amino group. R1 and R2 are ligands of M, and each independently an amino group or an ethylenediamino group. Each n, m and k is a positive integer, and a sum of n, m and k is equal to 3 or 4. | 2015-09-10 |
20150255277 | CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS - Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface. | 2015-09-10 |
20150255278 | THIN FILM TRANSISTOR, THIN FILM TRANSISTOR SUBSTRATE, DISPLAY APPARATUS AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR - A thin film transistor including a gate electrode; an active layer insulated from the gate electrode; a source electrode and a drain electrode that are insulated from the gate electrode and are electrically connected to the active layer; a first etch stopper layer that is formed of an insulation material and contacts a portion of the active layer located between areas of the active layer that are electrically connected to the source electrode and the drain electrode; a second etch stopper layer on the first etch stopper layer, the second etch stopper layer being formed of an insulation material of a same type as the insulation material used to form the first etch stopper layer, the second etch stopper layer having a higher density than the first etch stopper layer; and a third etch stopper layer on the second etch stopper layer. | 2015-09-10 |
20150255279 | SILICON CARBIDE SUBSTRATE, SILICON CARBIDE INGOT, AND METHODS FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE INGOT - A silicon carbide substrate, a silicon carbide ingot, and methods for manufacturing the silicon carbide substrate and the silicon carbide ingot capable of improving a yield of a semiconductor device having silicon carbide as constituent material are provided. In the silicon carbide substrate, patterns formed by crossing straight lines extending along the <11-20> direction and being observable by means of an X-ray topography are present at a number density of less than or equal to 0.1 patterns/cm | 2015-09-10 |
20150255280 | THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES - Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer. | 2015-09-10 |
20150255281 | SILICON SUBSTRATE PREPARATION FOR SELECTIVE III-V EPITAXY - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. | 2015-09-10 |
20150255282 | METHOD OF FABRICATING POLYSILICON LAYER, THIN FILM TRANSISTOR, ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME - A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer. | 2015-09-10 |
20150255283 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 2015-09-10 |
20150255284 | SELF-ALIGNED VIA PATTERNING WITH MULTI-COLORED PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS - Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material. | 2015-09-10 |
20150255285 | METHOD AND APPARATUSES FOR REDUCING POROGEN ACCUMULATION FROM A UV-CURE CHAMBER - Porogen accumulation in a UV-cure chamber is reduced by removing outgassed porogen through a heated outlet while purge gas is flowed across a window through which a wafer is exposed to UV light. A purge ring having specific major and minor exhaust to inlet area ratios may be partially made of flame polished quartz to improve flow dynamics. The reduction in porogen accumulation allows more wafers to be processed between chamber cleans, thus improving throughput and cost. | 2015-09-10 |
20150255286 | DEEP WELL IMPLANT USING BLOCKING MASK - Various methods include: forming an opening in a resist layer to expose a portion of an underlying blocking layer; performing an etch on the exposed portion of the blocking layer to expose a portion of an etch stop layer, wherein the etch stop layer resists etching during the etch of the exposed portion of the blocking layer; etching the exposed portion of the etch stop layer to expose a portion of a substrate below the exposed portion of the etch stop layer and leave a remaining portion of the etch stop layer; and ion implanting the exposed portion of the substrate, wherein the blocking layer prevents ion implanting of the substrate outside of the exposed portion. | 2015-09-10 |
20150255287 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To improve characteristics of a semiconductor device. | 2015-09-10 |
20150255288 | PLATE-LIKE OBJECT PROCESSING METHOD - A plate-like object processing method for processing a plate-like object including a substrate and a laminate formed on a front surface of the substrate, includes a substrate exposing step of exposing the substrate by removing the laminate by irradiating a region in which the laminate of the plate-like object is desired to be removed with a laser beam set at an energy density that destroys the laminate but does not destroy the substrate. | 2015-09-10 |
20150255289 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure is disclosed. The method comprises: a) providing an SOI substrate, and forming a gate stack on the SOI substrate; b) conducting amorphous implantation to source/drain regions, wherein process temperature of the amorphous implantation to the source region is higher than process temperature of the amorphous implantation to the drain region; c)performing the source/drain region doping; d) annealing to activate the impurities and recrystallize the amorphous region of the source/drain regions. In step b), the process temperature is higher than 50 in the amorphous implantation to the source region whereas the process temperature is lower than −30 in the amorphous implantation to the drain region. The present invention provides a method to generate defects under the source region. The defects can serve as discharge channels for the charges accumulated in the bulk region to reduce the impact of the floating bulk effect and to improve the reliability of the device. | 2015-09-10 |
20150255290 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An insulating film ( | 2015-09-10 |
20150255291 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region. | 2015-09-10 |
20150255292 | FORMING A VTFT WITH ALIGNED GATE - A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure and in the reentrant profile. A photoresist is deposited on the conformal conductive inorganic thin film over the gate structure and filling the reentrant profile. The photoresist is exposed from a side of the photoresist opposite the substrate allowing the photoresist in the reentrant profile to remain unexposed. The conformal conductive inorganic thin film is etched in areas not protected by the photoresist to form a patterned conductive gate layer located in the reentrant profile of the gate structure. | 2015-09-10 |
20150255293 | PLANARIZATION PROCESS - Planarization processing methods are disclosed. In one aspect, the method includes patterning a material layer and planarizing the patterned material layer by using sputtering. Due to the patterning of the material layer, the loading requirements of nonuniformity on a substrate for sputtering the material layer are reduced, compared with that before the patterning. | 2015-09-10 |
20150255294 | LOWERING PARASITIC CAPACITANCE OF REPLACEMENT METAL GATE PROCESSES - The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance. | 2015-09-10 |
20150255295 | METHODS OF FORMING ALTERNATIVE CHANNEL MATERIALS ON A NON-PLANAR SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure. | 2015-09-10 |