35th week of 2011 patent applcation highlights part 22 |
Patent application number | Title | Published |
20110211363 | OMNIDIRECTIONALLY ILLUMINATED SPORT BOARD - An illuminated sport board/skateboard emits light from both the top and bottom of the board to yield a significant quantum of light for optimal visibility and safety. A base panel is provided having an underside surface with at least one transparent segment aligned with an inlay cavity within the base's interior core. A battery powered lighting source containing a plurality of light emitting diodes or an electroluminescent lighting strip is housed within the inlay cavity. A top shell having at least one transparent display is attached to the base panel in a manner that aligns the transparent display with the LED emitted or electroluminescent lighting. Light is emitted from both the top and bottom of the board owing emission through the transparent display of the top shell and the transparent segment of the base panel. The illuminated sport board may be constructed as a skateboard, snowboard, or skis to provide safety from vehicles and other recreational participants. | 2011-09-01 |
20110211364 | Rotating Fiber Optic Sculpture - A sculpted decorative object, such as a Christmas tree, is shown which has a motor driven vertical drive shaft and three rotating sections. Rotation of the vertical drive shaft and an associated drive gear causes relative rotation of a driven gear and, in turn, a respective rotating section of the object about the axis of the drive shaft. A fiber optic bundle is mounted within each rotating section of the object. Each bundle contains several fiber optic strands which terminate at a LED light source at one end and at a light emitting element at an opposite end. Each LED light source is supplied from a common electrical source by means of a series of wiper contacts and rotatable contact rings carried by respective stationary and rotating portions of the sculpted object. | 2011-09-01 |
20110211365 | LIGHT GUIDE PLATE, AND BACKLIGHT UNIT - Provided are a light guide plate and a backlight unit. The backlight unit includes A light guide plate comprising a first light guide member having a first inclined plane and a second light guide member having a second inclined plane and having a refractive index different from that of the first light guide member, and the first light guide member located on the second light guide member to face the first inclined plane and the second inclined plane; an optical member on the light guide plate; a first light emitting module located at a lateral surface of the first light guide member; a second light emitting module located at a lateral surface of the second light guide member; and a reflective member located below the second light guide member. | 2011-09-01 |
20110211366 | BACKLIGHT MODULE - A backlight module includes a light guide plate having a light incident surface, a light source module, at least one catch member, and a cushion member. The light source module is disposed adjacent to the light incident surface and has at least one light-emitting element, wherein a light beam emitted by the light-emitting element is capable of entering the light guide plate through the light incident surface. The catch member engages with one end of the light source module, wherein the catch member has at least one extension part extending towards the light incident surface of the light guide plate, and the extension part has an end surface facing the light incident surface. The cushion member is disposed between the light guide plate and the light source module and is adjacent to the light incident surface of the light guide plate and the end surface of the catch member. | 2011-09-01 |
20110211367 | REFLECTIVE PLATE, PLANAR LAMP AND PLANAR LAMP FIXTURE INCLUDING THE SAME - A directional prism reflective plate includes a prism surface ( | 2011-09-01 |
20110211368 | LIGHT GUIDE PLATE, WIRING MODULE AND ELECTRONIC APPLIANCE - A light guide plate has a substantially flat shape and used as a backlight for an electronic appliance. The light guide plate introduces thereinto illuminating light emitted from a light source through part of a side surface thereof and directs the illuminating light out of the light guide plate through light emitting parts formed in a main surface of the light guide plate, in which a light-receiving surface for the illuminating light on the side surface is inclined relative to a plane perpendicular to the main surface. Thus, illuminating light is refracted, enters the light guide plate, and propagates in the light guide plate while undergoing total internal reflection. Light can be effectively directed out of the light guide plate through the light emitting parts. Thus, a light guide plate with which power saving and reduction in thickness can be achieved by improving light use efficiency, a wiring module in which the light guide plate is used, and an electronic appliance in which the light guide plate or the wiring module is used are provided. | 2011-09-01 |
20110211369 | LOW OUTPUT VOLTAGE CONVERTER UTILIZING DISTRIBUTED SECONDARY CIRCUITS - Embodiments of the present invention relate to a low-output voltage converter, delivering voltage power less than 1 VDC, utilizing distributed secondary circuits. In one embodiment of the present invention, there is provided a voltage converter comprises a primary circuit for receiving an input voltage, comprising a plurality of primary windings arranged in series, a plurality of secondary circuits, each comprising a secondary winding for aligning with a primary winding to form a transformer, and each of the secondary circuits arranged in parallel, and an output for providing an output voltage down to, or less than 1 VDC. | 2011-09-01 |
20110211370 | Systems and Methods of Resonant DC/DC Conversion - Systems and methods of resonant DC/DC conversion disclosed herein improve the basic resonant converter designs by proactively setting and coordinating the gate drive timings between the primary side and secondary side. By proactively setting and coordinating gate drives timings between the primary side and secondary side, both efficiency and transient performance optimizations may be achieved with or without diode emulation mode, depending on whether the switching frequency is below resonance or above resonance, and the nature of the load characteristics. If the switching frequency of the converter is determined to be at or below the resonance frequency, the output transistors may be configured to be fully active at or above a predetermined output load current. The turn-on timing of the output transistors is dependant on the load for a given output voltage, and is almost independent of input voltage. Turn-on timing may be significantly different at light load to no load. | 2011-09-01 |
20110211371 | DUAL DRIVE SYSTEM FOR TRANSFORMER ISOLATED HALF BRIDGE AND FULL BRIDGE FORWARD CONVERTERS - The present invention relates to a power converter circuit for operating on a DC input voltage comprising a forward ferrite-core transformer having at least two primary windings and at least one secondary winding, at least one automatic switching device provided between the primary windings, a current sense circuit provided between the first primary winding and the automatic switching device, and a control unit having a voltage sense circuit, the control unit being connected to the automatic switching device and the current sense circuit and being configured to operate the automatic switch on the basis of an input parameter, thereby controlling the out put voltage. | 2011-09-01 |
20110211372 | COMPENSATION CIRCUITS AND CONTROL METHODS OF SWITCHED MODE POWER SUPPLY - A compensation circuit has a resistor, a switch and a compensation capacitor. The resistor and the switch are connected in series between a power node and a compensation node. The compensation capacitor is connected to the compensation node, whose voltage is responsive to the output power source. For a predetermined period of time after the voltage falls below a predetermined value, the switch is open and no current flows through the resistor from the power node to the compensation node. | 2011-09-01 |
20110211373 | METHOD AND APPARATUS TO REDUCE AUDIO FREQUENCIES IN A SWITCHING POWER SUPPLY - An example controller for use in a power supply regulator includes a switch signal generator, a modulation circuit, and a multi-cycle modulator circuit. The modulation circuit modulates the duty cycle of a pulse width modulated switching signal to provide a fixed peak switching current in the switch during light load conditions and a variable peak switching current during load conditions other than the light load condition. The multi-cycle modulator circuit enables the switch signal generator to provide a switch signal uninterrupted if the load condition is other than the light load condition and disables the switch signal generator for a first time period and then enables the switch signal generator for a second time period when the load condition is the light load condition. The multi-cycle modulator circuit adjusts the first time period in response to the feedback signal to regulate the output. | 2011-09-01 |
20110211374 | POWER SUPPLY DEVICE - The present power supply device includes a microcomputer that detects a current input to an active filter, a voltage input to the active filter, and a voltage output from the active filter, decreases a target voltage as the input current increases, and controls an IGBT to turn on/off the IGBT to match the input current and the input voltage in phase with each other and also match the output voltage to the target voltage. Thus, as the input current increases, the target voltage is decreased. A loss caused at the IGBT can be reduced to be small | 2011-09-01 |
20110211375 | POWER FACTOR CORRECTION CONVERTER - A power factor correction converter includes an output voltage error amplifier which functions as a proportioning device in a low-frequency range in order to stabilize the output voltage by feedback control and obtains a reference current amplitude value vm by multiplying an error ev between a desired output voltage value Vref and a detected output voltage value vo by a predetermined proportionality factor. A factor element multiplies the reference current amplitude value by a predetermined factor and adds the resulting value to a reference value to obtain a desired output voltage value. The factor element functions as a low-pass filter by changing the desired output voltage value Vref in accordance with the reference current amplitude value vm in a low-frequency range and reducing the factor value in a high-frequency range. | 2011-09-01 |
20110211376 | SWITCHING CONTROL CIRCUIT AND SWITCHING POWER SUPPLY DEVICE - A switching control IC outputs a rectangular wave signal from an output terminal thereof to a driving circuit. A feedback circuit compares a value of a divided voltage of a voltage across output terminals of a switching power supply device with a reference voltage, generates a feedback signal, and inputs the feedback signal into a feedback terminal of the switching control IC. A capacitor and a Zener diode are connected between the feedback terminal and a ground terminal. The Zener diode is selectively connected, and a voltage at the feedback terminal is changed in accordance with the presence of the Zener diode. A voltage at the feedback terminal is detected, and one of a latch method and a hiccup method is selected as a method for an overcurrent protection operation in accordance with the detected voltage. | 2011-09-01 |
20110211377 | POWER FACTOR CORRECTION CONVERTER - A PFC converter that rapidly and highly accurately detects current passing through an inductor so as to properly improve harmonics and the power factor as well as to correctly detect the operation state. In the PFC converter, a first current value is obtained by performing sampling at the middle portion of the on-period of a switching element, and a second current value is obtained by performing sampling at the middle portion of the off-period thereof. If the first current value and the second current value are equal or substantially equal to each other, then it is determined that the operation state is a continuous current mode, and if the first current value and the second current value are not equal or substantially equal to each other, then it is determined that the operation state is a discontinuous current mode. | 2011-09-01 |
20110211378 | Utility for full wave rectified current-fed class of DC galvanically isolated DC-to-DC power conversion topologies allows reduction of working voltage magnitudes and improvement to efficiency for secondary circuits - New utility of an existing class of DC galvanically isolated current sourcing circuit topologies for power conversion simultaneously allows improvement in its secondary circuit(s) to power conversion efficiency and reduction in working voltage magnitudes, or simply reduction in working voltage magnitudes, with resulting benefits for reduction in manufacturing cost, reduction in size and weight, and increase in market acceptance, or may simply allow secondary circuit(s) to enable easier provisioning of safety, improvement in reliability, or improvement in efficiency. The magnitude of DC output voltage is optimized at higher value for greater efficiency, while simultaneously optimizing the secondary circuit's working voltage maximum magnitude at a lower value for greater safety. The method requires full cycle current-compliant input impedance of the secondary power source whereby the secondary of the DC galvanically isolating device behaves in a mode of being a full cycle voltage-compliant current source. | 2011-09-01 |
20110211379 | POWER CONVERTER WITH REVERSE RECOVERY AVOIDANCE - A power converter includes a reverse-recovery avoidance scheme. The power converter may include deliver current from a direct current (DC) power source to an alternating current (AC) load. A first switch and second switch of the power converter may be operated to supply the AC load with positive current respective to the AC load from the DC power source. A third and fourth switch of the power converter may be operated to supply the AC load with negative current respective to the AC load from the DC power source. A first diode may be electrically coupled in series with the second switch and second diode may be electrically coupled in parallel with the first diode and the second switch. The second diode may conduct the positive current when the first switch is off and the second switch is on. A third diode may be electrically coupled in series with the fourth switch and a fourth diode may be electrically coupled in parallel with the third diode and the fourth switch. The fourth diode may conduct the negative current when the third switch is off and the fourth switch is on. | 2011-09-01 |
20110211380 | THREE-QUARTER BRIDGE POWER CONVERTERS FOR WIRELESS POWER TRANSFER APPLICATIONS AND OTHER APPLICATIONS - A three-quarter bridge power converter includes a first switch configured to selectively couple a switch node to a higher voltage. The power converter also includes a second switch configured to selectively couple the switch node to a lower voltage. The power converter further includes a third switch configured to selectively cause a third voltage to be provided to the switch node when the first and second switches are not coupling the switch node to the higher and lower voltages. The third switch may be configured to selectively couple the switch node to an energy storage or energy source, such as a capacitor. The third switch may also be configured to selectively couple an energy storage or energy source to ground, where the energy storage or energy source is coupled to the switch node. | 2011-09-01 |
20110211381 | POWER CONVERTING APPARATUS - A neutral point clamped three-phase three-level inverter is connected to a first DC power supply and single-phase inverters are connected in series with AC output lines of individual phases of the three-phase three-level inverter such that sums of output voltages of the three-phase three-level inverter and output voltages of the respective single-phase inverters are output to a load through a smoothing filter. An output control unit controls the three-phase three-level inverter so that the individual phases of the three-phase three-level inverter output primary voltage pulses at a rate of one pulse per half cycle and controls the individual single-phase inverters by PWM, so that output voltages to the individual phases of the load form sine waves of which phases are offset by 2π/3 from one phase to another, the sine waves having the same peak value. | 2011-09-01 |
20110211382 | HIGH DENSITY AND LOW VARIABILITY READ ONLY MEMORY - A read-only memory for storing two data values using a single transistor includes a word line, a pair of bit lines, a select line, and a transistor to store data corresponding to each bit lines in the pair of bit lines. The gate terminal of the transistor is connected to the word line, a first diffusion terminal of the transistor is connected to one of the first bit line and the select line based on the first data value and a second diffusion terminal of the transistor is connected to one of the second bit line and the select line based on the second data value. | 2011-09-01 |
20110211383 | INTEGRATED CIRCUIT HAVING VARIABLE MEMORY ARRAY POWER SUPPLY VOLTAGE - An integrated circuit comprises a memory array and a bias circuit. The memory array comprises a plurality of memory cells arranged in a grid of rows and columns. A first conductor is coupled to a power supply voltage terminal of each of the plurality of memory cells. A second conductor is coupled to receive a power supply voltage. The memory array also includes a plurality of dummy cells. A transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode. The bias circuit is coupled to the control electrode of the transistor. | 2011-09-01 |
20110211384 | STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES - Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors. | 2011-09-01 |
20110211385 | SEMICONDUCTOR DEVICE - There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell. | 2011-09-01 |
20110211386 | Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors - A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide. | 2011-09-01 |
20110211387 | SCALABLE NONVOLATILE MEMORY - Various magnetoresistive memory cells and architectures are described which enable nonvolatile memories having high information density. | 2011-09-01 |
20110211388 | HIGH GMR STRUCTURE WITH LOW DRIVE FIELDS - Multi-period structures exhibiting giant magnetoresistance (GMR) are described in which the exchange coupling across the active interfaces of the structure is ferromagnetic. | 2011-09-01 |
20110211389 | MAGNETORESISTIVE ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME - The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio. | 2011-09-01 |
20110211390 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided. | 2011-09-01 |
20110211391 | Programmable Resistance Memory - A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses. | 2011-09-01 |
20110211392 | CELL STRING OF A MEMORY CELL ARRAY AND METHOD OF ERASING THE SAME - A cell string included in a memory cell array of a nonvolatile memory device includes a plurality of memory cells, a string select transistor, and a ground select transistor. The plurality of memory cells are connected in series. The string select transistor is connected between a bitline and the plurality of memory cells, and has a structure substantially the same as a structure of each memory cell. The ground select transistor is connected between the plurality of memory cells and a common source line, and has a structure substantially the same as the structure of each memory cell. | 2011-09-01 |
20110211393 | FLASH MEMORY DEVICE AND SET-UP DATA INITIALIZATION METHOD - A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a page buffer and decoder configured to read the set-up data from the set-up data region, and a status detector receiving the set-up data from the page buffer and decoder and configured to discriminate the first data from the second data and generate a Pass/Fail status signal. | 2011-09-01 |
20110211394 | FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION - Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required. | 2011-09-01 |
20110211395 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier. | 2011-09-01 |
20110211396 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - The erase operation of a nonvolatile semiconductor memory is executed by a method including applying an erase pulse to a data erase area in a memory cell array, determining whether the threshold voltage of a memory cell arranged in the data erase area reaches an erase level and outputting a verify result, and determining whether a new erase pulse is applied or a state is shifted to a wait state based on the verify result. The new erase pulse is applied when the threshold voltage does not reach the erase level and the application of the new erase pulse is prohibited and the wait operation is performed when the threshold voltage reaches the erase level. | 2011-09-01 |
20110211397 | PIPE LATCH CIRCUIT AND METHOD FOR OPERATING THE SAME - A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal. | 2011-09-01 |
20110211398 | MEMORY DEVICE AND ASSOCIATED MAIN WORD LINE AND WORD LINE DRIVING CIRCUIT - A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected. | 2011-09-01 |
20110211399 | METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE - In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes. | 2011-09-01 |
20110211400 | GLOBAL BIT SELECT CIRCUIT INTERFACE WITH FALSE WRITE THROUGH BLOCKING - A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation. | 2011-09-01 |
20110211401 | GLOBAL BIT SELECT CIRCUIT INTERFACE WITH SIMPLIFIED WRITE BIT LINE PRECHARGING - A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented on a pair of write data input lines; a pair of complementary global read bit lines in selective communication with the array through local read bit lines, the global read bit lines configured to read data stored in a selected cell and present the read data on a pair of read data output lines; and write control logic configured to control precharging of the global write bit lines independently with respect to the global read bit lines, and wherein a pulse width of write data on the global write bit lines is determined only by a global column select signal. | 2011-09-01 |
20110211402 | LOW POWER FLOATING BODY MEMORY CELL BASED ON LOW-BANDGAP-MATERIAL QUANTUM WELL - Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell. | 2011-09-01 |
20110211403 | BIMODAL MEMORY CONTROLLER - A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller. | 2011-09-01 |
20110211404 | Recalibration Systems and Techniques for Electronic Memory Applications - A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal. | 2011-09-01 |
20110211405 | EXTERNAL SIGNAL INPUT CIRCUIT OF SEMICONDUCTOR MEMORY - In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration. | 2011-09-01 |
20110211406 | ADDRESS DELAY CIRCUIT - An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address. | 2011-09-01 |
20110211407 | SEMICONDUCTOR MEMORY DEVICE AND ASSOCIATED LOCAL SENSE AMPLIFIER - A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit. | 2011-09-01 |
20110211408 | SEMICONDUCTOR STORAGE DEVICE - A voltage of a bit line connected to a memory cell is stepped up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply. | 2011-09-01 |
20110211409 | Embedded Memory Databus Architecture - A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs | 2011-09-01 |
20110211410 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having an open bit line structure includes a normal memory cell block, a reference memory cell block, and a sense amplifier. The normal memory cell block includes a plurality of normal memory cells and a driving bit line connected to the normal memory cells. The reference memory cell block includes a reference bit line connected to a reference cell capacitor. The sense amplifier is configured to sense and amplify voltage levels of the driving bit line and the reference bit line. | 2011-09-01 |
20110211411 | Semiconductor device, information processing system including same, and controller for controlling semiconductor device - To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with a column command, a memory cell selected by the row address and column address in a bank selected by the bank address included in a core chip selected by the chip address is accessed. This can increase the number of banks recognizable to a controller, thereby improving the memory access efficiency of the semiconductor device which includes the plurality of memory chips. | 2011-09-01 |
20110211412 | TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS - Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell. | 2011-09-01 |
20110211413 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal, a second bank selection driving control signal generation unit configured to generate a plurality of second bank selection driving control signals corresponding to the plurality of banks in response to one of a read command signal and a write command signal and in response to the address signal, and an internal voltage driver configured to selectively drive a plurality of internal voltage terminals corresponding to the plurality of banks in response to the plurality of first bank selection driving control signals and the plurality of second bank selection driving control signals. | 2011-09-01 |
20110211414 | SEMICONDUCTOR MEMORY MODULE - A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit width of data. The data is transferred between the first circuit and the plurality of semiconductor memories. | 2011-09-01 |
20110211415 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 2011-09-01 |
20110211416 | CIRCUIT AND METHOD FOR RECOVERING CLOCK DATA IN HIGHLY INTEGRATED SEMICONDUCTOR MEMORY APPARATUS - Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units. | 2011-09-01 |
20110211417 | MEMORY DEVICE WITH PSEUDO DOUBLE CLOCK SIGNALS AND THE METHOD USING THE SAME - A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is | 2011-09-01 |
20110211418 | APPARATUS AND METHOD FOR METERING, MIXING AND PACKAGING SOLID PARTICULATE MATERIAL - The present invention relates to a method and an apparatus to produce solid particulate material from solid particulate components. The components are metered and mixed according to a desired recipe. After having been mixed the material is metered and packaged in a suitable form, e.g. in bags. The apparatus ( | 2011-09-01 |
20110211419 | ERGONOMIC PORTABLE MIXING APPARATUS - An apparatus includes an elongate shaft, a first paddle including a connecting member disposed generally parallel to the shaft and a cross member disposed generally perpendicular to the shaft and coupled thereto, wherein the connecting member includes at least one notch formed along an edge thereof, and a second paddle including a connecting member disposed generally parallel to the shaft and a cross member disposed generally perpendicular to the shaft and coupled thereto, wherein the connecting member includes at least one notch formed along an edge thereof. | 2011-09-01 |
20110211420 | DEVICES FOR CARRYING OUT MECHANICAL, CHEMICAL AND/OR THERMAL PROCESSES - A device for carrying out mechanical, chemical and/or thermal processes in a housing ( | 2011-09-01 |
20110211421 | HORIZONTAL MIXING TRAILER SYSTEM - An apparatus for transporting and mixing materials includes a horizontally disposed container supported by a trailer, a motor mounted on the outside of the container, a shaft coupled to the motor and horizontally disposed in the container, and a mixing pedal coupled to the shaft and horizontally disposed in the container. The apparatus may include adjustably angled mixing pedals, and also adjustably angled fins. The apparatus may include a second chamber in the container including a second motor, a second shaft and a second mixing pedal. The apparatus may include a centrifugal pump for moving fluids into and out of the two chambers, as well as between the two chambers. The centrifugal pump may also power the two motors hydraulically. | 2011-09-01 |
20110211422 | Method to Acquire Simultaneously Seismic Data With Source Arrays Designed for Specific Targets - A method for acquiring seismic data. The method may include towing one or more seismic streamers in the water, towing a first air gun array and a second air gun array in the water at a first depth, and towing a third air gun array and a fourth air gun array in the water at a second depth greater than the first depth. While towing the air gun arrays, the first and second air gun arrays and the third and fourth air gun arrays may be separated by a cross line distance that depends on a separation between the seismic streamers. The method may also include firing seismic energy, by the first, second, third and fourth air gun arrays, through the water into the earth. After firing the seismic energy, the method may record seismic signals reflected from strata in the earth beneath the water. | 2011-09-01 |
20110211423 | Gravity Measurements Using Seismic Streamers - A technique facilitates collection and use of data on subterranean formations. The technique comprises obtaining gravity measurements through the use of seismic streamers. At least one streamer is provided such that each streamer has multiple sensors, e.g. accelerometers. The at least one streamer is towed with a tow vessel, and gravity data are accumulated via the multiple sensors during towing. | 2011-09-01 |
20110211424 | Acoustic Transducer for Swath Beams - A swath beam acoustic transducer ( | 2011-09-01 |
20110211425 | ELECTRONIC TIMER WITH GRAPHIC TIME SCALE DISPLAY PANEL - An electronic timer graphically displaying programmed ON/OFF settings includes a microprocessor; a time setting unit electrically connected to the microprocessor for a user to set at least one programmed ON/OFF setting for at least one selected day; a memory unit electrically connected to the microprocessor for storing the programmed ON/OFF setting; a clock signal generating unit electrically connected to the microprocessor for generating a clock signal to the microprocessor; and a graphic time scale display unit electrically connected to the microprocessor and including a plurality of time scale segments, each of which represents a predetermined time period. The microprocessor calculates based on the programmed ON/OFF settings to derive all the time scale segments that are corresponding to the programmed ON/OFF settings, and drives the graphic time scale display unit to show the time scale segments corresponding to the programmed ON/OFF settings. | 2011-09-01 |
20110211426 | HAMMER FOR A WATCH STRIKING MECHANISM - The hammer ( | 2011-09-01 |
20110211427 | STRIKING MECHANISM FOR A WATCH WITH AN ACTIVE DAMPER COUNTER-SPRING - The watch striking mechanism ( | 2011-09-01 |
20110211428 | HEAT-ASSISTED MAGNETIC RECORDING WITH SHAPED MAGNETIC AND THERMAL FIELDS TO MINIMIZE TRANSITION CURVATURE - Devices and methods are provided for heat-assisted magnetic recording (HAMR). In an illustrative example, a device includes a magnetic write pole having a convex pole tip; a magnetic opposing pole longitudinally displaced from the magnetic write pole; and a thermal-source component disposed proximate to the magnetic write pole and comprising a laterally elongated thermal-source peg disposed proximate to the convex pole tip. | 2011-09-01 |
20110211429 | OPTICAL PICKUP DEVICE AND OPTICAL DISC DEVICE - An optical pickup device includes a plurality of laser light sources emitting laser beams of different oscillation wavelengths, and a plurality of objective lenses on which the laser beams in the form of diverging beams emitted by the plurality of laser light sources are incident, and which directly focus the laser beams onto a recording surface of an optical disc. A rising mirror reflects a laser beam in the form of a diverging beam emitted by a laser light source of a predetermined oscillation wavelength among the plurality of laser light sources so as to lead the laser beam to one of the plurality of objective lenses, and transmits the laser beam in the form of a diverging beam emitted by the other laser light source. As the rising mirror transmits the laser beam in the form of the diverging beam emitted by said other laser light source, astigmatism is generated so as to correct existing astigmatism of the laser beam emitted by said other laser light source. | 2011-09-01 |
20110211430 | Disc discrimination apparatus and method - Detection is made as to at least one of a ratio between a tracking error and a focus error, and a duty cycle of an off-track signal with respect to an optical disc. A decision is made as to whether or not the optical disc is playable on the basis of the detected at least one of the ratio and the duty cycle. The ratio is a ratio of the focus error to the tracking error or a ratio of the tracking error to the focus error. | 2011-09-01 |
20110211431 | SEMICONDUCTOR INTEGRATED CIRCUIT AND DISK RECORDING AND REPRODUCING DRIVE USING THE SAME - The present invention enables a comprehensive evaluation from both of data read from a disk and a servo signal of a servo controller. The present invention provides a semiconductor integrated circuit mountable to a disk recording and reproducing drive, which comprises a signal processor of an RF signal read from a pickup, a servo controller responsive to a servo error signal read from the pickup, a memory controller, and an external interface. The memory controller is supplied with read data and a servo signal and stores the read data and the servo signal in a buffer memory according to a time division process. The read data and the servo signal stored in the buffer memory can be transferred to an external device via the external interface by the memory controller. | 2011-09-01 |
20110211432 | OPTICAL DISC AND OPTICAL DISC APPARATUS - The invention provides an optical disc apparatus which prevents that a laser beam whose power is set at a read power level causes erroneous data recording or deletion. The optical disc apparatus includes an emission controller which controls an amount of an electrical current that a current supply portion supplies to a laser diode in order to control a level of emission power at which the laser diode emits the laser beam. The emission controller has a function to set levels of the emission power at the following transition processings: a transition processing after a read processing and before a write processing, a transition processing after a write processing and before a read processing, a transition processing between two read processings for respective areas, and a transition processing between two write processings for respective areas. | 2011-09-01 |
20110211433 | RECORDING/REPRODUCING METHOD, RECORDING/REPRODUCING APPARATUS AND INFORMATION STORAGE MEDIUM - A recording and/or reproducing method, a recording and/or reproducing apparatus, and an information storage medium are provided. The method of recording data to an information storage medium includes: according to a change in a method of using the information storage medium, rearranging the order of a first information structure with a variable size and a second information structure with a fixed size, both of which are included in management information of the information storage medium, so that the first information structure with the variable size can be positioned following the second information structure with the fixed size; and recording the rearranged management information on the information storage medium. According to the method and apparatus, recording management information can be found in a fixed location of a finalized information storage medium, thereby allowing the recording management information to be found easily and quickly. | 2011-09-01 |
20110211434 | METHOD OF RECOGNIZING TRACK PITCH OF OPTICAL DISK - A method of recognizing a track pitch of an optical disk, adapted for an optical disk player, is provided. The method includes the steps of driving an optical pickup head to a predetermined position, so that the optical pickup head and the spindle motor are a predetermined distance apart, reading a data sector address, and recognizing the magnitude of the track pitch of the optical disk according to the value of the data sector address. | 2011-09-01 |
20110211435 | LASER ATTACHMENT DEVICE AND OPTICAL PICK-UP DEVICE USING THE SAME - A laser attachment device of the present invention is formed of a LD package and a LD holder housing it. A first inner wall of the LD holder to come into contact with a side surface of the LD package is an inclined surface. This allows the facing direction of the LD package to be corrected by the first inner wall being the inclined surface, even when a laser beam emitted from a light emitting chip housed in the LD holder is inclined with respect to an optical axis. Thus, the traveling direction of the laser beam is corrected to the optical axis side. | 2011-09-01 |
20110211436 | Information Processor Device and Storage Medium - In an information storage device in which small partitions for storing information are three-dimensionally placed inside a solid, the invention aims at long-period storage, robustness, and rapid information reading. Accordingly, the stored three-dimensional information is divided into two-dimensional data for each layer, and two-dimensional inverse Fourier transform is previously applied for the two-dimensional data. The two-dimensional data is recorded in each layer in a Z direction inside a storage medium which is solid. When the information is reproduced, electromagnetic waves are irradiated to a storage area MA as gradually rotating the storage area MA around a z axis, and projection images of all layers during the rotation are obtained from response. By applying one-dimensional Fourier transform for a plurality of projection images obtained as described above, the recorded original three-dimensional information is rapidly reproduced. | 2011-09-01 |
20110211437 | OPTICAL PICKUP DEVICE AND OPTICAL DISC APPARATUS - An optical pickup device including: a laser diode for emitting laser light; an objective lens which irradiates an optical beam emitted from the laser diode; an actuator which displaces the objective lens in a radius direction of the optical disc; a grating for branches an optical beam reflected by an information recording layer into plural regions; and one photodetector having plural light receiving parts for receiving the branched optical beams, wherein the photodetector has a first light receiving part which detects zero-th order grating diffracted light and plural second light receiving parts which detecting grating diffracted light having an order not less than that of ±first order grating diffracted light; a detected signal of the zero-th order grating diffracted light is defined as a reproduction signal; and a detected signal of the grating diffracted light is defined as a signal for servo controlling. | 2011-09-01 |
20110211438 | COLLIMATING LENS UNIT AND OPTICAL PICKUP DEVICE USING THE SAME - An optical pickup device that can reduce interlayer crosstalk, without changing the configuration of the optical system, and without excessively increasing the size of the optical system. The optical pickup device reproduces a signal from a multilayered optical information recording medium having a plurality of information recording layers. The optical pickup device uses a collimating lens unit as a collimating optical system that collimates light from a light source, and the collimating lens unit includes a first and second lens group arranged at a predetermined distance from each other so as to form a converged light spot in the interior of the collimating lens unit, and an optical element provided between the first lens group and the second lens group so as to form a light spot at a position defocused from the position of the converged light spot, thereby decreasing quantity of light passing through the collimating lens unit. | 2011-09-01 |
20110211439 | QUALITY OF SERVICE (QoS) ACQUISITION AND PROVISIONING WITHIN A WIRELESS COMMUNICATIONS SYSTEM - In an embodiment, an access network (AN) receives a message configured to prompt a conditional allocation of Quality of Service (QoS) resources to an access terminal (AT). The message can be received from the AT or from an application server (AS) that arbitrates a communication session for the AT. In another embodiment, if the AT determines that a QoS resource request has not yet been granted, the AT waits until the traffic channel (TCH) has been obtained for a communication session before resending the QoS resource request. In another embodiment, if the AT determines to initiate or join a second communication session before a confirmation that QoS resources for a first communication session are relinquished, the AT waits until the confirmation is received before a request for QoS resources for the second communication session is sent. | 2011-09-01 |
20110211440 | METHODS AND SYSTEMS FOR ENABLING END-USER EQUIPMENT AT AN END-USER PREMISE TO EFFECT COMMUNICATIONS HAVING CERTAIN DESTINATIONS WHEN AN ABILITY OF THE END-USER EQUIPMENT TO COMMUNICATE VIA A COMMUNICATION LINK CONNECTING THE END-USER EQUIPMENT TO A COMMUNICATIONS NETWORK IS DISRUPTED - A method for effecting communications, such as telephone calls, accesses to data network sites (e.g., web sites), alarm system communications, and/or other communications, having certain destinations over a communications network. The method comprises: receiving a request for a communication originated by first end-user equipment at a first end-user premise when an ability of the first end-user equipment to communicate via a first communication link connecting the first end-user equipment to the communications network is disrupted; determining, based on a destination of the communication, that the communication is to be effected over the communications network; and causing information pertaining to the communication to be exchanged between the first end-user equipment and the communications network via a wireless communication link established between the first end-user equipment and second end-user equipment at a second end-user premise and a second communication link connecting the second end-user equipment to the communications network. Also provided are apparatus and computer-readable media containing a program element executable by a computing system to perform such a method. | 2011-09-01 |
20110211441 | SEQUENTIAL HEARTBEAT PACKET ARRANGEMENT AND METHODS THEREOF - An arrangement in a network tap for monitoring state of a monitoring system is provided. The arrangement includes a set of network ports that includes a set of input network ports for receiving data traffic and a set of output network ports for outputting the data traffic from the network tap. The arrangement also includes a monitoring port that is configured to receive the data traffic from the set of network ports and to forward the data traffic onward to the monitoring system. The arrangement further includes a logic component configured for executing a sequential heartbeat diagnostic test. The sequential heartbeat diagnostic test is configured for providing a first set of sequential heartbeat packets for testing and determining the state of the monitoring system. The arrangement yet also includes a logic component for activating one or more events when a failure condition exists for the state of the monitoring system. | 2011-09-01 |
20110211442 | VIRTUAL ROUTER WITH A PRIORITY VALUE PER PORT - A virtual router spans a number of physical routing devices. A set of physical ports on one of the physical routing devices is logically represented as a trunk. A respective port priority value is associated with each of those ports, and a device priority value is associated with the physical routing device. If a port in the trunk is out-of-service, then the device priority value can be adjusted by the port priority value associated with the out-of-service port. A corrective action can be implemented if the device priority value fails to satisfy a condition. For example, the physical routing device may failover to another one of the physical routing devices spanned by the virtual router. | 2011-09-01 |
20110211443 | NETWORK SWITCH WITH BY-PASS TAP - A network switch apparatus includes a first network port, a second network port, a first inline port, a second inline port, wherein the first and second inline ports are for communication with a pass-through device, a packet switch, and a by-pass device configured to operate in a first mode of operation, wherein in the first mode of operation, the by-pass device is configured to pass a first packet received at the first network port to the packet switch. The by-pass device is configured to switch from the first mode of operation to a second mode of operation upon an occurrence of a condition, and wherein in the second mode of operation, the by-pass device is configured to transmit a second packet received at the first network port to the second network port without passing the second packet to the packet switch. | 2011-09-01 |
20110211444 | Seamless Overlay Connectivity Using Multi-Homed Overlay Neighborhoods - A communication system enables a node to utilize multiple communication interfaces to connect to an overlay network. The use of multiple communication interfaces provides a redundant overlay network connection, thereby enabling a node to maintain connectivity or select a preferred connection to the overlay network, increasing efficiency or reducing costs in the overlay network. A network in which member nodes obtain services in the absence of server-based infrastructure is referred to as a “peer-to-peer overlay network” (or “overlay network” or simply “overlay”). Overlay networks consist of several nodes from hundreds, to thousands, joined together in a logical routing structure. Individual nodes often participate in routing and maintenance aspects of the overlay. Typically an overlay is formed through the enrollment and joining of all these nodes as defined by the overlay protocol. Nodes forming peer-to-peer overlay networks may communicate with each other over various network technologies. | 2011-09-01 |
20110211445 | System and Method for Computing a Backup Ingress of a Point-to-Multipoint Label Switched Path - Disclosed is an apparatus that includes a path computation element (PCE) configured to communicate with a path computation client (PCC) and compute a backup ingress node for a Point-to-Multipoint (P2MP) Label Switched Path (LSP) in a network associated with the PCC. The backup ingress node is coupled to an ingress node of the P2MP LSP and to a plurality of next-hop nodes of the ingress node of the P2MP LSP via a backup tree. | 2011-09-01 |
20110211446 | GIGABITS ZERO-DELAY TAP AND METHODS THEREOF - A gigabits zero-delay arrangement for enabling continuous monitoring of data traversing through a network in a high-speed Ethernet environment is provided. The arrangement includes a high-speed network device configured for monitoring the data flowing through the network. The arrangement also includes a primary power source for providing a first power to circuitry of the gigabits zero-delay arrangement. The arrangement further includes a sensor controller configured for monitoring power flowing into the high-speed network device and for establishing an alternative communication link. | 2011-09-01 |
20110211447 | METHOD AND APPARATUS FOR PERFORMING HYBRID PER STATION AND PER FLOW UPLINK ALLOCATIONS - Method and apparatus for performing hybrid per station and per flow/connection uplink allocations are described. The apparatus may implement a hybrid per flow/connection and per station uplink (UL) resource allocation to improve UL control efficiency and UL resource utilization. The apparatus may be configured to transmit or receive a resource allocation in a signal that contains an indicator that indicates intended flow information. | 2011-09-01 |
20110211448 | PER-CLASS SCHEDULING WITH RATE LIMITING - Providing network access is disclosed. Use of a provider equipment port via which network access is provided to two or more downstream nodes, each having one or more classes of network traffic associated with it, is scheduled on a per class basis, across the downstream nodes. The respective network traffic sent to each of at least a subset of the two or more downstream nodes is limited, on a per downstream node basis, to a corresponding rate determined at least in part by a capacity of a communication path associated with the downstream node. | 2011-09-01 |
20110211449 | COMMUNICATION TRANSPORT OPTIMIZED FOR DATA CENTER ENVIRONMENT - Methods and apparatus for congestion control in computer networks achieve high burst tolerance, low latency and high throughput with shallow-buffered switches. A method for controlling congestion includes transmitting a set of data packets on a network connection from a first computing device to a second computing device, identifying each data packet in the set of data packets that experienced congestion on the network connection, sending, by the second computing device to the first computing device, a sequence of bits that represents the number of data packets in the set of data packets that were identified as having experienced congestion, and adjusting a rate of transmitting data packets on the network connection based on the sequence of bits sent to the first computing device. | 2011-09-01 |
20110211450 | SYSTEM AND METHOD FOR AUTOMATICALLY ADAPTING AUDIO PACKET MARKING IN A PACKET NETWORK - Disclosed herein are systems, methods, and computer-readable storage media for managing a packet network to deal with a problem of dropped audio packets. A triggering event signal indicates that audio marked packet traffic in the packet network has exceeded a capacity limit. Upon receiving the triggering event signal, a transmitting device transmits audio packets marked as non-audio packets through the packet network. The transmitting device, for example, is a VoIP telephone. The triggering event signal, for example, is generated when the audio marked packet traffic exceeds a dropped packet threshold, or when monitoring of audio marked packet traffic indicates that audio marked packet traffic approaches a committed data rate (CDR) threshold. | 2011-09-01 |
20110211451 | SYSTEM AND METHOD FOR IMPROVED DATA TRANSMISSION RELIABILITY OVER A NETWORK - In one example embodiment, a method is provided and includes identifying a first data type of a first payload of a first data packet to be transmitted as part of a flow, where the first data type is identified by evaluating a quality of service (QoS) field, and setting an acknowledgement flag based on the first data type; the acknowledgement flag to indicate that an acknowledgement is not required from a receiving device such that a network device avoids retransmitting a first outgoing frame when the acknowledgement is not received for the first outgoing frame. In more particular instances, the method can include where the acknowledgement flag is in the first outgoing frame. | 2011-09-01 |
20110211452 | RADIO BASE STATION AND RADIO COMMUNICATION METHOD - A radio base station, comprising a DAP/RLSE/FLSE judging unit configured to judge whether the radio base station functions as both RLSE and FLSE, an application judging unit configured to judge whether the application running on the radio terminal is a specific application, and a handover instruction transmission unit configured to transmit a handover instruction to the radio terminal to handover either the RLSE or FLSE to another radio base station, when it is determined that the radio base station functions both as RLSE and FLSE and the running application is not the specific application. | 2011-09-01 |
20110211453 | Method, Apparatus, and Computer Program Product for Wireless Signal Storage With Signal Recognition Detection Triggering - Various methods for wireless signal storage with signal recognition detection triggering are provided. One method may include receiving a plurality of wireless signals via a plurality of frequency channels, storing representations of the plurality of wireless signals in a signal buffer, and receiving a trigger request for a signal of interest. In this regard, the trigger request may have been generated based on an analysis of at least one wireless signal within the plurality of wireless signals to thereby identify the signal of interest. The method may also include retrieving a representation of the signal of interest from the signal buffer based on the trigger request, and analyzing the retrieved representation of the signal of interest with associated signal characteristics to determine a location of a source of the signal of interest. Similar apparatuses and computer program products are also provided. | 2011-09-01 |
20110211454 | COMMUNICATION DEVICE, AND COMPUTER-READABLE STORAGE DEVICE AND METHOD FOR THE SAME - A communication device is provided that includes a communication unit configured to perform communication of a voice signal with a party device via a communication line, a wireless communication unit configured to perform wireless communication of a data signal with an external device, and a controller configured to perform first wireless communication and second wireless communication in parallel, using the wireless communication unit. The first wireless communication is adapted to enable wireless communication of the voice signal between a voice communication device and the communication unit via the wireless communication unit. The second wireless communication is adapted to enable wireless communication of the data signal between the external device and the wireless communication unit. | 2011-09-01 |
20110211455 | REPORT METHOD AND ACCESS CONTROL DEVICE AND RADIO DEVICE USING THE METHOD - A frame specifying unit frames in such a manner that a frame containing at least a plurality of slots is repeated and in such a manner that a part of the plurality of slots contained in each frame are reserved for use on an access control apparatus. An empty slot identifying unit detects a slot, which is usable for the communications between radio apparatuses, from among the remaining part of the plurality of slots. A selection unit selects a slot from among the part of the plurality of slots in order to broadcast information on the detected slot. A modulation unit and an RF unit broadcast information on the slot detected by the empty slot identifying unit, using the selected slot. | 2011-09-01 |
20110211456 | High Performance Three-Port Switch For Managed Ethernet Systems - A method and apparatus for isolating and analyzing segments of a deployed, operational cable plant from a remote location. Individual cables, or segments, within an operationally deployed cable plant infrastructure may be isolated and analyzed without requiring a technician to physically inspect and perform an on-site analysis. The approach allows a cable segment to be isolated and analyzed without physically disconnecting the cable from the deployed infrastructure. By isolating and analyzing selected cable plant segments, an entire deployed cable plant infrastructure may be discretely analyzed and specific problems within the cable plant infrastructure may be identified. The approach allows the analyses to be performed from a remote location and is compatible with and may be integrated within a multipurpose network management system. | 2011-09-01 |
20110211457 | Method and Arrangement in a Communication System For Exchanging a Status Report - Methods and arrangements in a first node for requesting a status report from a second node. The first node and the second node are both comprised within a wireless communication system. The status report comprises positive and/or negative acknowledgement of data sent from the first node, to be received by the second node. The methods comprises the steps of: detecting if any data units have been lost during the transmission, generating a status report, based on the made detection concerning lost data units, buffering the generated status report in a buffer, updating the buffered status report when a change concerning lost data units is detected, receiving a trigger for sending a status report to the second node, and transmitting the status report to the second node, as a response to the received trigger. | 2011-09-01 |
20110211458 | MOBILE STATION, RADIO BASE STATION, AND MOBILE COMMUNICATION METHOD - In a mobile station (UE) according to the present invention, a radio link failure state determination unit determines whether or not the mobile station (UE) is in a radio link failure state, based on a downlink synchronization state and a discontinuous reception state parameter, when the mobile station (UE) is in a discontinuous reception state. The radio link failure state determination unit determines whether or not the mobile station (UE) is in the radio link failure state, based on the downlink synchronization state and a non-discontinuous reception state parameter, when the mobile station (UE) is not in the discontinuous reception state. | 2011-09-01 |
20110211459 | SYSTEM AND METHOD FOR ANALYZING AND TESTING PACKET FLOWS TO LOCALIZE PROBLEMS - Disclosed herein are systems, methods, and computer-readable storage media for analyzing packet flows and generating an alarm and for active testing of a network to localize problems. The system analyzes packet flows for bitstreams associated with a network node in order to compute a measure of protection that a queue of the network node gives to a high-priority one of the bitstreams relative to a low-priority one of the bitstreams, and uses the measure of protection to determine whether the network node is a source of a protection error with respect to priority markings for packets flowing through the network node, and generates an alarm upon determining that the network node is a source of a protection error with respect to the priority markings for the packets flowing through the network node. | 2011-09-01 |
20110211460 | Systems and Methods for Determining Packet Error Rate (PER) for Wireless Encapsulated Network Packet Data Communications Links - A method for generating a packet sequence for determining a Packet Error Rate (PER) using network packets, the method comprising generating, using a Local Area Network (LAN) enabled computer, a series of network PER test packets and frames, each packet comprising a predetermined unique identifier and each frame comprising a predetermined sequence for the packets in the series of network packets, wherein the series of network packets and frames are each of a size that is compliant with a predetermined framing mode and encapsulation protocol for the transmission system for determining a PER from the series of network packets and frames, and transmitting, using a transmitting device, the network packets and frames to a receiving device. | 2011-09-01 |
20110211461 | Method for Data Transmission in a Local Area Network - A method for data transmission in a local are network, wherein data is transmitted on the Media Access Control (MAC) layer within successive time frames between a plurality of first nodes comprising client nodes to a second node comprising a coordinator node for the plurality of first nodes. A synchronizing slot for sending a synchronizing message from the second node to the first nodes includes acknowledgements for time slots used for data transmissions in previous time frames from the first nodes to the second node. The acknowledgements indicate whether a data transmission in the previous time frame was successful. Based on these acknowledgements, retransmission time slots included in the current time frame are used for retransmitting data that have not been transmitted successfully in a time slot of the previous time frame. | 2011-09-01 |
20110211462 | METHODS AND SYSTEMS FOR SCHEDULING IN A VIRTUAL MIMO COMMUNICATION ENVIRONMENT - A system and method for scheduling cooperative uplink transmissions a virtual multiple input multiple output (MIMO) wireless communication environment are provided. More specifically, both random and channel aware orthogonal scheduling techniques for identifying a sub-set of N mobile terminals to provide cooperative uplink transmissions for each transmit time interval are provided. | 2011-09-01 |