33rd week of 2012 patent applcation highlights part 41 |
Patent application number | Title | Published |
20120208305 | FABRICATING METHOD OF A PIXEL UNIT - A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer. | 2012-08-16 |
20120208306 | METHOD FOR ENCAPSULATING AN ORGANIC LIGHT EMITTING DIODE - Methods for encapsulating OLED structures disposed on a substrate using a soft/polymer mask technique are provided. The soft/polymer mask technique can efficiently provide a simple and low cost OLED encapsulation method, as compared to convention hard mask patterning techniques. The soft/polymer mask technique can utilize a single polymer mask to complete the entire encapsulation process with low cost and without alignment issues present when using conventional metal masks. Rather than utilizing a soft/polymer mask, the encapsulation layers may be blanked deposited and then laser ablated such that no masks are utilized during the encapsulation process. | 2012-08-16 |
20120208307 | MANUFACTURING METHOD OF HIGH-EFFICIENCY LED - A manufacturing method of a high-efficiency light-emitting diode (LED) is provided. A soft mold is used to transfer a microstructure or a nano-scale pattern thereon onto an imprinting material. The imprinting material is distributed all over an LED wafer; and the imprinting process may be performed through forward imprinting or reverse imprinting. | 2012-08-16 |
20120208308 | METHOD MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device having a stacked body of nitride semiconductor including a light emitting layer. The method can include selectively etching a substrate in an atmosphere containing chlorine and nitrogen, using a carbon-containing mask formed on a surface of the substrate translucent to light emission emitted from the light emitting layer. The method can include forming a nitride semiconductor layer on the etched surface of the substrate, the nitride semiconductor having a higher refractive index than the substrate. In addition, the method can include forming the stacked body including the nitride semiconductor layer on the substrate. | 2012-08-16 |
20120208309 | GLASS PLATE FOR SUBSTRATE, METHOD FOR PRODUCING SAME, AND METHOD FOR PRODUCING TFT PANEL - The present invention relates to a glass plate for a substrate contains, as a glass matrix composition, in mol % on the oxide basis, SiO | 2012-08-16 |
20120208310 | NON-HALOGENATED ETCHANT AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE NON-HALOGENATED ETCHANT - Exemplary embodiments of the present invention disclose a non-halogenated etchant for etching an indium oxide layer and a method of manufacturing a display substrate using the non-halogenated etchant, the non-halogenated etchant including nitric acid, sulfuric acid, a corrosion inhibitor including ammonium, a cyclic amine-based compound, and water. | 2012-08-16 |
20120208311 | ORGANIC LIGHT EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - A top emission organic light emitting display and a method of manufacturing the same. The organic light emitting display includes a substrate, a plurality of thin film transistors (TFT) on the substrate, a plurality of first electrodes coupled to the plurality of TFTs, auxiliary electrodes having a mesh structure defining areas where the plurality of first electrodes are located, a pixel defining layer on a substantially entire area of the substrate and patterned to expose the first electrodes and the auxiliary electrodes, an organic light emission layer on the substantially entire area of the substrate including the exposed first electrodes and auxiliary electrodes, and second electrodes on the organic light emission layer. Steps are formed at lower parts of the auxiliary electrodes, and the second electrodes are coupled to the auxiliary electrodes through contact regions in which the auxiliary electrodes are exposed due to the steps. | 2012-08-16 |
20120208312 | METHOD OF MANUFACTURING ORGANIC PHOTOVOLTAIC DEVICE - A method of manufacturing an organic photovoltaic device of a pre-defined shape and size is provided. The method includes providing a first substrate with said pre-defined shape and size, the size being less than 900 square centimeters and depositing an organic photoactive layer on said first substrate followed by depositing an electrically conducting layer on said organic photoactive layer. Thereafter, said electrically conducting layer and said organic photoactive layer are scribed from said first substrate forming zones on first substrates, whereby forming an active substrate. Further, providing a second substrate with said pre-defined shape and size and depositing a gas-absorbent layer on said second substrate whereby forming an inactive substrate. Finally, encapsulating said active substrate with said inactive substrate to form said organic photovoltaic device with said pre-defined shape and size, whereby not involving cutting of said first substrate after deposition of said organic photoactive layer. | 2012-08-16 |
20120208313 | METHODS OF FORMING AGGREGATE PARTICLES OF NANOMATERIALS - Methods for forming aggregates of nanomaterials are provided. The aggregates are formed from a liquid dispersion of the nanomaterials in a liquid. The dispersion is aerosolized and the liquid removed from the aerosolized dispersion to provide the aggregates. The aggregates are useful as a photoelectric layer and/or a light-dispersive layer in dye-sensitized solar cells. | 2012-08-16 |
20120208314 | System, method and apparatus for thin film manufacturing - A method for forming multiple layers in a single process chamber includes placing a substrate in the process chamber having multiple processing sources and iteratively forming a copper indium gallium selenium (CIGS) including forming multiple relatively thin CIGS layers including forming a copper indium gallium (CIG) layer on the substrate, the CIG layer having a thickness of between less than about 50 angstroms and about 200 angstroms, forming a selenium layer on the CIG layer, the selenium layer having a thickness of between less than about 50 angstroms and about 200 angstroms and heating the substrate, the CIG layer and the selenium layer. A processing chamber system is also disclosed. | 2012-08-16 |
20120208315 | THREE-DIMENSIONAL BICONTINUOUS HETEROSTRUCTURES, METHOD OF MAKING, AND THEIR APPLICATION IN QUANTUM DOT-POLYMER NANOCOMPOSITE PHOTODETECTORS AND PHOTOVOLTAICS - Provided herein are embodiments of a three-dimensional bicontinuous heterostructure, a method of producing same, and the application of this structure. The three-dimensional bicontinuous heterostructure includes two interpenetrating layers which are spatially continuous, include only protrusions or peninsulas, and have no islands. The method of producing the three-dimensional bicontinuous heterostructure includes forming an essentially planar continuous bottom layer of a first material; forming a layer of this first material on top of the bottom layer that is textured to produce protrusions for subsequent interpenetration with a second material, coating this second material onto this structure, and forming a coating with the second material that ensures that only the second material is contacted by subsequent layer. One of the materials includes visible and/or infrared-absorbing semiconducting quantum dot nanoparticles, and one of materials is a hole conductor and the other is an electron conductor. | 2012-08-16 |
20120208316 | Method For Forming A Photo-Active Layer Of The Solar Cell - The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation. | 2012-08-16 |
20120208317 | Intermetal Stack for Use in a Photovoltaic Cell - A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack. | 2012-08-16 |
20120208318 | SEMICONDUCTOR DEVICE HAVING A METAL OXIDE CHANNEL - A semiconductor device includes a metal oxide channel and methods for forming the same. The metal oxide channel includes indium, gallium, and zinc. | 2012-08-16 |
20120208319 | Packaged Semiconductor Device with Encapsulant Embedding Semiconductor Chip that Includes Contact Pads - A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, where x is a pitch of the second contact pads in micrometers. | 2012-08-16 |
20120208320 | On-Chip RF Shields with Front Side Redistribution Lines - A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines. | 2012-08-16 |
20120208321 | PASSIVATION LAYER FOR SEMICONDUCTOR DEVICE PACKAGING - Methods of protecting a surface of a copper layer or a copper bonding pad on a semiconductor device against oxidation. A surface of the layer or bonding pad is cleaned by removing an oxidation layer with a plasma. A polymer layer is formed on the cleaned surface of the layer using a plasma-enhanced deposition process to protect the cleaned surface of the layer against exposure to an oxidizing gas. | 2012-08-16 |
20120208322 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A multilayer wiring substrate has an upper surface with multiple bonding leads and a lower surface with multiple lands. Multiple wiring layers and insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper and lower surface sides of the core material. The third insulating layers are formed on the upper and lower surface sides of the core material with the second insulating layers in-between. The uppermost and lowermost wiring layers are formed over the third insulating layers. | 2012-08-16 |
20120208323 | Method for Mounting a Semiconductor Chip on a Carrier - A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm | 2012-08-16 |
20120208324 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a multichip thin package requiring a thickness of submillimeter region, it is difficult to thin the package if the chips are mounted over a usual die pad. According to a technique of the present application, in a manufacturing method of a semiconductor device of a thin resin sealed multichip rectangular package having wire connection between the chips, at least one chip is fixed to a die pad thinned more than a die pad support lead, the die pad is supported by die pad support leads arranged to respectively connect a pair of long sides of the rectangle, and sealing resin is introduced from one side of the pair of long sides when resin molding is performed. | 2012-08-16 |
20120208325 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a base substrate. A heat pressure process is performed to form a wiring support member on the base substrate to cover the top surface and the side surfaces of the semiconductor chip while exposing each of the bumps. Wirings are formed to be electrically connected to the bumps on the wiring support member. The base substrate is removed from the semiconductor chip and the wiring support member. | 2012-08-16 |
20120208326 | Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. | 2012-08-16 |
20120208327 | IMPRINT APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - According to one embodiment, an imprint apparatus includes an ejection unit, an ejection command generating unit, a determining unit, a prohibition command generating unit, and an ejection control unit. The ejection unit ejects a resin material. The ejection command generating unit generates an ejection command based on a drop recipe. The determining unit determines the presence or absence of a processing target substrate in an ejection destination of the resin material. The prohibition command generating unit, when the processing target substrate is not present in an ejection destination, generates an ejection prohibition command. The ejection control unit gives priority to the ejection prohibition command over the ejection command. | 2012-08-16 |
20120208328 | BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES - A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region. | 2012-08-16 |
20120208329 | INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE - Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body. | 2012-08-16 |
20120208330 | THIN FILM TRANSISTOR ARRAY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a thin film transistor array substrate includes: forming a gate pattern on a substrate; forming a first gate insulating film and a second gate insulating film on the substrate; forming a source/drain pattern and a semiconductor pattern on the substrate; forming a passivation film on the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film including over-etching the passivation film to form an open region in the passivation film; forming a transparent electrode film on the substrate; removing the photo-resist pattern and a portion of the transparent electrode film on the photo-resist pattern; and forming a pixel electrode on the first gate insulating layer. | 2012-08-16 |
20120208331 | COMPOUND SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A vertical type GaN series field effect transistor having excellent pinch-off characteristics is provided. A compound semiconductor device includes a conductive semiconductor substrate, a drain electrode formed on a bottom surface of the conductive semiconductor substrate, a current blocking layer formed on a top surface of the conductive semiconductor substrate, made of high resistance compound semiconductor or insulator, and having openings, an active layer of compound semiconductor burying the openings and extending on an upper surface of the current blocking layer, a gate electrode formed above the openings and above the active layer, and a source electrode formed laterally spaced from the gate electrode and formed above the active layer. | 2012-08-16 |
20120208332 | SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE - Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged. | 2012-08-16 |
20120208333 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming an impurity junction area within an area of the semiconductor substrate; forming a contact hole which partially exposes a surface the impurity junction area; and performing an additional ion implant process to implant impurity ions into the impurity junction area exposed through the contact hole, thereby increasing an impurity concentration of a surface portion of the impurity junction area. | 2012-08-16 |
20120208334 | METHODS OF FABRICATING A DUAL POLYSILICON GATE AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME - Methods of forming a dual polysilicon gate are provided. The method includes forming a polysilicon layer doped with impurities of a first conductivity type on a substrate having a first region and a second region, forming a mask pattern that covers the polysilicon layer in the first region and leaves the polysilicon layer in the second region, injecting impurities of a second conductivity type into the polysilicon layer in the second region left exposed by the mask pattern. Removing the mask pattern, and patterning the polysilicon layer to form a first polysilicon pattern in the first region and a second polysilicon pattern in the second region. The second polysilicon pattern is formed to have protrusions that laterally protrude from sidewalls thereof. Subsequently, impurities of the second conductivity type are injected into the substrate in the second region and into the protrusions of the second polysilicon pattern. | 2012-08-16 |
20120208335 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING LOW CONTACT RESISTANCE - Methods of fabricating a semiconductor device are provided. The method includes forming a first gate stack and a second gate stack on a first region and a second region of a substrate, respectively. The method may further comprise forming first impurity regions self-aligned with the first gate stack and second impurity regions self-aligned with the second gate stack in the substrate of the first region and in the substrate of the second region, respectively. First impurity ions may be injected into the first and second impurity regions, forming a mask pattern covering the first region and exposing the second region on the substrate where the first impurity ions are injected and second impurity ions having an opposite conductivity type to the first impurity ions may be injected into the second impurity regions exposed by the mask pattern using a plasma doping process. The mask pattern may then be removed. | 2012-08-16 |
20120208336 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 2012-08-16 |
20120208337 | SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions. | 2012-08-16 |
20120208338 | SELF ALIGNED IMPACT-IONIZATION MOS (I-MOS) DEVICE AND METHODS OF MANUFACTURE - A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel. | 2012-08-16 |
20120208339 | PASSIVATING GLUE LAYER TO IMPROVE AMORPHOUS CARBON TO METAL ADHESION - A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer. | 2012-08-16 |
20120208340 | METHODS OF FABRICATING A STORAGE NODE IN A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING A CAPACITOR USING THE SAME - A storage node is formed in a semiconductor device by forming an interlayer insulation layer on a substrate, forming an etch stop layer and a first sacrificial layer on the interlayer insulation layer, patterning the first sacrificial layer and the etch stop layer to form a first sacrificial layer pattern and an etch stop layer pattern that define a storage node contact hole, forming a recessed first storage node conductive pattern that conformally covers a lower sidewall and a bottom surface of the storage node contact hole, forming a second storage node conductive pattern that includes a first portion surrounded by the recessed first storage node conductive pattern and a second portion conformally covering an upper sidewall of the storage node contact hole, and removing the first sacrificial layer pattern. The recessed first storage node conductive pattern and the second storage node conductive pattern constitute a storage node. | 2012-08-16 |
20120208341 | Alignment Marks for Polarized Light Lithography and Method for Use Thereof - Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process. | 2012-08-16 |
20120208342 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching. | 2012-08-16 |
20120208343 | METHOD FOR MANUFACTURING A MICRO-ELECTRO-MECHANICAL DEVICE, IN PARTICULAR AN OPTICAL MICROSWITCH, AND MICRO-ELECTRO-MECHANICAL DEVICE THUS OBTAINED - A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein. | 2012-08-16 |
20120208344 | CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION COMPRISING INORGANIC PARTICLES AND POLYMER PARTICLES - A chemical mechanical polishing (CMP) composition, comprising (A) at least one type of inorganic particles which are dispersed in the liquid medium (C), (B) at least one type of polymer particles which are dispersed in the liquid medium (C), (C) a liquid medium, wherein the zeta-potential of the inorganic particles (A) in the liquid medium (C) and the zeta-potential of the polymer particles in the liquid medium (C) are of same signs. | 2012-08-16 |
20120208345 | METHOD FOR FORMING A SELF-ALIGNED ISOLATION STRUCTURE UTILIZING SIDEWALL SPACERS AS AN ETCH MASK AND REMAINING AS A PORTION OF THE ISOLATION STRUCTURE - The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow. | 2012-08-16 |
20120208346 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO | 2012-08-16 |
20120208347 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Methods of fabricating a three-dimensional semiconductor device are provided. Methods may include forming a stack structure including first layers and second layers alternately stacked on a substrate, patterning the stack structure to form at least one isolation trench, forming channel structures penetrating the stack structure and being spaced apart from the isolation trench, and forming upper interconnection lines on the stack structure to connect the channel structures to each other. An isolation trench may be formed prior to formation of the channel structures. | 2012-08-16 |
20120208348 | METHOD OF MANUFACTURING SOI SUBSTRATE - The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step. | 2012-08-16 |
20120208349 | Support for Wafer Singulation - A support substrate or chuck | 2012-08-16 |
20120208350 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention aims to provide a method of manufacturing a semiconductor device that is capable of preventing cracks in a low dielectric material layer of a semiconductor wafer, while also suppressing an increase in the number of steps in the manufacturing process. This object is achieved by a method of manufacturing a semiconductor device including the steps of pasting a film for forming a protective layer in which a support base, an adhesive layer, and a thermosetting resin layer are laminated, in that order, onto a bumped wafer in which a low dielectric material layer is formed, with the thermosetting resin layer serving as a pasting surface, and further, peeling the support base and the adhesive layer from the thermosetting resin layer, forming a protective layer by thermally curing the thermosetting resin layer, and dicing the bumped wafer and the protective layer together. | 2012-08-16 |
20120208351 | CLEANING APPARATUS FOR SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A cleaning apparatus for a semiconductor manufacturing apparatus includes: a oxide removal unit that removes an oxide over a surface of a deposit adhered to components of the semiconductor manufacturing apparatus, and a deposit removal unit that removes the deposit after the oxide over the surface is removed by the oxide removal unit. | 2012-08-16 |
20120208352 | METHODS AND SYSTEMS FOR FORMING THIN FILMS - A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films. | 2012-08-16 |
20120208353 | Method for Manufacturing a Semiconductor Component - A semiconductor component having a low resistance conduction path and a method for manufacturing the semiconductor component. When the semiconductor component is a Schottky diode, one or more trenches are formed in an epitaxial layer of a first conductivity type that is formed over a semiconductor substrate of the first conductivity type. The trenches may extend into the semiconductor material. Epitaxial semiconductor material of a second conductivity type is selectively grown along the sidewalls of the trenches. An anode contact is formed in contact with the epitaxial layer and the selectively grown epitaxial material and a cathode contact is formed in contact with the semiconductor substrate. | 2012-08-16 |
20120208354 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - In a MOS-type semiconductor device in which, on a Si substrate, a SiGe layer having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si cap layer, and an insulating layer are sequentially laminated, the problem of the shift of the absolute value of the threshold voltage toward a smaller value caused by negative fixed charges formed in or near the interface between the Si cap layer and the insulting film by diffusion of Ge is overcome by neutralizing the negative fixed charges by positive charges induced in and near the interface between the Si cap layer and the insulating film along with addition of nitrogen atoms to the semiconductor device surface by NO gas annealing and thereby shifting the threshold voltage toward a larger value. | 2012-08-16 |
20120208355 | GALLIUM NITRIDE SUBSTRATE - A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m | 2012-08-16 |
20120208356 | Device component forming method with a trim step prior to sidewall image transfer (SIT) processing - Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed. | 2012-08-16 |
20120208357 | METHODS AND SYSTEMS FOR FORMING THIN FILMS - A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films. | 2012-08-16 |
20120208358 | METHOD FOR PRODUCING A MULTILAYER FILM INCLUDING AT LEAST ONE ULTRATHIN LAYER OF CRYSTALLINE SILICON, AND DEVICES OBTAINED BY MEANS OF SAID METHOD - Method of fabricating a multilayer film having at least one ultrathin layer of crystalline silicon, the film being fabricated from a substrate having a crystalline structure and including a previously-cleaned surface. The method includes the steps of: a) exposing the cleaned surface to a radiofrequency plasma generated in a gaseous mixture of SiF4, hydrogen, and argon, so as to form an ultrathin layer of crystalline silicon having an interface sublayer in contact with the substrate and containing microcavities; b) depositing at least one layer of material on the ultrathin layer of crystalline silicon so as form a multilayer film, the multilayer film including at least one mechanically strong layer; and c) annealing the substrate covered in the multilayer film at a temperature higher than 400° C., thereby enabling the multilayer film to be separated from the substrate. | 2012-08-16 |
20120208359 | Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates - A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate. | 2012-08-16 |
20120208360 | METHOD FOR FORMING SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A microcrystalline semiconductor film is formed over a substrate using a plasma CVD apparatus which includes a reaction chamber in such a manner that a deposition gas and hydrogen are supplied to the reaction chamber in which the substrate is set between a first electrode and a second electrode; and plasma is generated in the reaction chamber by supplying high-frequency power to the first electrode. Note that the plasma density in a region overlapping with an end portion of the substrate in a region where the plasma is generated is set to be higher than that in a region which is positioned more on the inside than the region overlapping with the end portion of the substrate, so that the microcrystalline semiconductor film is formed over a region which is positioned more on the inside than the end portion of the substrate. | 2012-08-16 |
20120208361 | METHOD FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate. | 2012-08-16 |
20120208362 | STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES - A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening. | 2012-08-16 |
20120208363 | METHODS OF DEPOSITING ALUMINIUM LAYERS - A method of depositing an aluminium film on a substrate includes placing the substrate on a support, depositing a first layer of aluminium onto the substrate with the substrate in an unclamped condition, clamping the substrate to the support and depositing a second layer of aluminium continuous with the first layer. The second layer is thicker than the first layer and the second layer is deposited at a substrate temperature of less than about 22° C. | 2012-08-16 |
20120208364 | METHOD FOR OPENING ONE-SIDE CONTACT REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING ONE-SIDE JUNCTION REGION USING THE SAME - A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed. | 2012-08-16 |
20120208365 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off. | 2012-08-16 |
20120208366 | PREVENTION AND REDUCTION OF SOLVENT AND SOLUTION PENETRATION INTO POROUS DIELECTRICS USING A THIN BARRIER LAYER - A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch. | 2012-08-16 |
20120208367 | METHOD FOR FABRICATING CARBON HARD MASK AND METHOD FOR FABRICATING PATTERNS OF SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using C | 2012-08-16 |
20120208368 | METHOD AND APPARATUS FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere. | 2012-08-16 |
20120208369 | Method of Etching Features in Silicon Nitride Films - A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern. The method includes preparing a film stack on a substrate, the film stack containing a SiN film on the substrate and a mask pattern on the SiN film, forming a plasma from a process gas containing HBr gas, O | 2012-08-16 |
20120208370 | METHOD FOR ETCHING OF SILICON SURFACES - The invention relates to a method for etching of silicon surfaces with the following steps: | 2012-08-16 |
20120208371 | METHOD AND APPARATUS FOR MULTIZONE PLASMA GENERATION - Embodiments of the present invention provide a method and apparatus for plasma processing a substrate to form a film on the substrate and devices disposed thereon by controlling the ratio of ions to radicals in the plasma at a given pressure. A given pressure may be maintained to promote ion production using one plasma source, and a second plasma source may be used to provide additional radicals. In one embodiment, a low pressure plasma is generated in a processing region having the substrate positioned therein, and a high pressure plasma is generated in separate region. Radicals from the high pressure plasma are injected into the processing region having the low pressure plasma, thus, altering the natural distribution of radicals to ions at a given operating pressure. The resulting process and apparatus enables tailoring of the ion to radical ratio to allow better control of forming films on high aspect ratio features, and thus improve corner rounding, conformality of sidewall to bottom trench growth, and selective growth. | 2012-08-16 |
20120208372 | PROCESS GAS DELIVERY FOR SEMICONDUCTOR PROCESS CHAMBERS - Methods for gas delivery to a process chamber are provided herein. In some embodiments, a method may include flowing a process gas through one or more gas conduits, each gas conduit having an inlet and an outlet for facilitating the flow of gas through the gas conduits and into a gas inlet funnel having a second volume, wherein each gas conduit has a first volume less than the second volume, and wherein each gas conduit has a cross-section that increases from a first cross-section proximate the inlet to a second cross-section proximate the outlet but excluding any intersection points between the gas inlet funnel and the gas conduit, and wherein the second cross-section is non-circular; and delivering the process gas to the substrate via the gas inlet funnel. | 2012-08-16 |
20120208373 | METHOD FOR DEPOSITING AN AMORPHOUS CARBON FILM WITH IMPROVED DENSITY AND STEP COVERAGE - A method for depositing an amorphous carbon layer on a substrate includes the steps of positioning a substrate in a chamber, introducing a hydrocarbon source into the processing chamber, introducing a heavy noble gas into the processing chamber, and generating a plasma in the processing chamber. The heavy noble gas is selected from the group consisting of argon, krypton, xenon, and combinations thereof and the molar flow rate of the noble gas is greater than the molar flow rate of the hydrocarbon source. A post-deposition termination step may be included, wherein the flow of the hydrocarbon source and the noble gas is stopped and a plasma is maintained in the chamber for a period of time to remove particles therefrom. | 2012-08-16 |
20120208374 | AMORPHOUS CARBON DEPOSITION METHOD FOR IMPROVED STACK DEFECTIVITY - Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less, and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater. | 2012-08-16 |
20120208375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H | 2012-08-16 |
20120208376 | METHOD OF FORMING SILICON NITRIDE FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method of forming a silicon nitride film by using a plasma CVD method, where the silicon nitride film has abundant traps and is useful as a charge accumulation layer of a nonvolatile semiconductor memory device. A silicon nitride film having a lot of traps is formed by performing plasma CVD by using processing gases including a nitrogen gas and a gas of a compound formed of silicon atoms and chlorine atoms, and by setting a pressure in a processing container within a range between more than or equal to 0.1 Pa and less than or equal to 8 Pa, in a plasma CVD apparatus that performs film-formation by introducing microwaves in the processing container by using a planar antenna having a plurality of holes to generate plasma. | 2012-08-16 |
20120208377 | RAPID THERMAL PROCESSING USING ENERGY TRANSFER LAYERS - A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source in the process chamber in a way which subjects the wafer to a thermal profile such that the energy transfer layer influences at least one part of the thermal profile. The thermal profile has at least a first elevated temperature event. The method further includes, in time relation to the thermal profile, removing the energy transfer layer in the process chamber at least sufficiently for subjecting the wafer to a subsequent step. An associated intermediate condition of the wafer is described. | 2012-08-16 |
20120208378 | FLEXIBLE MAGNETIC INTERCONNECTS - A flexible magnetic interconnect is disclosed. In one embodiment, an apparatus includes a module having a recess therein. A magnetic structure is moveable within the recess and a flexible circuit cooperates with the module to retain the magnetic structure within the recess. Movement of the magnetic structure is caused by magnetic attraction between the magnetic structure and an external magnetic structure. The flexible circuit includes a compliant contact, which changes shape by movement of the magnetic structure. | 2012-08-16 |
20120208379 | AC INLET - An AC inlet is electrically connected to a circuit board of an electronic device and includes an insulating body, two electrical conductive pins and two electrical conductive elastic pieces. The insulating body has an insertion trough through which the electrical conductive pins are disposed. The electrical conductive elastic pieces are electrically connected to the two electrical conductive pins and the circuit board. Each electrical conductive elastic piece comprises a connecting portion electrically connected to the electrical conductive pin, a bending portion extending from the connecting portion, and a fixing portion extending from the bending portion to be electrically connected to the circuit board. The elastic deformation of the bending portion protects the electrical connection between the electrical conductive pins and the circuit board. The present invention prevents against solder cracks caused by shaking forces during its removal and plugging. Further, the time and cost for assembly are reduced. | 2012-08-16 |
20120208380 | CONTACT RELIABILITY IN SEPARABLE ELECTRICAL INTERFACES - A separable electrical interface is provided, the interface having a circuit card having one or more electrically conductive card edge tabs. Each of the card edge tabs has a raised, curved top surface profile. The separable electrical interface also includes one or more connector contacts. Each of the one or more connector contacts has a curved surface profile. The curved surface of each of the one or more connector contacts is positioned relative to a corresponding card edge tab to selectively engage the raised curved surface of the corresponding card edge tab at the point of final contact. | 2012-08-16 |
20120208381 | Interconnection Interface Using Twist Pins for Testing and Docking - A twist pin is used as an interconnect interface to conduct signals to and from an electronic component. The twist pin includes a bulge which establishes compressive contact force with a sidewall of a via in which the twist pin resides, and the resulting force resists movement of the end of the twist pin away from the electronic component to assure good signal conductivity. The arrangement may be used as a test socket for testing integrated circuit components or permanently docking electronic components. | 2012-08-16 |
20120208382 | Security Device - A security device for preventing or inhibiting unauthorized separation of a first part (e.g., a cable filter device) from a second part (e.g., a cable signal source) includes a connector having first and second connector parts which are freely rotatable with respect to each other, the first connector part including a male threaded end for removable connection to the first part and the second connector part including a female connector end for removable connection to the second part. A cylindrical sheath extends in covering relation to the first and second connector parts and is freely rotatable with respect thereto. In the attached condition, the first and second connector parts are accessible for attachment and removal only with a specially configured tool. | 2012-08-16 |
20120208383 | LEVER-TYPE CONNECTOR - A lever-type connector includes a connector housing, a cover attached to the connector housing, a lever rotatably mounted on the connector housing. The lever is rotated in a situation that a mating connector is fitted to the connector housing in a half-fitted condition, thereby moving the mating connector with respect to the connector housing from the half-fitting condition to a completely fitting condition. A retaining portion is provided on the lever. A lock portion provided on the cover is engaged with the retaining portion when the lever has been rotated. A lever claw portion is provided on the retaining portion. The lock portion is provided on a distal end portion of the lock arm. A lock protection portion is provided on the retaining portion so as to be positioned away from a rotation center of the lever than the lever claw portion so that the lock protection portion covers the lock portion. | 2012-08-16 |
20120208384 | PLUG DEVICE HAVING A CLOSURE UNIT - An electrical plug device has a contact module in which a complimentary plug device element can be inserted from an access site along a insertion axis. The plug device includes a closure unit having one or more cover elements which move from a rest position to an open position when the complimentary plug device element is inserted. The cover elements may have sloped guide surfaces and can be radially urged apart from each other. | 2012-08-16 |
20120208385 | ELECTRICAL CONNECTOR - An electrical connector comprising a housing provided on one of opposite end portions thereof with an opening through which a flat circuit device is inserted into the housing, a plurality of conductive contacts arranged on the housing for contacting with connecting terminals on the flat circuit device in the housing, and a shell member mounted on the housing and provided therein with a holding portion operative to hold the flat circuit device in the housing. A releasing portion extends from the shell member toward the outside thereof, and a connecting portion extends from the releasing portion in a direction perpendicular to a conductive contact arrangement and the holding portion extends from the connecting portion, so that a folded-back protrusion is constituted in a body in the shell member with the releasing, connecting and holding portions. | 2012-08-16 |
20120208386 | HIGH-VOLTAGE CONNECTOR COMPONENT FOR A HIGH-VOLTAGE CABLE, HIGH-VOLTAGE CONNECTOR, AND METHOD OF MANUFACTURING A HIGH-VOLTAGE CONNECTOR COMPONENT - A high-voltage connector component for a high-voltage cable comprises an insulator made of a polymer material which surrounds a cable end portion of the high-voltage cable, wherein the insulator is received in a housing and is made of an elastomer material, wherein the elastomer material is filled, cast or injected into the housing in order to form the insulator. The connector component is designed such that upon connection to a corresponding connector component a basically closed pressure chamber is formed between the housing, the corresponding connector component and the cable end portion, wherein the pressure chamber is basically provided for being completely occupied by the insulator. Loading the insulator with pressure results in a gap-free, high-voltage-sealed pressing of the corresponding connector component to the insulator, a gap-free, high-voltage-sealed pressing of the insulator to the housing, and a gap-free, high-voltage-sealed pressing of the insulator to the sheath surface of the cable end portion. | 2012-08-16 |
20120208387 | SUBSTRATE CONNECTING STRUCTURE - Provided is a substrate connecting structure that includes a support housing to which a main substrate is attached, and a shield housing for housing a relay substrate, the support housing being provided with a first opening for exposing a first connector provided in the main substrate, a first guide, and a pair of hinges, the shield housing being provided with a second opening for exposing a second connector provided in the relay substrate, and a second guide that works cooperatively with the first guide, the first guide and the second guide guiding the shield housing so that the shield housing can move perpendicularly to a main surface of the support housing provided with the first opening, ends of the pair of hinges being located between the shield housing and the support housing and being adapted to be rotated to separate the shield housing from the support housing. | 2012-08-16 |
20120208388 | CONNECTOR AND CONNECTING UNIT - A connector includes a connector protrusion to be inserted into a connector socket and including a locking lever provided on a first surface and a connecting terminal provided on a second surface opposing the first surface or on a front surface; and a connector frame surrounding the connector protrusion and having an opening in a surface opposing the first surface of the connector protrusion. When the connector frame is moved in a direction opposite to the direction where the connector protrusion is inserted while the connector protrusion is in the connector socket, an end of the locking lever fits into the opening and the locking lever is unlocked. | 2012-08-16 |
20120208389 | CONNECTOR - The invention provides a connector including first and second conductive parts and a biasing device. The first and second conductive parts are opposed to each other so as to hold a flexible electric conductor therebetween. The first conductive part includes a locking hole or locking recess, and the second conductive part includes a locking projection of pointed shape. The locking projection is configured to pass through the electric conductor and be received in the locking hole or locking recess when the first and second conductive parts hold the electric conductor. The biasing device includes a clamp of generally C shape to hold the first and second conductive parts holding the electric conductor. | 2012-08-16 |
20120208390 | CONNECTOR ASSEMBLY AND A CONNECTOR PART THEREOF - There is a discussed a connector assembly having a plug member, a sleeve member slidably mounted around the plug member, and a receptacle member. One end of the sleeve member is connectable and disconnectable to the receptacle member by virtue of either a first flexing movement or a second flexing movement in dependence upon the position of the sleeve member relative to the receptacle member, hi this way, different decoupling forces are required to separate the connector assembly in dependence on the relative position of the sleeve member and the plug member. | 2012-08-16 |
20120208391 | LOW PROFILE LATCHING CONNECTOR - A small, low-profile plug connector for use with electronic devices provides a latching member with a pair of hooks that engage mating holes in a guide frame, and which can be easily delatched from the guide frame or opposing connector or housing. The hooks lock the plug connector into engagement with the frame or housing, but are readily released by way of a simple ramp and lobe mechanism in the plug connector. The ramp and lobe mechanism converts horizontal movement of a pull tab-like actuator into vertical movement of a latching member such that the hooks are lifted upward and disengaged from the guide frame or housing. | 2012-08-16 |
20120208392 | ELECTRICAL CARD CONNECTOR - An electrical card connector is provided. The electrical card connector includes an insulating body and a cover. Axles of the cover come into contact with pivotal connection slots of the insulating body through flat surfaces, respectively. The axles are prevented from rotating within sliding portions of the pivotal connection slots, respectively, such that the cover cannot be opened while sliding. The axles of the cover come into contact with the pivotal connection slots of the insulating body through curved surfaces, respectively, to reinforce axial strength, increase contact area and friction of the pivotal connection slots, and prevent the axles from being stretched to the detriment of the structural strength of the axles. | 2012-08-16 |
20120208393 | Spring-Loaded Connection and Conductor Connection Unit - The invention describes a spring-loaded connection with a busbar piece and a bent clamping spring, which has a bearing limb, a spring bend adjoining the bearing limb and a clamping limb which adjoins the spring bend opposite the transition between the bearing limb and the spring bend. The clamping limb is aligned with the busbar piece so as to form a clamping point for an electrical conductor. An actuating lug extends away from the clamping limb. The actuating lug extends from the clamping limb past the bearing limb into an actuating region located behind the bearing limb, when viewed from the clamping limb in the direction of the bearing limb. The actuating lug has, in this actuating region, an abutment for an actuating element which can be arranged in the actuating region between the bearing limb and the abutment. | 2012-08-16 |
20120208394 | REUSABLE DOUBLE-CONTACT ELECTRICAL WIRE CONNECTOR FOR SINGLE-AND MULTI-THREAD WIRES - A double-blade, reusable push-in wire connector for electrically interconnecting together multiple wires has a guide and lock element, which is mated with a conduction and retention element and assembled inside an enclosing element. The guide and lock element has at least one separation wall extending along the direction of insertion of the wires. The conduction and retention element has at least one resilient spring leg and a conduction plate. A wire installation access port is opened in the guide and lock element for force-opening of the clamping between the at least one resilient spring leg and the conduction plate so as to remove an inserted wire from or to insert a multi-thread wire into the connector. | 2012-08-16 |
20120208395 | CONNECTOR APPARATUS - A connector apparatus has an equipment-side connector ( | 2012-08-16 |
20120208396 | FIXING STRUCTURE OF CONNECTOR - A fixing structure of a connector includes a housing and a rear holder fixing the housing to a casing by screws. The rear holder has a base plate opposing the casing. First through holes are formed on the base plate so as to correspond to second openings for leading out conductive parts of the female terminals respectively. Terminal holding members are respectively provided at the first through holes for contacting the female terminals respectively. The screws are inserted respectively through second through holes which are arranged so as to deviate to one side with respect to a center of gravity of a region in which the first through holes are formed. Elasticity of one of the terminal holding members which is disposed at a first position facing at least one of the second through holes in a peripheral part of the region are smaller than elasticity of another one of the terminal holding members which is disposed at a position except for the first position. | 2012-08-16 |
20120208397 | ELECTRICAL JUNCTION BOX FOR A PHOTOVOLTAIC MODULE - An electrical junction box for a photovoltaic module includes a box receptacle including a plurality of positive contacts configured to contact a positive pole of the photovoltaic module and a plurality of negative contacts configured to contact a negative pole of the photovoltaic module. A box lid includes a positive connection cable connected to at least one positive mating contact and a negative connection cable connected to at least one negative mating contact. The box lid is configured to be disposed on the box receptacle in a plurality of selectable fitting positions each based on a respective predetermined alignment of the connection cables. In each fitting position, the at least one positive mating contact and the at least one negative mating contact of the box lid are configured to respectively electrically contact the associated respective positive contact and the associated respective negative contact of the box receptacle. | 2012-08-16 |
20120208398 | CENTER CONDUCTOR TERMINAL HAVING INCREASED CONTACT RESISTANCE - A terminal assembly is provided for terminating a center conductor of a coaxial cable. The terminal assembly includes a terminal body having a pin at one end and a cavity at the other end for accommodating a center conductor therein. A contact member is supported within the cavity. The contact member includes plural inwardly directed cantilevered beams extending from a contact base for deflectable engagement with the inserted center conductor. The terminal body includes an inwardly directed shoulder for engagement with the beams at a location between the base and the distal ends of the beams. The location defines a deflection fulcrum at a location distal from the base so as to provide increased contact engagement force between the distal ends of the beams and the center conductor. | 2012-08-16 |
20120208399 | ELECTRICAL CARRIER ASSEMBLY AND SYSTEM OF ELECTRICAL CARRIER ASSEMBLIES - A male coaxial connector includes at least one termination device having a tubular shield surrounding and isolated from a pin that is configured to electrically connect with a socket of a female termination device, and a plate extending from one of a leading end of the tubular shield and a leading end of the female termination device. Upon electrical interconnection, the plate forms a ground circuit extending between the at least one termination device and a ground of the female termination device. | 2012-08-16 |
20120208400 | HEADER ASSEMBLY - A header assembly is provided that includes an outer housing that has a mating end and a harness end. The outer housing has a cavity at the mating end and a flange configured to be mounted to a panel of a device. The outer housing is configured to be exposed to an exterior of the device for mating with a plug assembly. A shield is received in the cavity that has a front and a rear. An inner housing is received in the cavity with the shield surrounding at least a portion of the inner housing. The inner housing has a front and a rear and has a latch engaging the front of the shield. The latch allows the inner housing to be released from the shield to remove the inner housing from the cavity. | 2012-08-16 |
20120208401 | PLUG CONTACT ARRANGEMENT AND THE MANUFACTURE THEREOF - A plug can include a set of primary contacts for communication signal transmission, a storage device to store physical layer information (PLI), and a set of secondary contacts for PLI signal transmission. One or more sets of secondary contacts may be manufactured from a conductive strip. The storage device associated with each set may be mounted to an insulating layer that physically connects the contacts of each set. | 2012-08-16 |
20120208402 | Terminal Module And Method For Manufacturing The Same - The invention is a terminal module and a method for manufacturing the same. The terminal module includes an insulating body and a plurality of first and second terminals. The plurality of first and second terminals are alternatively arranged side by side and partially insert-molded within the insulating body. The plurality of first terminals and the plurality of second terminals are connected to a common terminal carrier. | 2012-08-16 |
20120208403 | ELECTRIC CONNECTOR AND ENDOSCOPE - An electric connector portion includes first and second electric contact portions which are connectable to first and second target electric contact portions, respectively, and a protective member which is movable from a protecting position where the first and second electric contact portions are protected to an opening position where the first and second electric contact portions are opened in a moving direction extending from the first electric contact portion side to the second electric contact portion side, wherein the protective member includes an opening portion which is configured to open the second electric contact portion when the protective member is arranged at the opening position. | 2012-08-16 |
20120208404 | CONNECTOR ASSEMBLY - The present invention provides a connector assembly having a small size and preventing a contact between a bolt fastener and a detection member. The connector assembly includes a connector having an inner chamber with an opening and a plurality of connector terminals, a connector receptacle having a plurality of connector receptacle terminals securable together with the connector terminals and a first detection member, and a cover for covering the opening and having a second detection member. When the opening of the inner chamber is covered with the cover, the first detection member and the second detection member are connected together and detect that the cover is covered. The first detection member is disposed between the adjacent connector receptacle terminals. An end surface of the first housing is positioned inwardly of the inner chamber with respect to a surface of a connector electrical contact portion. | 2012-08-16 |