33rd week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120205704 | LED CHIP, LED AND A METHOD FOR MANUFACTURING LED CHIP - The present invention relates to illuminating field, especially relates to LED chip, LED and a method of manufacturing LED chip, the method of manufacturing LED chip comprises: forming a first semiconductor layer, a luminous layer and a second semiconductor layer sequentially on a substrate; forming a phosphor powder layer on the second semiconductor layer; removing a part of the phosphor powder layer and a part of the second semiconductor layer to form at least one groove which exposes a part of the second semiconductor layer; removing a part of the phosphor powder layer, a part of the second semiconductor layer, a part of the luminous layer and a part of the first semiconductor layer to form at least one unfilled corner which exposes a part of the first semiconductor layer; forming a first electrode in the unfilled corner, and forming a second electrode in the groove. In the present invention, the process of coating phosphor powder in manufacturing LED is brought into the course of LED chip manufacturing, the advantages of this procedure are simple, controllable, to improve the light extraction efficiency of LED, to save a lot of phosphor powder and to greatly reduce the cost. | 2012-08-16 |
20120205705 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A vertical semiconductor light emitting device which can alleviate a concentration of current inside a semiconductor film without impairing the electrical connection between an ohmic electrode and the semiconductor film. The semiconductor light emitting device includes the semiconductor film in contact with a support; a first electrode for partially covering the surface of the semiconductor film opposite to the contact surface with the support; and a second electrode provided on the contact surface side of the semiconductor film with the support. The second electrode includes first and second transparent electrodes made of the mutually same metal oxide transparent electrical conductor and electrically connected to each other, and the second transparent electrode is located to be opposed to the first electrode with the semiconductor film interposed therebetween and has a higher contact resistance with the semiconductor film than the first transparent electrode does. | 2012-08-16 |
20120205706 | TWO-PHASE COOLING FOR LIGHT-EMITTING DEVICES - System, method, and apparatus for two phase cooling in light-emitting devices are disclosed. In one aspect of the present disclosure, an apparatus includes a light-emitting device and a two-phase cooling apparatus coupled to the light-emitting device. The coupling of the two-phase cooling apparatus and the light-emitting device is operatively configured such that thermal coupling between the light-emitting device and the two-phase cooling apparatus enables, when, in operation, heat generated from the light-emitting device to be absorbed by a substance of a first phase in the two-phase cooling apparatus to convert the substance to a second phase. | 2012-08-16 |
20120205707 | LIGHT-EMITTING DIODE PACKAGE - A light-emitting diode package includes: a frame unit, and at least one light-emitting diode chip including a chip body and a contact layer disposed between the chip body and the frame unit. One of the frame unit and the contact layer contains a magnetic material, and the other one of the frame unit and the contact layer contains a material capable of being magnetically attracted to the magnetic material. | 2012-08-16 |
20120205708 | LIGHT-EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device package. The light-emitting device package includes a lead frame comprising a plurality of separate leads; a molding member that fixes the plurality of leads and comprises an opening portion that exposes the lead frame; and a light-emitting device chip that is attached on the lead frame in the opening portion and emits light through an upper surface portion of the light-emitting device chip, wherein a height of the molding member is lower than a height of the light-emitting device chip with respect to the lead frame. | 2012-08-16 |
20120205709 | Light-Emitting Device and Lighting Device - A light-emitting device and a lighting device each including a light-emitting element which can recover from a short circuit between a pair of electrodes by itself without adversely affecting the characteristics of the element is provided. An oxide layer is provided so as to be in contact with an electrode of the light-emitting element, whereby, due to heat generated when a short circuit is caused between a pair of electrodes, oxygen in the oxide layer and an electrode material in a short-circuited part are reacted with each other and the electrode material in the short-circuited part can be an insulator. Further, by providing an oxide layer in contact with an electron-injection layer containing an alkaline earth metal, an oxide of the alkaline earth metal can be formed, whereby moisture that enters the insulator formed by an insulation phenomenon in the short-circuited part can be adsorbed and removed. | 2012-08-16 |
20120205710 | LED MODULE - A LED module includes a substrate, a LED chip supported on the substrate, a metal wiring installed on the substrate, the metal wiring including a mounting portion on which the LED chip is mounted, an encapsulating resin configured to cover the LED chip and the metal wiring, and a clad member configured to cover the metal wiring to expose the mounting portion, the encapsulating resin arranged to cover the clad member. | 2012-08-16 |
20120205711 | LIGHT EMITTING DEVICE - Disclosed are a light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes the light emitting structure layer including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers, a conductive support substrate electrically connected to the second conductive semiconductor layer, a contact electrically connected to the first conductive semiconductor layer, a dielectric material making contact with the contact and interposed between the contact and the conductive support substrate, and an insulating layer electrically insulating the contact from the active layer, the second conductive semiconductor layer, and the conductive support substrate. | 2012-08-16 |
20120205712 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A light-emitting device includes a light emitting element, a resin package defining a recessed portion serving as a mounting region of the light emitting element, gate marks each formed on an outer side surface of the resin package, and leads disposed on the bottom surface of the recessed portion and electrically connected to the light emitting element. The light emitting element is mounted on the lead. The gate marks include a first gate mark formed on a first outer side surface of the resin package and a second gate mark formed on an outer side surface which is different than the first outer side surface. | 2012-08-16 |
20120205713 | Memory Cells, Memory Arrays, Methods Of Forming Memory Cells, And Methods Of Forming A Shared Doped Semiconductor Region Of A Vertically Oriented Thyristor And A Vertically Oriented Access Transistor - A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor. | 2012-08-16 |
20120205714 | APPARATUS AND METHOD FOR PROTECTION OF ELECTRONIC CIRCUITS OPERATING UNDER HIGH STRESS CONDITIONS - Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device. | 2012-08-16 |
20120205715 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth. | 2012-08-16 |
20120205716 | Epitaxially Grown Extension Regions for Scaled CMOS Devices - Epitaxially grown extension regions are disclosed for scaled CMOS devices. Semiconductor devices are provided that comprise a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises at least a channel layer formed below the gate stack. One or more etched extension regions containing an epitaxially grown dopant are provided in the channel layer. | 2012-08-16 |
20120205717 | COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE DEVICE AND ELECTRIC DEVICE - A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure. | 2012-08-16 |
20120205718 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device including: a substrate; an electron transit layer formed on and above the substrate; and an electron supply layer formed on and above the electron transit layer, wherein a first region or regions having a smaller thermal expansion coefficient than the electron transit layer and a second region or regions having a larger thermal expansion coefficient than the electron transit layer are mixedly present on a surface of the substrate. | 2012-08-16 |
20120205719 | DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME - A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin. | 2012-08-16 |
20120205720 | TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES - Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film. | 2012-08-16 |
20120205721 | Design Structure for High Density Stable Static Random Access Memory - A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer. | 2012-08-16 |
20120205722 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device. | 2012-08-16 |
20120205723 | RANGE SENSOR AND RANGE IMAGE SENSOR - A range image sensor capable of improving its aperture ratio and yielding a range image with a favorable S/N ratio is provided. A range image sensor RS has an imaging region constituted by a plurality of one-dimensionally arranged units on a semiconductor substrate | 2012-08-16 |
20120205724 | ELECTRONIC CIRCUITS INCLUDING A MOSFET AND A DUAL-GATE JFET - Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. | 2012-08-16 |
20120205725 | Method of Fabricating a Semiconductor Device with a Strain Inducing Material - Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating. | 2012-08-16 |
20120205726 | Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates - A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate. | 2012-08-16 |
20120205727 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER - A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device. | 2012-08-16 |
20120205728 | Semiconductor Structure and Method for Manufacturing the Same - The present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, and forming a dummy gate stack on the substrate, sidewall spacers on sidewalls of the dummy gate stack, and source/drain regions at both sides of the dummy gate stack, wherein the dummy gate stack comprising a dummy gate; forming a first contact layer on surfaces of the source/drain regions; forming an interlayer dielectric layer to cover the first contact layer; removing the dummy gate or the dummy gate stack material to form an opening, filling the opening with a first conductive material or with a gate dielectric layer and a first conductive material to form a gate stack structure; forming through holes within the interlayer dielectric layer, so that a portion of the first contact layer or a portion of the first contact layer and the source/drain regions are exposed in the through holes; forming a second contact layer on the exposed portions of the regions; filling the through holes with a second conductive material to form contact vias. Besides, the present invention further provides a semiconductor structure, which is favorable for reducing the contact resistance. | 2012-08-16 |
20120205729 | FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. | 2012-08-16 |
20120205730 | TRANSPARENT CONDUCTIVE FILM FOR IMPROVING CHARGE TRANSFER IN BACKSIDE ILLUMINATED IMAGE SENSOR - The present disclosure provides an image sensor device and a method of forming the image sensor device. In an example, an image sensor device includes a substrate having a front surface and a back surface; a sensor element disposed at the front surface of the substrate, the sensor element being operable to sense radiation projected toward the back surface of the substrate; and a transparent conductive layer disposed over the back surface of the substrate, the transparent conductive layer at least partially overlying the sensor element. The transparent conductive layer is configured for being electrically coupled to a bottom portion of the sensor element. | 2012-08-16 |
20120205731 | SINGLE PHOTON AVALANCHE DIODES - A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well. | 2012-08-16 |
20120205732 | INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT - An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor. | 2012-08-16 |
20120205733 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND DOUBLE-LAYER METAL CONTACT AND FABRICATION METHOD THEREOF - Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer. | 2012-08-16 |
20120205734 | Very Dense NVM Bitcell - An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step. | 2012-08-16 |
20120205735 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region. | 2012-08-16 |
20120205736 | Memory Arrays and Methods of Forming Electrical Contacts - Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays. | 2012-08-16 |
20120205737 | SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 2012-08-16 |
20120205738 | NEAR ZERO CHANNEL LENGTH FIELD DRIFT LDMOS - Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space ( | 2012-08-16 |
20120205739 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF - The semiconductor device of this invention has unit cells, each of which includes: a substrate; a drift layer on the substrate; a body region in the drift layer; a first doped region of a first conductivity type in the body region; a second doped region of the first conductivity type arranged adjacent to the body region and in a surface region of the drift layer; a third doped region of the first conductivity type arranged between two adjacent unit cells' second doped region of the first conductivity type and in the surface region of the drift layer to contact with the second doped region of the first conductivity type; a gate insulating film arranged to contact with the surface of the drift layer at least between the first and second doped regions of the first conductivity type; a gate electrode on the gate insulating film; and first and second ohmic electrodes. The dopant concentration of the third doped region of the first conductivity type is lower than that of the second doped region of the first conductivity type and equal to or higher than that of the drift layer. | 2012-08-16 |
20120205740 | Lateral Power MOSFET With Integrated Schottky Diode - A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate. | 2012-08-16 |
20120205741 | STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween. | 2012-08-16 |
20120205742 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SOI STRUCTURE USING A BULK SEMICONDUCTOR STARTING WAFER - Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., single-fin or multi-fin MUGFET, multiple series-connected single-fin, multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections). Also disclosed is a SOI structure formed using the above-described method. | 2012-08-16 |
20120205743 | PD SOI DEVICE WITH A BODY CONTACT STRUCTURE - The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology. | 2012-08-16 |
20120205744 | BODY CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE - Embodiments of the invention provide SOI body-contacted transistors that can be used for high frequency analog and digital circuits. In accordance with certain embodiments of the invention, the SOI transistor gate can have an “I” shape, similar to the shape of the gate of a floating body SOI transistor. However, a body region is provided that extends perpendicular to the width direction of the gate and is contacted at an end of the extended body region. To form such a body contact structure, a source/drain implant block mask and silicide block mask are used during the formation of the source/drain regions. The source/drain implant block mask and silicide block mask can be formed on the same region, but the silicide block mask can allow for the body contact portion at the end of the extended body region to be silicided during the siliciding of the source/drain regions. | 2012-08-16 |
20120205745 | Device and Associated Semiconductor Package for Limiting Drain-Source Voltage of Transformer-Coupled Push Pull Power Conversion Circuit - A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage V | 2012-08-16 |
20120205746 | END-TO-END GAP FILL USING DIELECTRIC FILM - A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures. | 2012-08-16 |
20120205747 | SEMICONDUCTOR SUBSTRATE, FIELD-EFFECT TRANSISTOR, INTEGRATED CIRCUIT, AND METHOD FOR FABRICATING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth. | 2012-08-16 |
20120205748 | DEVICE LAYOUT IN INTEGRATED CIRCUITS TO REDUCE STRESS FROM EMBEDDED SILICON-GERMANIUM - An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated. | 2012-08-16 |
20120205749 | SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE - Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects. | 2012-08-16 |
20120205750 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks. | 2012-08-16 |
20120205751 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a substrate, and a gate electrode provided on the substrate via a gate insulator. The device further includes a source region of a first conductivity type and a drain region of a second conductivity type provided in the substrate to sandwich the gate electrode, and a channel region provided between the source and drain regions in the substrate. The gate insulator includes a first insulator portion having a first edge which is positioned on the source region and is parallel to a channel-width direction, and a second edge which is positioned on the channel or source region and is parallel to the channel-width direction, and having a first thickness. The gate insulator further includes a second insulator portion positioned on a drain region side with respect to the first insulator portion, and having a second thickness greater than the first thickness. | 2012-08-16 |
20120205752 | Strengthened Micro-Electromechanical System Devices and Methods of Making Thereof - In an embodiment, a micro-electromechanical device can include a substrate, a beam, and an isolation joint. The beam can be suspended relative to a surface of the substrate. The isolation joint can be between a first portion and a second portion of the beam, and can have a non-linear shape. In another embodiment, a micro-electromechanical device can include a substrate, a beam, and an isolation joint. The beam can be suspended relative to a surface of the substrate. The isolation joint can be between a first portion and a second portion of the beam. The isolation joint can have a first portion, a second portion, and a bridge portion between the first portion and the second portion. The first and second portions of the isolation joint can each have a seam and a void, while the bridge portion can be solid. | 2012-08-16 |
20120205753 | MICRO-ELECTROMECHANICAL SYSTEM DEVICES AND METHODS OF MAKING MICRO-ELECTROMECHANICAL SYSTEM DEVICES - A micro-electromechanical system (MEMS) device includes a substrate, a first beam, a second beam, and a third beam. The first beam includes first and second portions separated by an isolation joint. The first and second portions each comprise a semiconductor and a first dielectric layer. An electrically conductive trace is mechanically coupled to the first beam and electrically coupled to the second portion's semiconductor but not the first portion's semiconductor. The second beam includes a second dielectric layer. The profile of each of the first, second, and third beams has been formed by a dry etch. A cavity separates a surface of the substrate from the first, second, and third beams. The cavity has been formed by a dry etch. A side wall of each of the first, second, and third beams has substantially no dielectric layer disposed thereon, and the dielectric layer has been removed by a vapor-phase etch. | 2012-08-16 |
20120205754 | PIEZOELECTRIC DEVICE AND METHOD FOR MANUFACTURING PIEZOELECTRIC DEVICE - A piezoelectric device includes a piezoelectric thin film formed by separating and forming a piezoelectric single crystal substrate, an inorganic layer formed on a back surface of the piezoelectric thin film, an elastic body layer disposed on a surface opposite to the piezoelectric thin film of the inorganic layer, and a support pasted to a surface opposite to the inorganic layer of the elastic body layer. In a membrane structure portion, the inorganic layer and the elastic body layer are disposed on the piezoelectric thin film through a gap layer. The elastic body layer reduces a stress caused by pasting the piezoelectric thin film including the inorganic layer and the support and has a certain elastic modulus. The inorganic layer is formed with a material having an elastic modulus higher than that of the elastic body layer and suppresses damping caused by disposing the elastic body layer. | 2012-08-16 |
20120205755 | MEMS MICROPHONE - A MEMS microphone has a cover, a base and a MEMS chip. The cover has a contact voice receiving unit which is disposed on the base, and a space is formed between the cover and the base. The MEMS chip is disposed in the space and electrically connected to the base and the contact voice receiving unit. The MEMS microphone enhances the quality of voice transmission by reducing interferences from ambient noises. | 2012-08-16 |
20120205756 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - A semiconductor device includes a semiconductor chip with a gate electrode, and a stress detecting element placed on a surface of the semiconductor chip, and which detects stress applied to the surface. The semiconductor device controls a control signal to be applied to the gate electrode in response to stress detected by the stress detecting element. The stress detecting element is preferably provided as a first stress detecting element which detects stress applied to a central portion of the semiconductor chip in plan view. The stress detecting element is preferably provided as a second stress detecting element which detects stress applied to a circumferential portion of the semiconductor chip in plan view. | 2012-08-16 |
20120205757 | Pinning field in MR devices despite higher annealing temperature - The pinning field in an MR device was significantly improved by using the Ru 4A peak together with steps to minimize interfacial roughness of the ruthenium layer as well as boron and manganese diffusion into the ruthenium layer during manufacturing. This made it possible to anneal at temperatures as high as 340° C. whereby a high MR ratio could be simultaneously achieved. | 2012-08-16 |
20120205758 | Magnetic element with improved out-of-plane anisotropy for spintronic applications - A magnetic element is disclosed wherein first and second interfaces of a free layer with a Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to lower switching current or increase thermal stability in a magnetic tunnel junction (MTJ). In a MTJ with a bottom spin valve configuration where the Hk enhancing layer is an oxide, the capping layer contacting the Hk enhancing layer is selected to have a free energy of oxide formation substantially greater than that of the oxide. The free layer may be a single layer or composite comprised of an Fe rich alloy such as Co | 2012-08-16 |
20120205759 | MAGNETIC TUNNEL JUNCTION WITH SPACER LAYER FOR SPIN TORQUE SWITCHED MRAM - A magnetic tunnel junction (MTJ) includes first and second magnetic layers; a tunnel barrier located between the first and second magnetic layers; a first spacer layer located between the first magnetic layer and the tunnel barrier, the first spacer layer comprising a non-magnetic material; and a first interfacial layer located between the first spacer layer and the tunnel barrier. | 2012-08-16 |
20120205760 | MAGNETIC RANDOM ACCESS MEMORY WITH FIELD COMPENSATING LAYER AND MULTI-LEVEL CELL - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field. | 2012-08-16 |
20120205761 | Non-Volatile Magnetic Memory with Low Switching Current and High Thermal Stability - A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer. | 2012-08-16 |
20120205762 | MAGNETIC TUNNEL JUNCTION DEVICE - The magnetic tunnel junction device of the present invention includes a first ferromagnetic layer, a second ferromagnetic layer, an insulating layer formed between the first ferromagnetic layer and the second ferromagnetic layer. The insulating layer is composed of fluorine-added MgO. The fluorine content in the insulating layer is 0.00487 at. % or more and 0.15080 at. % or less. This device, although it includes a MgO insulating layer, exhibits superior magnetoresistance properties to conventional devices including MgO insulating layers. The fluorine content is preferably 0.00487 at. % or more and 0.05256 at. % or less. | 2012-08-16 |
20120205763 | NON-VOLATILE MAGNETIC MEMORY WITH LOW SWITCHING CURRENT AND HIGH THERMAL STABILITY - A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer. | 2012-08-16 |
20120205764 | Methods of Integrated Shielding into MTJ Device for MRAM - Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via. | 2012-08-16 |
20120205765 | IMAGE SENSORS WITH STACKED PHOTO-DIODES - This describes color filter arrangements for image sensor arrays that are formed using image sensor pixels with stacked photo-diodes. The stacked photo-diodes may include first and second photo-diodes and may have the ability to separate color signal according to the depth of carrier generation in a silicon substrate. A single color filter may be formed over the stacked photo-diodes to provide full red-green-blue sensing capability. Charge drain regions may also be formed at different depths in the silicon substrate. If the charge drain regions are formed beneath the stacked photo-diodes in the substrate, full red-green-blue color sensing may be achieved without the use of color filters. | 2012-08-16 |
20120205766 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME AND ELECTRONIC APPARATUS - A solid-state imaging device includes: an optical filter in which a filter layer is formed on a transparent substrate; a solid-state imaging component that is arranged to be opposed to the optical filter and in which plural pixels that receive light made incident via the filter layer are arrayed in a pixel area of a semiconductor substrate; and a bonding layer that is provided between the optical filter and the solid-state imaging component and sticks the optical filter and the solid-state imaging component together. | 2012-08-16 |
20120205767 | PLASMONIC DETECTOR AND METHOD FOR MANUFACTURING THE SAME - A plasmonic detector and method for manufacturing a plasmonic detector. The plasmonic detector comprises two nanoscale metallic rods coupled to a bias voltage; a nanoscale cavity formed between adjacent ends of the two nanoscale metallic rods; and an absorption material disposed in the nanoscale cavity for converting an electromagnetic field to an electric current for outputting via the nanoscale metallic rods. | 2012-08-16 |
20120205768 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus including an insulating structural body having a through opening, a wiring part formed on a front surface of the structural body, a solid-state imaging element which is connected to the wiring part and also is attached to the structural body so as to close the through opening, a translucent member which is opposed to the solid-state imaging element and is attached to the structural body through an adhesive inside an adhesion region R so as to close the through opening, and a solder resist film with which at least a part of the front surface of the structural body is covered, and is characterized in that a region R | 2012-08-16 |
20120205769 | BACK SIDE ILLUMINATED IMAGE SENSOR WITH REDUCED SIDEWALL-INDUCED LEAKAGE - Provided is an image sensor device. The image sensor device includes having a front side, a back side, and a sidewall connecting the front and back sides. The image sensor device includes a plurality of radiation-sensing regions disposed in the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers and extends beyond the sidewall of the substrate. The image sensor device includes a bonding pad that is spaced apart from the sidewall of the substrate. The bonding pad is electrically coupled to one of the interconnect layers of the interconnect structure. | 2012-08-16 |
20120205770 | SCHOTTKY DIODE WITH HIGH ANTISTATIC CAPABILITY - A Schottky diode with high antistatic capability has an N− type doped drift layer formed on an N+ type doped layer. The N− type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N− type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N− type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability. | 2012-08-16 |
20120205771 | SCHOTTKY DIODE WITH LOW FORWARD VOLTAGE DROP - A Schottky diode with a low forward voltage drop has an N− type doped drift layer formed on an N+ type doped layer. The N− type doped drift layer has a first surface with a protection ring inside which is a P-type doped area. The N− type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N− type doped drift layer and the P-type doped area forms a Schottky barrier. The height of the Schottky barrier is lower than the surface of the N− type doped drift layer, thereby reducing the thickness of the N− type doped drift layer under the Schottky barrier. This configuration reduces the forward voltage drop of the Schottky barrier. | 2012-08-16 |
20120205772 | TRENCH SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A trench Schottky diode and a manufacturing method thereof are provided. A plurality of trenches are formed in Asemiconductor substrate. A plurality of doped regions are formed in the semiconductor substrate and under some of the trenches. A gate oxide layer is formed on a surface of the semiconductor substrate and the surfaces of the trenches. A polysilicon structure is formed on the gate oxide layer. Then, the polysilicon structure is etched, so that the gate oxide layer within the trenches is covered by the polysilicon structure. Then, a mask layer is formed to cover the polysilicon structure within a part of the trenches and a part of the gate oxide layer, and the semiconductor substrate uncovered by the mask layer is exposed. Afterwards, a metal sputtering layer is formed to cover a part of the surface of the semiconductor substrate. | 2012-08-16 |
20120205773 | SCHOTTKY DIODE WITH LOWERED FORWARD VOLTAGE DROP - A Schottky diode with a lowered forward voltage drop has an N− type doped drift layer formed on an N+ type doped layer. The N− type doped drift layer has a surface formed with a protection ring inside which is a P-type doped layer. The surface of the N− type doped drift layer is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N− type doped drift layer within the P-type doped layer forms a Schottky barrier. An upward extending N type doped layer is formed on the N+ type doped layer and under the Schottky barrier to reduce the thickness of the N− type doped drift layer under the Schottky barrier. This lowers the forward voltage drop of the Schottky diode. | 2012-08-16 |
20120205774 | ISOLATION STRUCTURE PROFILE FOR GAP FILLING - An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth. | 2012-08-16 |
20120205775 | METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - The invention relates to a method for manufacturing a semiconductor device. Accordingly, the trench processing sequence is changed and stress absorbing layers are applied. A shallow trench structure is etched. A deep trench structure is etched. A liner oxide is applied in the deep and shallow trench structure. An amorphous polysilicon liner is deposited on top of the liner oxide. A nitride liner is applied on top of the amorphous polysilicon liner, and the deep and shallow trenches are filled with oxide. | 2012-08-16 |
20120205776 | DUAL CONTACT TRENCH RESISTOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - The invention relates to a semiconductor structures and methods of manufacture and, more particularly, to a dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture. In a first aspect of the invention, a method comprises forming a trench in a substrate; forming a first insulator layer within the trench; forming a first electrode within the trench, on the first insulator layer, and isolated from the substrate by the first insulator layer; forming a second insulator layer within the trench and on the first electrode; and forming a second electrode within the trench, on the second insulator layer, and isolated from the substrate by the first insulator layer and the second insulator layer. | 2012-08-16 |
20120205777 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a trench formed in a substrate and defining a plurality of active regions, a punch-through prevention layer filling a part of the trench and coupled to a ground, and an isolation layer formed over the punch-through prevention layer and filling the other part of the trench. | 2012-08-16 |
20120205778 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a package structure and method for manufacturing the same. The package structure can minimize the area of the circuit board used for packaging, by stacking a passive element directly on a chip. The disclosed package structure comprises: a circuit board having a first surface, where a plurality of first connecting pads being disposed thereon; a chip unit having an active surface, a non-active surface and a plurality of conductive vias, while a plurality of second connecting pads and a plurality of electric pads being disposed on the active surface, and a plurality of third connecting pads being disposed on the non-active surface; a plurality of solder balls electrically connected with the first connecting pads and the second connecting pads; and a passive element being electrically connected with the third connecting pads. The passive element and the chip unit both electrically connect to the chip unit. | 2012-08-16 |
20120205779 | SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METAL CONTACTS, AND METHODS OF FABRICATING THE SAME - Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided. | 2012-08-16 |
20120205780 | Methods, Systems and Devices for Electrostatic Discharge Protection - A resistor-equipped transistor includes a package that provides an external collector connection node ( | 2012-08-16 |
20120205781 | SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO - A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region. | 2012-08-16 |
20120205782 | Imprint Apparatus, Imprint Method, and Process Condition Selection Method - An imprint apparatus of one embodiment includes: a resist dropping unit adapted to drop resist onto a substrate; a patterning unit adapted to pattern the resist into transfer patterns corresponding to the template patterns; and a control unit configured to change a dropping condition for a resist dropping process shot by shot. The control unit is adapted to control, as the dropping condition, the distance to the position of a droplet of the resist to be dropped onto the substrate from a position on the substrate to be pressed with an assessment pattern, the assessment pattern being one of the template patterns that is to be assessed. | 2012-08-16 |
20120205783 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a first non-flat non-polar nitride semiconductor layer, a first structure layer on at least a portion of the surface of the first non-flat non-polar nitride semiconductor layer and a first non-polar nitride semiconductor layer on the first non-flat non-polar nitride semiconductor layer and the first structure layer. The first non-flat non-polar nitride semiconductor layer includes a plurality of solid particles. | 2012-08-16 |
20120205784 | GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES - Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient. | 2012-08-16 |
20120205785 | Technique for Etching Monolayer and Multilayer Materials - A process is disclosed for sectioning by etching of monolayers and multilayers using an RIE technique with fluorine-based chemistry. In one embodiment, the process uses Reactive Ion Etching (RIE) alone or in combination with Inductively Coupled Plasma (ICP) using fluorine-based chemistry alone and using sufficient power to provide high ion energy to increase the etching rate and to obtain deeper anisotropic etching. In a second embodiment, a process is provided for sectioning of WSi | 2012-08-16 |
20120205786 | METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE - A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer. | 2012-08-16 |
20120205787 | ORGANIC GRADED SPIN ON BARC COMPOSITIONS FOR HIGH NA LITHOGRAPHY - An antireflective coating that contains at least two polymer components and comprises chromophore moieties and transparent moieties is provided. The antireflective coating is useful for providing a single-layer composite graded antireflective coating formed beneath a photoresist layer. | 2012-08-16 |
20120205788 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another. | 2012-08-16 |
20120205789 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device, a first semiconductor element having a first terminal is embedded in a resin layer such that terminals thereof are exposed through a first surface of the resin layer. A wiring layer is formed in the first surface of the resin layer. A second semiconductor element includes second and third terminals. Regardless of the relationship between the plane size of the first semiconductor element and that of the second semiconductor element, the second terminal of the second semiconductor element is connected to the first terminal of the first semiconductor element exposed through the first surface of the resin layer, and the third terminal of the second semiconductor element is connected to the wiring layer formed in the resin layer. | 2012-08-16 |
20120205790 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a stacked structure including a lead frame having a front surface and a back surface, the front surface being made of Cu, a semiconductor chip having a front surface and a back surface, including a Cu layer that forms the back surface, disposed so that the back surface is opposed to the front surface of the lead frame, and a bonding layer interposed between the lead frame and the semiconductor chip, in which the bonding layer includes a Bi-based material layer and Cu alloy layers not containing Pb that sandwich the Bi-based material layer from both sides in an opposing direction of the lead frame and the semiconductor chip with respect to the Bi-based material layer. | 2012-08-16 |
20120205791 | SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS - A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side. | 2012-08-16 |
20120205792 | SEMICONDUCTOR DEVICE - Between a logic LSI ( | 2012-08-16 |
20120205793 | SEED LAYER PASSIVATION - A method of processing a microfeature workpiece generally includes depositing a first conducting layer, at least partially reducing oxides on the first conducting layer to provide a reduced first conducting layer, and exposing the reduced first conducting layer to a substantially oxygen-free environment to provide a passivated first conducting layer. A microfeature workpiece generally includes a first conducting layer, a monolayer directly on the first conducting layer, and a second conducting layer. | 2012-08-16 |
20120205794 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE AND SEMICONDUCTOR CHIP - A semiconductor chip package structure including a first semiconductor chip, a second semiconductor chip and a supporting substrate is provided. The first semiconductor chip includes at least a first conductor unit. The first conductor unit has a first bonding surface and a second bonding surface exposed from the first semiconductor chip. The second semiconductor chip includes at least a second conductor unit. The second conductor unit has a third bonding surface and a fourth bonding surface exposed from the second semiconductor chip. The third bonding surface is contacted with and electrically connected to the first bonding surface. The supporting substrate includes a wire unit for electrically connecting to at least one of the second bonding surface and the fourth bonding surface. A semiconductor chip and a semiconductor chip group are also provided. | 2012-08-16 |
20120205795 | STACKED PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs. | 2012-08-16 |
20120205796 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a substrate having a connection terminal with a groove on its surface. Nanopowder may be disposed on a bottom of the groove. A semiconductor chip may be flip-chip bonded to the substrate by the nanopowder. A filler member may be interposed between the substrate and the semiconductor chip. | 2012-08-16 |
20120205797 | BUMP AND SEMICONDUCTOR DEVICE HAVING THE SAME - A bump includes a metal pillar formed over a structural body; and a diffusion barrier member formed to cover at least a portion of a side surface of the metal pillar. | 2012-08-16 |
20120205798 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer. | 2012-08-16 |
20120205799 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed. | 2012-08-16 |
20120205800 | PACKAGING STRUCTURE - A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip. | 2012-08-16 |
20120205801 | Anti-Tamper Wrapper Interconnect Method and a Device - A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads. | 2012-08-16 |
20120205802 | PRINTED CIRCUIT BOARD AND FLIP CHIP PACKAGE USING THE SAME WITH IMPROVED BUMP JOINT RELIABILITY - A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land. | 2012-08-16 |
20120205803 | PACKAGING CONFIGURATIONS FOR VERTICAL ELECTRONIC DEVICES USING CONDUCTIVE TRACES DISPOSED ON LAMINATED BOARD LAYERS - This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals. | 2012-08-16 |