31st week of 2010 patent applcation highlights part 22 |
Patent application number | Title | Published |
20100194371 | DC-DC CONVERTER AND SWITCHING CONTROL CIRCUIT - Disclosed a switching control circuit including: a first drive circuit to generate a drive signal for driving a driving switching element to flow current through an inductor for voltage conversion into on/off states; wherein the first drive circuit generates the drive signal so that a transition time of the drive signal in which the driving switching element shifts from an off state to an on state becomes longer than a transition time of the drive signal in which the driving switching element shifts from the on state to the off state. | 2010-08-05 |
20100194372 | MODE CONTROL CIRCUIT FOR SWITCHING REGULATORS AND METHOD THEREOF - A mode control method and apparatus for a switching regulator is disclosed. The method receives an input signal and amplifying the input signal to get an amplified signal. The amplified signal is sent to a sample circuit to get a sample signal. The sample signal is delivered to an averaging circuit to get an averaged sensed output signal. The averaged sensed output signal is compared with a first pre-determined threshold or an second pre-determined threshold to get a PWM enable signal. The appropriate mode is determined based on the PWM enable signal. | 2010-08-05 |
20100194373 | Electrical Transformer with Unidirectional Flux Compensation - transformer includes a soft magnetic core on which a primary winding arrangement, a secondary winding arrangement, and a compensation winding arrangement are arranged. The compensation winding arrangement is connected to a current control device which feeds a compensation current into the compensation winding arrangement using a control signal. A magnetic field measuring device measures the magnetic field in the core of the transformer or the stray magnetic field that closes outside the core via an air path and provides the control signal. | 2010-08-05 |
20100194374 | SYSTEM AND METHOD FOR PROVIDING ELECTROMAGNETIC IMAGING THROUGH ELECTROQUASISTATIC SENSING - A system and method for providing electromagnetic imaging through electroquasistatic sensing contains an electromagnetic sensor for imaging a sample. The electromagnetic sensor contains drive/sense electronics and a pixelated sensor array having an array of capacitive sensor electrodes that source electric fields that interact with the sample, and wherein the electrodes are individually drivable by the drive/sense electronics in a coordinated manner to establish a desired temporal and spatial pattern in which electrical properties of the electrodes are used to generate an image. Other components of the system include a precision motion controller, sensor head and associated electronics, and a computer for performing data acquisition and signal inversion. | 2010-08-05 |
20100194375 | ELECTRONIC TRANSFORMER MEASURING DEVICE HAVING SURFACE MOUNTING ASSEMBLY - A method and apparatus for mounting an electronic measuring device inside the housing a pad mount low voltage distribution power transformer are provided. The space inside a transformer enclosure cover contains the power input and output connections and cables. The electronic measuring device includes a surface mounting assembly that is configured to mount the measuring device at multiple locations of the housing. | 2010-08-05 |
20100194376 | METHOD FOR IMPLEMENTING CONTINUOUS RADIO FREQUENCY (RF) ALIGNMENT IN ADVANCED ELECTRONIC WARFARE (EW) SIGNAL STIMULATION SYSTEMS - A method for characterizing the effect of each step attenuator state, on phase and amplitude, which may include in an exemplary embodiment: activating each step attenuator state as the sole contributor to attenuation, and measuring at least one of a step attenuator amplitude contribution (SAAC) and/or a step attenuator phase contribution (SAPC). | 2010-08-05 |
20100194377 | PRIME-BASED FREQUENCY SAMPLING - Various embodiments provide methods, apparatuses, and systems for sampling a waveform using relatively prime sampling methods. A waveform with a first plurality of cycles and a first frequency may be sampled with a waveform sampling device. Sampling the waveform may include sampling the waveform at a sampling rate of the waveform sampling device. Sampling the waveform may include taking a sample number of samples of the waveform where the sample number may be relatively prime with respect to the number of cycles of the waveform. The sample number of samples of the waveform may be interleaved with a controller. | 2010-08-05 |
20100194378 | SYSTEM FOR PHASE IDENTIFICATION - A phase identification system for identifying the phase of an extra-high- voltage or low-voltage power distribution line is disclosed. The phase identification system compares a reference phase of a transformer substation with a phase of a power distribution line remote from the transformer substation and identifies the phase. The phase identification system includes a reference unit capturing the reference phase from the transformer substation and transmitting the reference phase to a service server, the service server storing the reference phase received from the reference unit for 30 to 60 minutes and externally transmitting the reference phase via a network, the network providing a data communication path between the service server and a local unit, and the local unit capturing the phase from the power distribution line, receiving the reference phase from the service server, and identifying the phase captured from the power distribution line. | 2010-08-05 |
20100194379 | OPTICAL FIBER ELECTRIC CURRENT MEASUREMENT APPARATUS AND ELECTRIC CURRENT MEASUREMENT METHOD - In a reflection type optical fiber electric current measurement apparatus, a standardization reference signal (Xr), which is defined by the intensity (Pr) of the optical reference signal transmitted through a partial transmission mirror by using a reflector ( | 2010-08-05 |
20100194380 | METHOD AND APPARATUS FOR MEASURING CURRENT OUTPUT OF LOW-VOLTAGE PAD-MOUNT DISTRIBUTION POWER TRANSFORMERS - A current sensing assembly is provided for sensing the current travelling through a current carrying member of a pad mount distribution transformer in a meter network. A current sensor includes a slot having an open end that receives the current carrying member. The sensor includes a conductive coil disposed adjacent the slot that generates an output signal indicating a sensed current level. A retainer member includes a retainer wall that is configured to be inserted into the open end of the slot so as to define a receptacle that captures the current carrying member therein. | 2010-08-05 |
20100194381 | Current detection apparatus - A current detection apparatus where a sensor unit that detects the magnetic field in a predetermined magnetic field detection direction is disposed in a vicinity such that the magnetic field detection direction is substantially orthogonal to an extension direction of the subject bus bar at the detection portion, one of the plurality of bus bars disposed adjacent to the subject bus bar is set as an adjacent bus bar, a plane that is orthogonal to an extension direction of each portion of the adjacent bus bar is set as an extension orthogonal plane of the portion, and the extension direction of each portion of the adjacent bus bar relative to the sensor unit is set such that none of the extension orthogonal planes of the respective portions of the adjacent bus bar pass through the sensor unit in a parallel direction to the magnetic field detection direction. | 2010-08-05 |
20100194382 | METHOD FOR DETERMINING ELECTRICAL POWER SIGNAL LEVELS IN A TRANSMISSION SYSTEM - A signal level detection method is provided, the method includes providing a feed line system that includes coaxial cable connectors connected coaxial cable sections. Each coaxial cable connector includes a connector body, a coupling circuit positioned within the connector body, an electrical signal power level detection circuit electrically connected to the coupling circuit and comprised by the connector body, and an output component comprised by the connector body. At least one coupling circuit senses an electrical signal flowing through at least one associated coaxial cable connector. At least one electrical signal power level detection circuit detects a plurality of associated power levels of the electrical signal flowing through at least one associated coaxial cable connector. | 2010-08-05 |
20100194383 | APPARATUS FOR DETERMINING AND/OR MONITORING A PROCESS VARIABLE - An apparatus for determining and/or monitoring at least one process variable of a medium. The apparatus includes: at least one probe unit; and at least one electronics unit, which supplies the probe unit with an operating signal and which receives from the probe unit a received signal. The probe unit includes at least one probe electrode and at least one guard electrode; and the probe electrode and the guard electrode are surrounded, at least partially, by at least one insulating unit. The the insulating unit has, in the region of the guard electrode, a smaller thickness than in the region of the probe electrode. | 2010-08-05 |
20100194384 | SYSTEM INCLUDING CIRCUIT THAT DETERMINES CALIBRATION VALUES - A system including magnetic sensing elements and a circuit. The magnetic sensing elements are configured to sense a magnetic field that is generated via a current and to provide signals that correspond to the magnetic field. The circuit is configured to determine calibration values based on the signals and measure the current based on the signals. | 2010-08-05 |
20100194385 | NON-CONTACT MULTI-TURN ABSOLUTE POSITION MAGNETIC SENSOR COMPRISING A THROUGH-SHAFT - The invention relates to an absolute position magnetic sensor for measuring the angular position, on a theta course, of a shaft passing through said sensor and comprising at least two systems for detecting the position of the shaft. Said invention is characterised in that: at least one of the detection systems generates a signal according to a “periodical” function of the theta/n period giving the periodical angular position of said shaft; at least one of the detection systems generates an absolute signal on a theta course of the shaft; and theta and n fit the equation: *theta/n=360*n>1. | 2010-08-05 |
20100194386 | MAGNETIC SENSOR DEVICE - The present invention provides a sensor device ( | 2010-08-05 |
20100194387 | MAGNETORESISTANCE SENSOR AND METHOD OF OPERATING A MAGNETORESISTANCE SENSOR - A magnetoresistive sensor system ( | 2010-08-05 |
20100194388 | Magnetic resonance imaging (MRI) using spir and/or chess suppression pulses - A magnetic resonance imaging apparatus includes an imaging condition setting unit and an image data acquisition unit. The imaging condition setting unit sets an imaging condition applying first and second suppression pulses of which at least ones of types, center frequencies and frequency bands are different from each other. The first and the second suppression pulses frequency-selectively suppress at least one of fat and silicone. The image data acquisition unit acquires image data according to the imaging condition. | 2010-08-05 |
20100194389 | METHOD FOR DYNAMIC MOTION GUIDED FUNCTIONAL MAGNETIC RESONANCE IMAGING - A method for imaging neuromuscular coupling and sensory processing with magnetic resonance imaging (“MRI”) is provided. More specifically, a method for examining the control that a subject's brain has over muscular motion, including both prompted and incidental actions, is provided. A dynamic acquisition is performed to rapidly acquire anatomical images of a desired muscle. This dynamic acquisition is interleaved with a functional acquisition that targets the cortical areas that are responsible for controlling, or processing, signals from the desired muscular region. By interleaving these two acquisitions, synchronized image information about the motion of the muscle along with the neuronal activity associated with the control of the muscle is acquired. Interleaving these data acquisitions also allows imaging of brain and muscle at substantially the same time, thereby reducing errors and pinpointing activity. | 2010-08-05 |
20100194390 | MAGNETIC RESONANCE METHOD AND APPARATUS FOR TIME-RESOLVED ACQUISITION OF MAGNETIC RESONANCE DATA - In a magnetic resonance method and apparatus for time-resolved acquisition of magnetic resonance data in an examination region of a magnetic resonance imaging scanner, an object being examined is placed on a table and is continuously moved through the examination region, magnetic resonance signals are acquired from the examination region while the object being examined is continuously moved with the table through the examination region and prior to the acquisition of magnetic resonance signals, a phase coding that corresponds to a position in k-space, for the purpose of sampling k-space, is carried out. An interruption of the movement of the table takes place at a predetermined table position, and the acquisition of magnetic resonance signals from an examination region is continued over the course of a predetermined time period, while the table ( | 2010-08-05 |
20100194391 | COMPENSATION DEVICE TO REDUCE THE ELECTROMAGNETIC FIELD LOAD DUE TO A MEDICAL INTERVENTION APPARATUS IN MAGNETIC RESONANCE EXAMINATIONS - A compensation device to reduce the electromagnetic field load due to the presence of a medical intervention apparatus in magnetic resonance examinations, has: a control device that has a radio-frequency input and a radio-frequency output, an injection device that is connected with the radio-frequency output and that injects the radio-frequency power delivered by the control device into the medical intervention apparatus, a measurement device that measures at least one electrical variable at the intervention apparatus, and a regulator that is connected with the control device and the measurement device. The regulator adjusts the control device to deliver the radio-frequency power so that the electrical variable at the intervention apparatus is reduced. | 2010-08-05 |
20100194392 | APPARATUS AND METHOD FOR RECONSTRUCTING AN MR IMAGE - An MR imaging apparatus is disclosed, wherein the MR imaging apparatus includes a plurality of gradient coils positioned about a bore of a magnet, and an RF transceiver system controlled by a pulse module to transmit RF signals to an RF coil assembly. The MR imaging apparatus also includes a controller coupled to the plurality of gradient coils and the RF transceiver system and programmed to obtain MR image signals at different echo times from a subject containing metabolites having known characteristics. The controller is further programmed to reconstruct images of the metabolites in a selected region of interest (ROI) using a probabilistic mathematical expression based on known information regarding an image acquisition process and using a spatial distribution of the metabolites to account for artifacts in the images. | 2010-08-05 |
20100194393 | GRADIENT COIL DEVICE, MAGNETIC RESONANCE IMAGING DEVICE, AND METHOD OF DESIGNING COIL PATTERN - There is provided a gradient coil device which can suppress any generation of an error magnetic field and thus an eddy current, and which can improve the image quality of a cross-sectional image. An MRI device includes a first coil generating a linear magnetic field distribution at an imaging region of the MRI device, and a second coil which suppresses any leakage of a magnetic field from the first coil to a static-magnetic-field coil device that generates a uniform magnetic field distribution at the imaging region. | 2010-08-05 |
20100194394 | SYSTEMS AND METHODS FOR REMOTE ELECTROMAGNETIC EXPLORATION FOR MINERAL AND ENERGY RESOURCES - A method for measuring the resistivity of geologic formations is described. An electromagnetic field may be generated using at least one stationary long-range transmitter. The frequency of the electromagnetic field may be between and/or including the ULF/ELF range. At least one component of the electromagnetic field may be measured by land, marine, and/or airborne receiver. A conductivity distribution may be determined based on the at least one measured component. The determined conductivity distribution may be correlated with geological formations and/or hydrocarbon deposits. | 2010-08-05 |
20100194395 | ENHANCED PASSIVE RANGING METHODOLOGY FOR WELL TWINNING - A method for drilling substantially parallel twin wells includes drilling a first well and deploying a casing string in the first well. A magnetized section of the casing string includes a plurality of magnetized wellbore tubulars having at least one pair of opposing magnetic poles located between longitudinally opposed ends of the wellbore tubular. A portion of a second well is drilled within sensory range of magnetic flux from the magnetized section of the casing string. The local magnetic field is measured in the second well and processed to determine a direction for subsequent drilling. Drilling proceeds along the direction for subsequent drilling. | 2010-08-05 |
20100194396 | Remotely reconfigurable system for mapping subsurface geological anomalies - A method and apparatus are provided for detecting and transmitting geophysical data from a plurality of electrodes inserted into the soil utilizing a set of identical dynamically reconfigurable voltage control units located on each electrode and connected together by a communications and power cable. A test sequence is provided in each voltage control unit. Each voltage control unit records data measurements for transmission to a central data collector. Each voltage control unit incorporates and determines its positional relationship to other voltage control units by logging when the unit is attached to the electrode. Each voltage control unit I equipped with a magnetic switch for detecting when they are in contact with the electrode. | 2010-08-05 |
20100194397 | MEASURING SYSTEM - There is provided a measuring system capable of rendering a power source voltage of an internal circuit higher than a drivable voltage of the internal circuit by removing or reducing a chloride film with greater certainty, thereby enabling operation, and initial activation of the internal circuit to be normally executed, or preventing the internal circuit from running away. The measuring system comprises a thionyl chloride based primary cell, a cell voltage measurement unit, and an internal circuit provided with state-transition controller wherein in the case of transition of the internal circuit to a state thereof, having a discharge current larger than the discharge current in the present state thereof, the transition is made according to results of comparison of a voltage measured by the cell voltage measurement unit with a threshold on the basis of a discharge current in a state before, or after the transition of the internal circuit. | 2010-08-05 |
20100194398 | RECHARGEABLE BATTERY ABNORMALITY DETECTION APPARATUS AND RECHARGEABLE BATTERY APPARATUS - The rechargeable battery abnormality detection apparatus is provided with an internal short circuit detection section ( | 2010-08-05 |
20100194399 | MEMORY SYSTEM, MEMORY TEST SYSTEM AND METHOD OF TESTING MEMORY SYSTEM AND MEMORY TEST SYSTEM - A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device. | 2010-08-05 |
20100194400 | Circuit Arrangement With A Test Circuit And A Reference Circuit And Corresponding Method - Implementations are presented herein that include a test circuit and a reference circuit. | 2010-08-05 |
20100194401 | SENSOR APPARATUS - A sensor apparatus of the present invention includes a first output terminal for outputting a sense signal, and a failure diagnosis circuit for determining whether a failure diagnosis object section is normal or abnormal, to output a failure detection signal from a second output terminal in the case of determining abnormality. The time required for an output concerning the failure detection signal from the failure diagnosis object section to reach the second output terminal is shorter than the time required for an output concerning the sense signal from the failure diagnosis object section to reach the first output terminal, thus leading to improvement in reliability under abnormal condition. | 2010-08-05 |
20100194402 | OPERATING CHARACTERISTIC MEASUREMENT DEVICE AND METHODS THEREOF - A device includes an integrated circuit device having a sensor to measure an operating characteristic of the device. The sensor provides information based on the measured operating characteristic to a trigger module. In response to the information indicating the measured operating characteristic meets a threshold associated with a device failure, the trigger module provides an indication to a storage element, which stores information indicating the threshold has been met. In the event of a failure of the integrated circuit device, the storage element can be accessed by a device analyzer to retrieve the stored information to determine the cause of the device failure. | 2010-08-05 |
20100194403 | PARTIAL DISCHARGE DETECTION SENSOR AND PARTIAL DISCHARGE DETECTION DEVICE USING THE SAME - A partial discharge detection sensor is used for detecting a partial discharge signal in a gas-insulated equipment using a PCB substrate, and a partial discharge detection device employs the partial discharge detection sensor. The partial discharge detection sensor includes a PCB substrate, a partial discharge signal detection pattern formed on the PCB substrate to detect a partial discharge signal in the gas-insulated equipment, and a connection terminal for receiving the partial discharge signal detected by the partial discharge signal detection pattern and transmitting the partial discharge signal to a connector that emits the partial discharge signal to the outside. The partial discharge detection sensor is attached to an inner wall of an enclosure of the gas-insulated equipment. | 2010-08-05 |
20100194404 | POWER SOURCE STABILIZATION CIRCUIT, ELECTRONIC DEVICE AND TESTING APPARATUS - A power source stabilization circuit provided within a chip of an electronic device is provided. The power source stabilization circuit stabilizes a power source voltage supplied to an operational circuit of the electronic device. The power source stabilization circuit includes an amplifier that detects a fluctuation component in the power source voltage occurring in a main power source wiring used to supply the power source voltage to the operational circuit, amplifies the detected fluctuation component, and outputs the amplified fluctuation component, and a stabilization capacitor that is provided between an output end of the amplifier and the main power source wiring and supplies to the main power source wiring a current to reduce fluctuation in the power source voltage occurring in the main power source wiring, in accordance with the output from the amplifier. | 2010-08-05 |
20100194405 | NOISE MEASUREMENT SYSTEM IN POWER STABILIZATION NETWORK, VARIABLE FILTER APPLIED TO THE SAME, AND METHOD FOR MEASURING NOISE IN POWER STABILIZATION NETWORK - A noise measurement system in power stabilization network, a variable filter applied to the same and a method for measuring noise in power stabilization network are disclosed, wherein the system comprises: a power stabilization network including a power input unit for receiving an external power, a power output unit for supplying a power to a power line communication modem and an output unit for a measurement instrument; a filter connected to the power stabilization network; and an EMI (Electromagnetic Interference) measurer. | 2010-08-05 |
20100194406 | HIGH-SPEED CAPACITOR LEAKAGE MEASUREMENT SYSTEMS AND METHODS - Systems and methods according to aspects of the present invention are described. The systems and methods enable charging, soaking, and measuring of capacitors to be conducted quickly. Charging and soaking typically occurs in parallel and certain embodiments facilitate the measuring of capacitor leakage by sequentially disconnecting each capacitor and measuring the time for voltage on the capacitor to reach a predetermined threshold. Further, all capacitors can be disconnected from a charging source simultaneously and voltages can be measured for each capacitor simultaneously. Monitoring can be periodic in nature. Substantial time savings in the calculation device of leakage values and parameters can be attained. | 2010-08-05 |
20100194407 | MEMS sensor - The MEMS sensor according to the present invention includes: a substrate made of a silicon material, having a recess dug down from the surface thereof; a fixed electrode made of a metallic material, arranged in the recess and fixed to the substrate; and a movable electrode made of a metallic material, arranged in the recess to be opposed to the fixed electrode and provided to be displaceable with respect to the fixed electrode. | 2010-08-05 |
20100194408 | Capacitance Detection in a Droplet Actuator - A method, circuit and apparatus for detecting capacitance on a droplet actuator, inter alia, for determining the presence, partial presence or absence of a droplet at an electrode on a droplet actuator by: (a) providing a droplet actuator comprising: (i) a substrate comprising electrodes arranged on the substrate for conducting droplet operations on a surface of the substrate; (ii) a capacitance detection circuit for detecting capacitance at the droplet operations surface at one or more of the electrodes; (b) detecting capacitance at the droplet operations surface at one or more of the electrodes; and (c) determining from the capacitance the presence, partial presence or absence of a droplet at the droplet operations surface at the electrode. | 2010-08-05 |
20100194409 | METHOD OF ELECTRICALLY DETECTING A BIOLOGICAL ANALYTE MOLECULE - The invention provides a method of electrically detecting a biological analyte molecule by means of a pair of electrodes. The electrodes are arranged at a distance from one another within a sensing zone. A capture molecule, which has an affinity to the analyte molecule and which is capable of forming a complex with the analyte molecule, is immobilised on an immobilisation unit. The immobilisation unit is contacted with a solution suspected to comprise the analyte molecule. The analyte molecule is allowed to form a complex with the capture molecule. The invention also provides a probe defined by a nanoparticulate tag that comprises or consists of electrically conducting matter that is capable of chemically interacting with the analyte molecule. In the method of the invention the electrically conducting nanoparticulate tag is added. Thereby the electrically conducting nanoparticulate tag is allowed to associate to the complex formed between the capture molecule and the analyte molecule. The presence of the analyte molecule is determined based on an electrical characteristic, influenced by the electrically conducting nanoparticulate tag, of a region in the sensing zone. | 2010-08-05 |
20100194410 | SENSOR FOR SENSING AN ANALYTE AND COMBINATION OF THE SENSOR AND AN OPTICAL READER - A sensor array for detecting the content of a fluid sample comprises first and second electrodes having connections for a drive signal. The first electrode is coated with a layer of a first material having optical properties which change according to the electrical charge passing through it or the potential across it. Sensor sites are defined by islands of a second material such that the charge passing through or the potential across the second material, in response to the drive signal, varies according to the fluid sample composition. | 2010-08-05 |
20100194411 | POROUS MEDIUM ELECTRICAL CONDUCTIVITY SENSOR - There is provided a sensor for measuring a quantity, such as the salinity, of the soil solution without requiring continuous calibration. The sensor is based on a porous material which automatically fills up and saturates when the soil is rewet and drains when the soil dries out from plant uptake or from air drying, then being filled up with a solution representative of the quantity to be measured in the soil during plant growth. | 2010-08-05 |
20100194412 | SEMICONDUCTOR DEVICE FOR GENERATING INTERNAL VOLTAGE AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a comparator, an internal voltage generator, a control signal generator, and a selector. The comparator may compare a reference voltage to an internal voltage and output a comparison signal. The internal voltage generator may generate and output the internal voltage in response to the comparison signal. The control signal generator may generate a control signal. The selector may receive first and second target voltages, and select and output one of the first and second target voltages as the reference voltage in response to the control signal. | 2010-08-05 |
20100194413 | METHOD OF DETERMINING AN IMPEDANCE FUNCTION OF A LOUDSPEAKER - The invention relates to a method of determining an impedance function IF of a load LS driven by an amplifier AM, said method comprising the steps of providing a digital audio signal DAS to said amplifier AM, measuring one of either a current signal representation CSR of current provided to said load LS by said amplifier AM or a voltage signal representation VSR of voltage provided to said load LS by said amplifier AM, determining a digital signal representation DSR on the basis of said digital audio signal DAS, and determining said impedance function IF of said load LS on the basis of said digital signal representation DSR and said measured one of either said current signal representation CSR or said voltage signal representation VSR. The invention further relates to a load monitoring amplifier comprising amplification means AM comprising an amplifier input AI for receiving a digital audio signal DAS and an amplifier output AO for delivering an amplified signal to a load LS and an analog reading point AR establishing one of either a current signal representation CSR by measuring the current of said amplified signal delivered to said load LS or a voltage signal representation VSR by measuring the voltage of said amplified signal delivered to said load LS, said load monitoring amplifier further comprising a digital reading point DR for determining a digital signal representation DSR on the basis of said digital audio signal DAS and a monitoring means MM for determining an impedance function IF of said load LS on the basis of said digital signal representation DSR and said one of either said current signal representation CSR or said voltage signal representation VSR. | 2010-08-05 |
20100194414 | ELECTRO OPTICAL DETECTOR - An electro-optical detecting device is disclosed. The electro-optical detecting device includes: an upper substrate and a lower substrate; a nematic liquid crystal layer interposed between the upper substrate and the lower substrate; a transparent electrode interposed between the nematic liquid crystal layer and the upper substrate, the transparent electrode connected to a device under test (DUT) via a power supply; a polarizing plate located over the nematic liquid crystal layer; and a reflecting plate located under the nematic liquid crystal layer. A method using the electro-optical detecting device includes applying a voltage between the transparent electrode and the BUT to generate an electric field across the liquid crystal layer; illuminating the detector and capturing an image of the detector using the light reflected from the detector: and determining the DUT has some defects from the image of the detector by an abnormal electric field generated between the transparent electrode and the DUT. | 2010-08-05 |
20100194415 | PROBE NEEDLE MATERIAL, PROBE NEEDLE AND PROBE CARD EACH USING THE SAME, AND INSPECTION PROCESS - Disclosed is a probe needle material used for producing a probe needle which is used in contact with an inspection object to inspect electrical characteristics of the inspection object, comprising not less than 0.1% by volume but not more than 3.5% by volume of at least one compound selected from the group consisting of titanium boride, zirconium boride, hafnium boride, niobium boride, tantalum boride, chromium boride, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide, niobium carbide, tantalum carbide, zirconium oxide, hafnium oxide and chromium oxide and the balance of a tungsten alloy mainly consisting of tungsten. | 2010-08-05 |
20100194416 | ELECTRICAL CONNECTING APPARATUS - An embodiment of an electrical connecting apparatus comprises a probe base plate and a plurality of contacts provided with tips to be pressed against electrodes of a device under test and arranged on the underside of the probe base plate. The distance dimensions from an imaginary plane parallel to the probe base plate to the tips of the contacts are made the greater toward the center of the probe base plate. | 2010-08-05 |
20100194417 | Interface Device - In a preferred embodiment, the present invention is an interface device comprising a receiver and a test adapter. The receiver has on each outer side a groove or ridge for use in initial engagement of the test adapter with the receiver. The test adapter has an engagement member having a plurality of clips arranged such that at least one clip engages with the groove or ridge on a side of the receiver. The test adapter further has a screw mechanism for drawing the engagement in and out of the test adapter to engage and disengage the test adapter with the receiver. | 2010-08-05 |
20100194418 | Method of correcting a position of a prober - A method of correcting a position of a prober, the method including obtaining a first image of a pad, the pad having a predetermined reference contact position, contacting the prober to the pad after obtaining the first image of the pad, obtaining a second image of the pad after contacting the prober to the pad, determining an actual contact position of an actual contact mark on the pad, the actual contact mark being produced by the contacting of the prober to the pad, comparing the second image to the first image to obtain an offset data, the offset data relating the actual contact position to the reference contact position, and correcting the position of the prober by aligning the actual contact position with the reference contact position based on the offset data. | 2010-08-05 |
20100194419 | MULTI-CONTACT PROBE ASSEMBLY - A multi-contact probe assembly may include a housing, a plurality of probe members, a plurality of spring members, and a plurality of electrical connectors. The housing may comprise a plurality of shafts in a pre-determined pattern. The plurality of probe members may be partially and moveably disposed within the plurality of shafts. The plurality of spring members may be disposed within the plurality of shafts spring-loading the probe members to partially and moveably extend beyond the plurality of shafts out of the housing in the pre-determined pattern. The plurality of electrical connectors may extend into the plurality of shafts for communicating signals from electrical testing equipment to the probe members. The pre-determined pattern may be substantially identical to a pattern of contacts on a circuit board being tested by the multi-contact probe assembly. In such manner, a circuit board which has a pattern of contacts that is substantially identical to the pre-determined pattern of probe members may be tested. | 2010-08-05 |
20100194420 | CONTACTOR, PROBE CARD, AND METHOD OF MOUNTING CONTACTOR - A contactor ( | 2010-08-05 |
20100194421 | TEST EQUIPMENT AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the test pattern; a trigger generating section that supplies a trigger signal to an external instrument connected to the device under test; and a synchronization control section that outputs, to the trigger generating section, a synchronization signal instructing generation of the trigger signal, based on at least a portion of the test pattern generated by the pattern generating section. | 2010-08-05 |
20100194422 | Semiconductor integrated circuit device operating frequency determining apparatus, determining method and computer-readable information recording medium - A variation in manufacturing total costs is obtained by using an excessive loss amount caused by unnecessarily discarding elemental semiconductor integrated circuits occurring as a result of a negative result being obtained in an elemental test but a positive result obtained from a device test, and a short loss amount caused by packaging elemental semiconductor integrated circuits for semiconductor integrated circuit devices that are discarded as a result of a positive result being obtained from the elemental test but a negative result being obtained from the device test. A new operating frequency is determined by using the variation in manufacturing total costs with respect to an operating frequency. | 2010-08-05 |
20100194423 | APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE TO BE TESTED - Provided is a semiconductor testing apparatus which can perform batch test of semiconductor wafers. In the semiconductor testing apparatus, an LSI apparatus for conducting a test and which provided with a circuit and an electrode for transmitting noncontact signals, and a probe card to which a contact-type probe pin is attached are separately arranged. The semiconductor testing apparatus is provided with a recognition unit for precisely aligning the electrodes of the LSI apparatus for conducting a test, the LSI wafer to be tested and the probe card. The LSI apparatus for conducting a test and a probe pin of the probe card are mounted on a stage or a pressurizing head, and contact can be made to sandwich an LSI wafer to be tested, from both the front surface and the rear surface of the LSI wafer to be tested at the same time. | 2010-08-05 |
20100194424 | HYBRID LOAD SYSTEMS INCLUDING A DYNAMIC ELECTRONIC LOAD AND PASSIVE RESISTIVE LOAD MODULES - A hybrid load system includes a dynamic electronic load module, and a plurality of passive resistive modules coupled with the dynamic electronic load module. The hybrid system includes a control system in communication with the dynamic electronic load module and the passive resistive modules for determining when and how many of the passive resistive modules should be applied in parallel with the dynamic electronic load module for creating a desired load. | 2010-08-05 |
20100194425 | METHOD AND APPARATUS FOR TESTING AN ALTERNATING CURRENT POWER SOURCE FOR DEFIBRILLATION COMPATIBILITY - A device tests a circuit that is a source of alternating current by measuring at least one electrical parameter of the circuit to determine whether the circuit is able to provide adequate energy for defibrillation by an external defibrillator. The device may test the circuit by applying a load to the circuit, and measuring one or more electrical parameters when the load is applied to the circuit. The device may be the external defibrillator itself, or a separate testing device. In some embodiments in which an external defibrillator tests a circuit, the defibrillator modifies a value of at least one therapy delivery parameter for a subsequent delivery of one or more defibrillation pulses based on the measured electrical parameter value measured. By modifying a therapy delivery parameter, the defibrillator may deliver defibrillation pulses at an energy level that is supportable by the circuit. | 2010-08-05 |
20100194426 | METHOD OF TESTING A POWER SUPPLY CONTROLLER AND STRUCTURE THEREFOR - In one embodiment, a power supply controller is configured to operate in a test mode that facilitates measuring the value of an output signal of an error amplifier of the power supply controller. | 2010-08-05 |
20100194427 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information. | 2010-08-05 |
20100194428 | OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME - An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal. | 2010-08-05 |
20100194429 | RECONFIGURABLE IC THAT HAS SECTIONS RUNNING AT DIFFERENT RECONFIGURATION RATES - Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates. | 2010-08-05 |
20100194430 | RECONFIGURABLE LOGIC CELL MADE UP OF DOUBLE-GATE MOSFET TRANSISTORS - Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions with which logical signals provided on the n inputs (A,B) may be processed. The cell contains, between the ground and the output (F) of the cell, at least one first branch including n dual gate N-type MOSFET transistors (M | 2010-08-05 |
20100194431 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Devices - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 2010-08-05 |
20100194432 | DEVICE FOR TRANSFORMING INPUT IN OUTPUT SIGNALS WITH DIFFERENT VOLTAGE RANGES - Arrangement for accepting an input signal in a first voltage range and producing an output signal in a second voltage range. A transition detection circuit ( | 2010-08-05 |
20100194433 | LEVEL SHIFTER AND SEMICONDUCTOR DEVICE HAVING OFF-CHIP DRIVER - Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate. | 2010-08-05 |
20100194434 | SYSTEMS AND METHODS OF INTEGRATED CIRCUIT CLOCKING - Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit. | 2010-08-05 |
20100194435 | CLOCK GUIDED LOGIC WITH REDUCED SWITCHING - Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path. | 2010-08-05 |
20100194436 | VERIFICATION SUPPORT SYSTEM AND METHOD - A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock. The system includes an identification unit to identify whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of logic gates of the receiver clock domain to combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic. | 2010-08-05 |
20100194437 | Implementing CML Multiplexer Load Balancing - A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair. | 2010-08-05 |
20100194438 | SEMICONDUCTOR DEVICE - It is intended to provide a semiconductor device which comprises an SGT-based, highly-integrated, high-speed, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A semiconductor device of the present invention comprises a CMOS inverter cascade circuit having at least two-stage CMOS inverter, wherein: a first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column; and a second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column. An output terminal line is connected to an input terminal line, wherein the output terminal line is arranged to interconnect a drain diffusion layer of each of the two SGTS at respective ones of the intersection of the 1st row and the intersection of the 2nd row and the 1st column and the 1st column, and a drain diffusion layer of the SGT at the intersection of the 1st row and the 2nd column, through an island-shaped semiconductor lower layer, and the an input terminal line is arranged to interconnect a gate of each of the two SGTs at respective ones of the intersection of the 1st row and the 3rd column and the intersection of the 2nd row and the 3rd column, and a gate of the SGT at and the intersecting of the 2nd row and 2nd column. | 2010-08-05 |
20100194439 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal. | 2010-08-05 |
20100194440 | Phase Error De-Glitching Circuit and Method of Operating - A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal. | 2010-08-05 |
20100194441 | LEAKAGE COMPENSATION FOR SAMPLE AND HOLD DEVICES - A sample and hold circuit with leakage compensation is disclosed. An example sample and hold circuit includes a first switch coupled to sample and hold an input signal value in a first capacitor coupled to the first switch in response to a sample signal. A second switch through which a second leakage current flows to a second capacitor coupled to the second switch is also included. The second leakage current through the second switch to the second capacitor is substantially equal to a first leakage current through the first switch to the first capacitor. An offset circuit that is coupled to the first and second capacitors is also included to produce a compensated sampled value in response to a difference between a quantity representing the held input signal value and charge accumulated in the first capacitor in response to the first leakage current from a quantity representing charge accumulated in the second capacitor in response to the second leakage current. | 2010-08-05 |
20100194442 | Method And System For Monitoring Silicon Process Properties For Power And Performance Optimization - Signal processing within an integrated circuit (IC) may be monitored by a silicon process monitor, where one or more inputs to the IC may be controlled. The controlled input may comprise a variable frequency signal, a variable voltage level, an analog signal and/or a known input with a corresponding expected output. The controlled input may drive a plurality of components on the IC. The IC output signal variations may be due to temperature and/or silicon manufacturing processes variations and may affect performance and/or power consumption. IC output signal variations may be detected based on the controlled inputs. Controlled inputs may be adjusted based on the detected output variations and may be adjusted to modify the output. The variations may be detected based on relative frequency between output and the controlled input. In addition, logical operations and/or counters may be utilized to detect variations. | 2010-08-05 |
20100194443 | dB-LINEAR VOLTAGE-TO-CURRENT CONVERTER - A dB-linear voltage-to-current (V/I) converter that is amenable to implementation in CMOS technology. In a representative embodiment, the dB-linear V/I converter has a voltage scaler, a current multiplier, and an exponential current converter serially connected to one another. The voltage scaler supplies an input current to the current multiplier based on an input voltage. The current multiplier multiplies the input current and a current proportional to absolute temperature and supplies the resulting current to the exponential current converter. The exponential current converter has a differential MOSFET pair operating in a sub-threshold mode and generating an output current that is proportional to a temperature-independent, exponential function of the input voltage. | 2010-08-05 |
20100194444 | REDUCTION OF SPURIOUS FREQUENCY COMPONENTS IN DIRECT DIGITAL SYNTHESIS - In an embodiment, an apparatus, comprises a phase accumulator configured to provide an output comprising a truncated phase word representative of an instantaneous phase; a multiplexer configured to provide an output representative of a phase rotation, wherein the output representative of the phase rotation is randomly selected from a group of phase rotation representation outputs; an adder configured to receive the output from the phase accumulator and the output from the multiplexer, wherein the adder provides an output representative of the instantaneous phase rotated by the phase rotation; a lookup table configured to receive the output representative of the instantaneous phase and to provide an amplitude output; and a rotator configured to receive the amplitude output and substantially to cancel the phase rotation. Other embodiments do not comprise a rotator. A method is also described. | 2010-08-05 |
20100194445 | POWER SUPPLY CONTROLLER WITH INPUT VOLTAGE COMPENSATION FOR EFFICIENCY AND MAXIMUM POWER OUTPUT - A controller for a power supply includes a logic block and a time-to-frequency converter. The logic block is to generate a drive signal in response to a clock signal. The drive signal is to be coupled to control switching of a power switch of the power supply to regulate an output of the power supply. The time-to-frequency converter is coupled to the logic block and generates the clock signal having a frequency responsive to a time period of the drive signal. | 2010-08-05 |
20100194446 | SOURCE DRIVER, DELAY CELL IMPLEMENTED IN THE SOURCE DRIVER, AND CALIBRATION METHOD FOR CALIBRATING A DELAY TIME THEREOF - A delay cell for delaying an input data signal to generate an output data signal includes a logic circuit and a bias current generator. The logic circuit is used for processing the input data signal to generate the output data signal. The bias current generator is coupled to the logic circuit for providing a first bias current to the logic circuit to control a delay time of the delay cell based on a process corner at which the delay cell is manufactured in a wafer. The bias current generator includes a first transistor coupled between a first power supply and the logic circuit for steering the first bias current of the logic circuit, wherein the first transistor is biased by a first bias voltage. | 2010-08-05 |
20100194447 | ZERO INPUT BIAS CURRENT, AUTO-ZEROED BUFFER FOR A SAMPLE AND HOLD CIRCUIT - An auto-zeroing, high impedance buffer for a sample and hold module that draws substantially no current from the input and has substantially no offset voltage at the output is discussed. During a hold mode, the offset voltage of an op-amp is accumulated on a capacitor. When the sample operation ensues the input signal is directed to the op-amp input via the capacitor where the circuitry is arranged so that the offset on the capacitor cancels the offset voltage of the op-amp. A second circuit may be fashioned and input to a sample and hold circuit for full differential operation. | 2010-08-05 |
20100194448 | Predriver and output driver circuit using the same - An output driver circuit includes a predriver control signal generation unit receiving a pull-up code signal, a pull-down code signal, a predriver selection signal and a read control signal and generating a pull-up control signal and a pull-down control signal; a predriver driven in response to the pull-up control signal and the pull-down control signal and receiving an internal data to drive a pull-up driving signal and a pull-down driving signal; and a driver receiving the pull-up driving signal and the pull-down driving signal and driving an output data outputted to a DQ pad, wherein the pull-up control signal and the pull-down control signal are enabled when the predriver is selected in a read operation period and a preset combination of the code signals is inputted. | 2010-08-05 |
20100194449 | Circuitry and Method for Reducing Second and Third-Order Nonlinearities - An electronic circuit ( | 2010-08-05 |
20100194450 | THIN-FILM TRANSISTOR CIRCUIT, DRIVING METHOD THEREOF, AND LIGHT-EMITTING DISPLAY APPARATUS - In a light-emitting display apparatus including a plurality of pixels each including a light-emitting element and a driving circuit of the light-emitting element, and the driving circuit includes a plurality of thin-film transistors connected in parallel, a threshold voltage of the thin-film transistor reversibly changes according to a voltage applied between a gate and a source or between the gate and a drain of each of the thin-film transistors, by selecting and switching the plurality of thin-film transistors TFT | 2010-08-05 |
20100194451 | METHOD OF CONTROLLING AN IGBT AND A GATE DRIVER - A method is disclosed for controlling an IGBT component and a gate driver. An exemplary method includes producing, with two separate driver circuits, a gate voltage for controlling the IGBT component, the outputs of the driver circuits being connected to free ends of a series connection of resistive components. A location, such as a midpoint between the series connection, forms the gate voltage. | 2010-08-05 |
20100194452 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes: an internal circuit; a ground terminal; a first terminal that is provided with a first signal that becomes to be a ground level during at least a portion of a period in which the internal circuit is operating; a detection circuit that compares a voltage on the first terminal and a voltage on the ground terminal, thereby detecting an open state of the ground terminal; and a setting circuit that sets the internal circuit to a reset state or a disabled state when the open state of the ground terminal is detected by the detection circuit. | 2010-08-05 |
20100194453 | SEMICONDUCTOR DEVICE - A device includes a voltage converter circuit that includes an output node, a voltage drop circuit, and a first transistor. The first transistor is electrically coupled between the output node and the voltage drop circuit. | 2010-08-05 |
20100194454 | Phase adjusting apparatus and camera - A phase adjusting apparatus includes a comparison code generating section, a calculating section, and a delay section. The comparison code generating section individually generates a first comparison code having a phase of a head code advanced and a second comparison code having the phase of the head code delayed, the head code being included in serial transfer data. The calculating section acquires a direction of adjustment of a phase of the serial transfer data using a comparison result of the head code and the first comparison code and a comparison result of the head code and the second comparison code. The delay section adjusts a delay amount of the serial transfer data based on the direction of adjustment of the phase. | 2010-08-05 |
20100194455 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS - A semiconductor integrated circuit apparatus includes a main clock generation circuit that generates a main clock signal, a plurality of function blocks, a clock generation circuit in the plurality of function blocks, and a phase locked loop circuit in the clock generation circuit. The phase locked loop circuit generates a clock signal in the plurality of function blocks, using the main clock signal from the main clock generation circuit. | 2010-08-05 |
20100194456 | Delay locked loop, electronic device including the same, and method of operating the same - A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time. | 2010-08-05 |
20100194457 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block. | 2010-08-05 |
20100194458 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit. | 2010-08-05 |
20100194459 | CIRCUIT AND DESIGN STRUCTURE FOR SYNCHRONIZING MULTIPLE DIGITAL SIGNALS - Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path. | 2010-08-05 |
20100194460 | WAVEFORM GENERATOR - Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then. | 2010-08-05 |
20100194461 | EXTENDED RANGE RMS-DC CONVERTER - Described herein is technology for, among other things, reducing offset errors in RMS-to-DC converters. The technology involves generating first and second feedback signals with first and second feedback paths respectively. A multiplier is then employed to receive first and second signals and provide a third signal based on multiplying the first signal and the second signal. The first signal is based on an input signal and the first feedback signal, and the second signal is based on the input signal and the second feedback signal. A chopper is then employed to receive an output signal, which is based on the third signal, and a chopping signal, and in turn provide a fourth signal based on multiplying the output signal with the chopping signal. As a consequence, the fourth signal represents the output signal shifted to a frequency different than that of low-frequency noise components of the first and second signals. | 2010-08-05 |
20100194462 | Current Control Circuits - Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit. | 2010-08-05 |
20100194463 | SWITCH CONTROL DEVICE AND SWITCH CONTROL METHOD - The present invention relates to a switch control device and a switch control method. The present invention controls a switching operation of a power switch that controls output power of a switching mode power supply (SMPS). The present invention generates an operation current corresponding to an input voltage of the SMPS and counts a compensation period in which a power supply voltage generated by the operation current increases from a predetermined counter low-reference voltage to a predetermined counter high-reference voltage. The present invention generates a compensation feedback current depending on the count result, generates a total feedback current by summing a main feedback current having a predetermined value and the compensation feedback current, and generates a power limit current of which a maximum value increases and decreases depending on the total feedback current. Turn-off of the power switch is determined by comparing the current flowing on the power switch with the power limit current. | 2010-08-05 |
20100194464 | Method and Circuit for Protecting a MOSFET - An integrated circuit includes a transistor. During operation a current slew-rate is determined based on a duration the transistor has been conducting and a current flowing through the transistor. The transistor can then be controlled to switch to its non-conducting state using the slew-rate. | 2010-08-05 |
20100194465 | TEMPERATURE COMPENSATED CURRENT SOURCE AND METHOD THEREFOR - In one embodiment, a temperature compensated current source includes a depletion mode transistor coupled in series with an active semiconductor device that adjust the depletion mode transistor to minimize variations in the current due to temperature changes. | 2010-08-05 |
20100194466 | QUANTUM BIT VARIABLE COUPLING METHOD, QUANTUM COMPUTING CIRCUIT USING THE METHOD, AND VARIABLE COUPLER - There is provided a quantum computing circuit comprising first and second superconductive magnetic flux quantum bit elements ( | 2010-08-05 |
20100194467 | Devices, Methods, and Systems With MOS-Gated Trench-to-Trench Lateral Current Flow - A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained. | 2010-08-05 |
20100194468 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, COMMUNICATION DEVICE, INFORMATION REPRODUCING DEVICE, IMAGE DISPLAY DEVICE, ELECTRONIC DEVICE, ELECTRONIC CONTROL DEVICE, AND MOBILE BODY - In order to suppress an instantaneous carrying current (surge current) and power supply noise caused by the instantaneous carrying current (the surge current), the power supply cutoff structure of a semiconductor integrated circuit device comprises a switching circuit for controlling a power supply to a controlled circuit. The switching circuit includes a plurality of transistors each having a different current capability. The transistors are sequentially provided with a certain regularity, including from a low current capability transistor up to a high current capability transistor. | 2010-08-05 |
20100194469 | Power Monitoring for Optimizing Operation of a Circuit - An example method for optimizing power consumption of digital circuits using dynamic voltage and threshold scaling (DVTS) is provided. A propagation delay of a signal through a portion of the circuit is determined and if the propagation delay does not meet a specified delay requirement, then a supply voltage and/or threshold voltage of the circuit is adjusted. Subsequently, a power consumption level of the circuit is determined and compared to previous power consumption levels. The supply and/or threshold voltage of the circuit can be readjusted to enable the circuit to meet specified power consumption requirements and the specified delay requirement, for example. | 2010-08-05 |
20100194470 | Integrated Circuit Package - An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die. | 2010-08-05 |