31st week of 2009 patent applcation highlights part 12 |
Patent application number | Title | Published |
20090189117 | Nitrates - A method of producing anhydrous calcium nitrate, anhydrous magnesium nitrate or mixture thereof involves removing water from a solution of calcium nitrate, magnesium nitrate or mixture thereof in a pulse combustion drier. The invention also provides a mixture of anhydrous calcium nitrate, anhydrous magnesium nitrate and the individual anhydrous nitrate salts in a sealed container. | 2009-07-30 |
20090189118 | Liquid Maleated Butyl Rubber - The present invention relates to a grafted liquid polymer comprising a polymer of a C | 2009-07-30 |
20090189119 | Use of metal complex compounds comprising pyridine pyrimidine or s-triazine derived ligands as catalysts for oxidations with organic peroxy acids and/or precursors of organic peroxy acids and h202 - The invention accordingly relates to the use as catalysts of at least one metal complex of formula (1) [L | 2009-07-30 |
20090189120 | COMPOUND, LIQUID CRYSTAL COMPOSITION, AND ANISOTROPIC MATERIAL - A compound represented by formula (I) below: | 2009-07-30 |
20090189121 | RARE EARTH OXYSULFIDE SCINTILLATOR AND METHODS FOR PRODUCING SAME - A method of producing a rare earth oxysulfide scintillating ceramic body includes heat treatment to form a consolidated body, followed by gas hot isostatic pressing (GHIPing). A powder is first provided having the general formula (M | 2009-07-30 |
20090189122 | METHOD FOR PREPARING OXIDE NANO PHOSPHORS - Disclosed is a method for preparing an oxide nano phosphor. A metal precursor solution is prepared. The metal precursor solution is impregnated into a porous polymer material. A heat treatment is performed on the porous polymer material having the metal precursor solution impregnated therein. The heat treatment is performed by heating the porous polymer material having the metal precursor impregnated therein up to a temperature of higher than 500° C. solution at a temperature elevating rate of higher than 100° C. per minute. | 2009-07-30 |
20090189123 | METHOD AND APPARATUS FOR A MULTI PURPOSE DATA AND ENGINEERING SYSTEM 205 - The present invention relates to a method of a manufacturing facility fitted and equipped onboard a marine vessel, the vessel first taking in seawater to fill the vessel ballast tanks using the vessel's sea chests, ensuring a reasonable stability factor to allow for continuous and safe operation of the manufacturing facility. | 2009-07-30 |
20090189124 | TRANSPARENT CONDUCTORS AND METHODS FOR FABRICATING TRANSPARENT CONDUCTORS - Transparent conductors and methods for fabricating transparent conductors are provided. In one exemplary embodiment, a transparent conductor comprises a substrate having a surface and a transparent conductive coating disposed on the surface of the substrate. The transparent conductive coating has a plurality of conductive components of at least one type and an aliphatic isocyanate-based polyurethane component. | 2009-07-30 |
20090189125 | ELECTRICALLY CONDUCTIVE POLYMER COMPOSITES - This invention relates to a process for preparing an electrically conductive composite comprising the weight ratio of carbon to polymer of greater than 0.11. The process comprises the steps of mixing non-predispersed carbon with an emulsion comprising a polymer in a liquid solvent to obtain a dispersion of the carbon within the polymer matrix, wherein the weight ratio of carbon to polymer is greater than 0.11; and removing the liquid solvent from the dispersion. The invention also relates to conductive polymer composites prepared by the process. | 2009-07-30 |
20090189126 | Glass Frits - Glass frits, conductive inks and articles having conductive inks applied thereto are described. According to one or more embodiments, glass frits with no intentionally added lead comprise TeO | 2009-07-30 |
20090189127 | Optical resin lens and production method for optical resin material - An optical resin lens characterized in comprising a polymer prepared employing a production method including a process which polymerizes olefin employing titanium halide and a catalyst comprised of the organic aluminum represented by Formula R | 2009-07-30 |
20090189128 | COLOR FILTER INK, COLOR FILTER INK SET, COLOR FILTER, IMAGE DISPLAY DEVICE, AND ELECTRONIC DEVICE - A color filter ink is adapted to be used to manufacture a color filter by an inkjet method. The color filter ink includes a pigment, a dispersing agent and a liquid medium. The pigment includes a halogenated phthalocyanine zinc complex and a pigment derivative represented by a prescribed chemical formula. The dispersing agent disperses the pigment. The liquid medium, in which the pigment is dispersed, includes at least a first liquid and a second liquid different than the first liquid. A boiling point at atmospheric pressure of the first liquid is 180 to 290° C. A content ratio of the second liquid in the color filter ink is 5 to 20 wt %. A relationship |SP (X)−SP (Y)|≦0.8 is satisfied, wherein a value SP (X) indicates a solubility parameter for the dispersing agent, and a value SP (Y) indicates a solubility parameter for the second liquid. | 2009-07-30 |
20090189129 | CONDUCTIVE EMULSION FOR PREPARING SURFACE FOR POWDER COATING - An emulsion for preparing a low-conductivity surface for powder coating, the emulsion including an emulsified organofunctional silane solution. A pre-powder coating emulsion provides a surface with conductivity. A non-conductive object having applied to an exterior surface of the object the emulsion including an emulsified organofunctional silane solution. | 2009-07-30 |
20090189130 | MODULAR VEHICLE RAMP SYSTEM - A modular vehicle ramp system is provided for elevating all four wheels of a vehicle off of the ground to allow a user easy access beneath the elevated vehicle. The components are modular allowing the ramp system to be employed in several different reconfigurable arrangements. A first embodiment provides one wheel support and one ramp that releasably engages with the wheel support. In another embodiment, at least two wheel supports are employed with two corresponding ramps releasably engaged therewith. Finally in another embodiment, two bridge sections extend between two wheel supports positioned at the front and two wheel supports positioned at the rear. Two ramps are releasably engaged with either the two forward or rear wheel supports such that a car can be driven up the ramps and over the bridge sections such that the four vehicle wheels are supported on the four wheel supports. | 2009-07-30 |
20090189131 | Hoisting device of a rope section having a lifting element with two shells assembled by sliding - A hoisting device of a section of a rope for a mechanical ski-lift installation comprises on the one hand a lifting element designed to be positioned pressing against the rope and on the other hand means for moving the lifting element in a first direction. The lifting element is formed by a sleeve having a main axis oriented in a second direction perpendicular to the first direction, designed to be positioned around the rope section. The sleeve comprises a top shell having connection means connecting with the means for moving, a bottom shell having a support dish designed to be positioned pressing underneath said rope section, the two shells comprising complementary guiding elements for assembly by sliding in the second direction, and securing means disabling sliding between the two shells after assembly. | 2009-07-30 |
20090189132 | Pallet Truck with Extending Forks - The invention relates to a pallet truck for substantially horizontal displacement of goods, comprising: a displaceable frame; at least one elongate fork connected to the frame for carrying the goods, wherein the fork is provided with a support wheel at a distance from the frame, and wherein the fork can be selectively extended in longitudinal direction via an extending mechanism. The invention also relates to a system for extending a carrying part of a pallet truck, comprising: at least one elongate fork connectable to a frame for carrying the goods, wherein the fork is provided with a support wheel at a distance from the frame, and wherein the fork can be selectively extended in longitudinal direction via an extending mechanism. The invention finally relates to a method for use and/or control of a pallet truck and/or system. | 2009-07-30 |
20090189133 | Hitch Installation Hoist - A portable hoist assembly is provided for lifting a hitch to be installed on the underside of a vehicle platform. The hitch has a hitch ball hole and the vehicle platform has a hole to be aligned with the hitch ball hole when the hitch is installed. The hoist assembly includes a hoist frame and a winch for paying out and drawing in a cable. The winch is supported by the frame above the vehicle platform hole. An elongated member is attached to the cable. The elongated member can be oriented in a first position wherein it can pass through the vehicle platform hole and the hitch ball hole. Also, the elongated member can be oriented in a second position wherein it cannot pass through the hitch ball hole. The elongated member can be lowered through the vehicle platform hole and the hitch ball hole in the first orientation and can secure the cable to the hitch in the second orientation. | 2009-07-30 |
20090189134 | Perceived Jack Position Drift Compensation Method and Apparatus - A controller commands a jack drive to extend and retract a jack leg relative to a jack base along a stroke having retraction and extension limits. The controller updates a perceived present leg position value in response to position change signals from a position change sensor. The controller occasionally applies compensation factors to the perceived present leg position value in the extension direction. The controller resets the perceived present leg position value whenever the jack leg reaches the retraction limit. | 2009-07-30 |
20090189135 | VEHICLE SUPPORT STAND - A motorcycle support stand includes a base ( | 2009-07-30 |
20090189136 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug and on the interlayer insulator, a phase-change material layer provided on the electric conductive material layer, and an upper-electrode plug provided on the phase-change material layer. The bottom-electrode plug and the upper-electrode plug which configure the phase-change memory device are provided at respective different positions in a plane of the semiconductor substrate. | 2009-07-30 |
20090189137 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved. | 2009-07-30 |
20090189138 | FILL-IN ETCHING FREE PORE DEVICE - A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed. | 2009-07-30 |
20090189139 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 2009-07-30 |
20090189140 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is formed on the first electrical contact. A second electrical contact is formed on the second dielectric layer, wherein the second electrical contact comprises an outstanding terminal. An opening passes through the second electrical contact, the second dielectric layer, and the first electrical contact. A phase-change material occupies at least one portion of the opening. A third dielectric layer is formed on and covers the second electrical contact, exposing a top surface of outstanding terminal. A top electrode is formed on the third dielectric layer, contacting the outstanding terminal. | 2009-07-30 |
20090189141 | Phase change memory device and method of forming the same - A phase change memory device and a method of forming the same include a conductive pattern formed on a substrate. A lower electrode contact is disposed on the conductive pattern. The phase change pattern is disposed on the lower electrode contact. An upper electrode is disposed on the phase change pattern. An area of an upper surface of the lower electrode contact is smaller than an area of a lower surface of the lower electrode contact. | 2009-07-30 |
20090189142 | Phase-Change Memory - A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact. | 2009-07-30 |
20090189143 | Nanotube array electronic and opto-electronic devices - Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The discussed electronic and photonic devices and circuits rely on the nanotube arrays grown on a variety of substrates, such as glass or Si wafer. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for a large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on Si-wafers, the CNT-based devices can be combined with the Si circuit elements, thus producing hybrid Si-CNT devices and circuits. | 2009-07-30 |
20090189144 | Device For Absorbing Or Emitting Light And Methods Of Making The Same - A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of nanowires established between the second and third layers. The second plurality of nanowires is formed of a second semiconductor material having a bandgap that is the same as or different from a bandgap of the first semiconductor material. | 2009-07-30 |
20090189145 | Photodetectors, Photovoltaic Devices And Methods Of Making The Same - A photodetector includes a first layer, a second layer and a plurality of nanowires established between the first and second layers. At least some of the plurality of nanowires have a bandgap that is different from a bandgap of at least some other of the plurality of nanowires. | 2009-07-30 |
20090189146 | Multifinger Carbon Nanotube Field-Effect Transistor - A multifinger carbon nanotube field-effect transistor (CNT FET) is provided in which a plurality of nonotube top gated FETs are combined in a finger geometry along the length of a single carbon nanotube, an aligned array of nanotubes, or a random array of nanotubes. Each of the individual FETs are arranged such that there is no geometrical overlap between the gate and drain finger electrodes over the single carbon nanotube so as to minimize the Miller capacitance (Cgd) between the gate and drain finger electrodes. A low-K dielectric may be used to separate the source and gate electrodes in the multifinger CNT FET so as t further minimize the Miller capacitance between the source and gate electrodes. | 2009-07-30 |
20090189147 | Organic transistor comprising a self-aligning gate electrode, and method for the production thereof - An unpatterned semiconductor layer is applied to a substrate for the production of an organic transistor. An insulator is arranged on the semiconductor layer wherein at least the insulator layer is patterned, so that at least source and drain electrode layers can be formed subsequently. The source and drain electrode layers are formed after the patterning of at least the insulator layer to ensures that an overlap of both a gate electrode layer and the source and drain electrode layers is essentially avoided. | 2009-07-30 |
20090189148 | TRANSISTOR ELEMENT, DISPLAY DEVICE AND THESE MANUFACTURING METHODS - A transistor element that a transistor using an organic semiconductor layer on a substrate, an insulating film between layers contacting the organic semiconductor layer and an upper electrode electrically contacting the transistor via a through hole provided in the insulating film between layers are layered, wherein the insulating film between layers comprises a mixture of organic materials and particles. | 2009-07-30 |
20090189149 | Composition for producing insulator and organic insulator using the same - Disclosed herein is a composition for producing an insulator. More specifically, the composition comprises a silane-based organic-inorganic hybrid material containing one or more multiple bonds, an acrylic organic crosslinking agent and a silane-based crosslinking agent having six or more alkoxy groups. Also disclosed herein is an organic insulator produced using the insulator composition. The organic insulator is highly crosslinked to facilitate the fabrication of an organic thin film transistor in terms of processing. | 2009-07-30 |
20090189150 | Organic semiconducting copolymer and organic electronic device including the same - An organic semiconducting copolymer according to example embodiments may be represented by Formula 1 below: | 2009-07-30 |
20090189151 | METHOD FOR SEPARATING A NON-EMISSION REGION FROM A LIGHT EMISSION REGION WITHIN AN ORGANIC LIGHT EMITTING DIODE (OLED) - The present invention relates to a method for separating at least one non-emission region ( | 2009-07-30 |
20090189152 | FERROELECTRIC MEMORY DEVICE - Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode. | 2009-07-30 |
20090189153 | FIELD-EFFECT TRANSISTOR - Disclosed herein is a field-effect transistor comprising a channel comprised of an oxide semiconductor material including In and Zn. The atomic compositional ratio expressed by In/(In+Zn) is not less than 35 atomic % and not more than 55 atomic %. Ga is not included in the oxide semiconductor material or the atomic compositional ratio expressed by Ga/(In+Zn+Ga) is set to be 30 atomic % or lower when Ga is included therein. The transistor has improved S-value and field-effect mobility. | 2009-07-30 |
20090189154 | ZnO NANOSTRUCTURE-BASED LIGHT EMITTING DEVICE - A Light Emitting Diode (LED) formed on a substrate of a material selected from at least one of a semiconductor, an insulator and a metal; at least one semiconductor film layer of ZnO or GaN deposited on the substrate; a nanotips array of ZnO or its ternary compound, the array being grown either directly or indirectly on a surface of at least one semiconductor film layer; at least one transparent and conductive oxide (TCO) layer deposited on at least one semiconductor film layer; and a semiconductor p-n junction under a forward bias voltage. | 2009-07-30 |
20090189155 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film. | 2009-07-30 |
20090189156 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film. | 2009-07-30 |
20090189157 | Device for measuring or inspecting substrates of the semiconductor industry - A device for measuring or inspecting substrates of the semiconductor industry, including a base frame and a module detachably mounted thereon via a module frame, wherein the module frame is detachably connected to the base frame via at least two self-aligning coupling elements and at least one alignment element, wherein the base frame and the module frame are in exactly defined spatial alignment with each other, when the module frame is detachably connected to the base frame. | 2009-07-30 |
20090189158 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals. On the second surface of the wiring board, a semiconductor chip having electrode pads is mounted. The electrode pads of the semiconductor chip and the internal connection terminals of the wiring board are electrically connected via connecting members. The external connection terminals are arranged along two opposite outer sides of the wiring board and each have a rectangular shape elongated in a direction toward the outer side. | 2009-07-30 |
20090189159 | GETTERING LAYER ON SUBSTRATE - Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a device region is formed in the device layer having a depth that maintains a distance in the device layer between the gettering layer and the device region. | 2009-07-30 |
20090189160 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE TFT - A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT, the TFT including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer and crystallized using a metal catalyst, and source and drain electrodes disposed on the semiconductor layer and electrically connected to source and drain regions of the semiconductor layer. A second metal is diffused into a surface region of the semiconductor layer, to getter the metal catalyst from a channel region of the semiconductor layer. The second metal can have a lower diffusion coefficient in silicon than the metal catalyst. | 2009-07-30 |
20090189161 | Light Emitting Device - While suppressing the frequency of a signal line driver circuit, a blur of a moving image of a light-emitting device using a light-emitting transistor can be prevented, without reducing a frame frequency. A switching element is provided in a path of a current which flows between a source and a drain of a light-emitting transistor, and the light-emitting transistor is made not to emit light by turning off the switching element, whereby pseudo-impulse driving is performed. Switching of the switching element can be controlled by a scan line driver circuit. In a specific structural example, the light-emitting device includes, in a pixel, a light-emitting transistor, a first switching element which controls supply of a potential of a video signal to a gate of the light-emitting transistor, and a second switching element which controls a current which flows between a source and a drain of the light-emitting transistor. | 2009-07-30 |
20090189162 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode display device to display a main image and a sub-image, such as background, illumination, or the like, without additional processes or a reduction in the resolution of the image, and a method of fabricating the same, the organic light emitting diode display device including: a substrate; a thin film transistor disposed on the substrate, including a semiconductor layer, a source electrode, a drain electrode, a gate insulating layer, and a gate electrode; an insulating layer disposed on the thin film transistor; a first lower electrode disposed on the insulating layer, electrically connected to the source electrode and the drain electrode of the thin film transistor; an auxiliary lower electrode disposed on the insulating layer, spaced apart from the first lower electrode; a first organic layer disposed on the first lower electrode, including at least one emission layer; a second organic layer disposed on the auxiliary lower electrode, including at least one emission layer; and an upper electrode disposed on the first organic layer and the second organic layer. | 2009-07-30 |
20090189163 | THIN FILM TRANSISTOR ARRAY SUBSTRATE - A TFT array substrate includes a substrate, a patterned first metallic layer, a patterned stack layer, a patterned dielectric layer, a patterned transparent conductive layer, and a patterned third metallic layer. Elements of each TFT in the TFT array substrate are arranged vertically, so that the TFT array substrate has relatively small fabrication area and is operable with a high conducting current. Further, the storage capacitance can be enhanced by enclosing or sandwiching the second metallic layer with the common lines and the transparent electrodes. In such a way, pixel flashing caused by those coupled signals can be reduced, thus promoting displaying quality thereof. | 2009-07-30 |
20090189164 | UNIFORM LARGE-GRAINED AND GRAIN BOUNDARY LOCATION MANIPULATED POLYCRYSTALLINE THIN FILM SEMICONDUCTORS FORMED USING SEQUENTIAL LATERAL SOLIDIFICATION AND DEVICES FORMED THEREON - Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated laser pulse in the sequence in a predetermined plane, masking portions of each homoginized fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof corresponding to each fluence controlled patterned beamlet pulse in the sequence of pulses of patterned beamlets, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film. | 2009-07-30 |
20090189165 | LIGHT-EMITTING DIODE LIGHT SOURCE - An LED light source comprises a lower substrate having an upper surface which is formed with a groove and covered with an insulating layer in an area outside the groove, wherein the insulating layer is partially covered with a metal layer; an upper substrate disposed on a top of the insulating layer and formed with an opening in an area corresponding to the groove; a plurality of sub-substrates disposed on an inner bottom portion of the groove, wherein each said sub-substrate has a surface covered with a circuit layer, adjacent said sub-substrates are electrically connected to each other at respective adjacent ends thereof by a first metal lead, and each said sub-substrate is provided thereon with a plurality of LED chips, in which each said LED chip is connected by a second metal lead to a corresponding electrical connection point; and a light-transmitting colloid filled in the groove and the opening. The plurality of LED chips are thus integrally packaged in the groove to form the LED light source, which can be easily manufactured while having a small volume and providing high brightness. | 2009-07-30 |
20090189166 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF LIGHT EMITTING CELLS AND METHOD OF FABRICATING THE SAME - Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source. In addition, since the semi-insulating buffer layer is employed, it is possible to prevent an increase in a leakage current through the thermally conductive substrate and between the light emitting cells. | 2009-07-30 |
20090189167 | LIGHT EMITTING DEVICE WITH HIGH LIGHT EXTRACTION EFFICIENCY - An exemplary solid-state light emitting device includes a substrate, a light emitting structure, a first electrode and a second electrode have opposite polarities with each other. The light emitting structure includes a first-type semiconductor layer, a second-type semiconductor layer and an active layer between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode electrically is connected with the first-type semiconductor layer. The first electrode includes a first contact pad and a current induced electrode spaced apart and insulated from each other. The second electrode has an opposite polarity with respect to the first electrode. The second electrode includes a transparent conductive layer formed on and electrically connected with the second-type semiconductor layer and a metallic conductive layer formed on the transparent conductive layer and in electrical contact therewith. | 2009-07-30 |
20090189168 | White Light Emitting Device - A white light emitting device is provided, which includes a light emitting element that emits a first light having a wavelength between 300 nm and 410 nm; and a fluorescent layer positioned over the light emitting element. The fluorescent layer includes a fluorescent whitening agent capable of absorbing at least a portion of the first light, and subsequently emitting a second light having a wavelength between 420 nm and 510 nm; and a photoluminescent material capable of absorbing at least a portion of the first light and at least a portion of the second light, and subsequently emitting a third light having a wavelength longer than wavelengths of the first light and the second light. | 2009-07-30 |
20090189169 | Light emitting diode lamp - A light emitting diode lamp includes a heat sink, a socket, a light emitting module, a holder and a lens. The socket and the holder are respectively positioned opposite sides of the heat sink. The light emitting module is combined with the heat sink and has a light emitting diode unit. The lens is mounted on the light emitting diode unit and combined inside the holder. The heat sink includes a substrate and a plurality of heat dissipating fins. The substrate has a plurality of extending arms in a manner that a slot is formed between two neighboring extending arms. A plurality of heat dissipating fins is inserted into the corresponding slots. One of opposite sidewall surfaces of each extending arm is against one of opposite surfaces of each heat dissipating fin. Thereby, there is no need of producing a heat sink by soldering. | 2009-07-30 |
20090189170 | Light emitting diode - A light emitting diode includes a casing, comprising a concave accommodation space; a lead frame, disposed in the casing, wherein the lead frame has at least two individual leads which extend into the accommodation space; a light emitting chip, disposed in the accommodation space and electrically connected to the leads; and an encapsulating material, inside the accommodation space. The light emitting diode emits light along an optical axis. The ratio of a first tilt angle between the first reflecting wall and the optical axis, and a second tilt angle to a second tilt angle between the second reflecting wall and the optical axis is no more than 4. | 2009-07-30 |
20090189171 | Light emitting diode package - An LED package includes a housing, a substrate, a pad frame and an LED chip. The housing includes a plastic material, and has a recess with an opening at a top of the housing. The substrate includes substantially the same material with the housing. The pad frame includes conductive material, and is inserted on the substrate, and is fixed between the housing and the substrate. The LED chip is mounted on the pad frame and is disposed at a center of the recess. The housing is protruded and extended to a lower portion of the LED chip. Thicknesses of the housing's sidewalls facing to each other through the recess are substantially the same with each other. | 2009-07-30 |
20090189172 | Light emitting diode with higher illumination efficiency - A light emitting diode (LED) with higher illumination efficiency is revealed. The LED includes a LED chip and an optical layer arranged on the bottom of the LED chip. The optical layer is a light-guiding layer, a light reflective layer or an energy-conversion layer that increases light emitting efficiency of the LED. Furthermore, a rough layer is disposed between the LED chip and the optical layer so as to increase surface area of the LED chip. Thus light emitted from the LED chip enters the optical layer more easily and the illumination efficiency of the LED is increased. | 2009-07-30 |
20090189173 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images. | 2009-07-30 |
20090189174 | Light emitting diode package - A light-emitting diode (“LED”) package is disclosed. The LED package includes a substrate, a pad frame, an LED chip and a housing. The pad frame includes a conductive lead divided by insulation materials on the substrate. The LED chip is mounted on the conductive lead. The housing surrounds the LED chip and the conductive lead, and has opening recess exposing the LED chip and a part of the conductive lead. The conductive lead includes a protrusion extended in both directions substantially perpendicular to a longitudinal direction of the housing. | 2009-07-30 |
20090189175 | Side view type light emitting diode package - Disclosed is a side view light emitting diode (LED) package whose light emitting surface has been relatively expanded. The LED package includes a housing and a lead frame extended externally through the housing and bent in a direction of the recessed space. The housing includes a reflecting housing having a cavity and a supporting housing. | 2009-07-30 |
20090189176 | Light-emitting diode package - Disclosed is a light-emitting diode package. The light-emitting diode package includes an electrode pad on which a chip is placed; a housing having a window through which the chip is exposed; a housing wall defining the window; and an electrode lead extended from the electrode pad in a direction of the housing to be exposed outside a surface of the housing, wherein the housing wall formed in the direction comprises a first portion and a second portion thicker than the first portion to cover the electrode lead. | 2009-07-30 |
20090189177 | Light emitting diode package and manufacturing method thereof - Disclosed are a light emitting diode package and a manufacturing method thereof. According to an embodiment of the present invention, the method includes: manufacturing a package main body having a plurality of cavities, the cavities being formed in a line on one surface, through molding by putting thermoplastic polymer into a previously produced mold; forming an electrode passing through the package main body; mounting a light emitting diode chip on a basal surface of the each cavity formed in the package main body; connecting electrically the light emitting diode chip and the electrode by using a bonding means; and sealing the light emitting diode chip and the bonding means by using a molding resin. | 2009-07-30 |
20090189178 | LEADFRAME HAVING A HEAT SINK SUPPORTING PART, FABRICATING METHOD OF A LIGHT EMITTING DIODE PACKAGE USING THE SAME, AND LIGHT EMITTING DIODE PACKAGE FABRICATED BY THE METHOD - Disclosed are a leadframe having heat sink supporting parts, a light emitting diode package in which the leadframe is employed, and a fabricating method of a light emitting diode package using the leadframe. The leadframe includes an outer frame surrounding a predetermined region. The heat sink supporting parts extend inward to face each other from the outer frame. Each of the supporting parts has an end portion coupled to a heat sink. Further, lead terminals extend inward to face each other from the outer frame. The lead terminals are spaced apart from the supporting parts. Accordingly, a package main body can be formed by an insert molding technique after the heat sink is coupled to the end portions of the supporting parts, and the heat sink and the lead terminals can be easily aligned. | 2009-07-30 |
20090189179 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method for manufacturing flip-chip light emitting diode (LED) package. A recess array is formed at the top surface of a silicon wafer. Two through-wafer via holes are formed in the recess. A plurality of LED chips are flip-chip mounted in each of the recesses, respectively. Two electrodes of each LED chip are respectively covered the two via holes. An encapsulator for encapsulating each LED chip is arranged in the recess to provide a flat top surface. A metal layer is deposited on the bottom surface of the silicon wafer to electrically connecting with the electrodes through the two via holes. Metal lines which electrically connecting the electrodes are formed by patterning the metal layer. A plurality of silicon submounts, each including at least one recess, are cut off from the silicon wafer. A fluorescent layer is arranged on the top surface of the encapsulator. | 2009-07-30 |
20090189180 | SILICONE RESIN COMPOSITION - A silicone resin composition is provided, which includes polysiloxane including (PSA1), (PSA2), (PSB) and (PSC), and a hydrosilylating catalyst, wherein a weight ratio between (PSA2) and (PSA1) (w2/w1) is 0.03-0.2: | 2009-07-30 |
20090189181 | Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor - A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer. | 2009-07-30 |
20090189182 | Integrated RF ESD Protection for High Frequency Circuits - The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground. | 2009-07-30 |
20090189183 | DUAL TRIGGERED SILICON CONTROLLED RECTIFIER - The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage. | 2009-07-30 |
20090189184 | Semiconductor-On-Diamond Devices and Associated Methods - Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (Alp), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation. | 2009-07-30 |
20090189185 | EPITAXIAL GROWTH OF RELAXED SILICON GERMANIUM LAYERS - A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 10 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface. | 2009-07-30 |
20090189186 | Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor | 2009-07-30 |
20090189187 | Active area shaping for Ill-nitride device and process for its manufacture - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 2009-07-30 |
20090189188 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (Al | 2009-07-30 |
20090189189 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer. | 2009-07-30 |
20090189190 | High Electron Mobility Transistor, Field-Effect Transistor, Epitaxial Substrate, Method of Manufacturing Epitaxial Substrate, and Method of Manufacturing Group III Nitride Transistor - Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor | 2009-07-30 |
20090189191 | SEMICONDUCTOR DEVICE - A semiconductor device includes a field effect transistor formed of a GaN-based compound semiconductor and having a source electrode, a drain electrode, and a gate electrode, and a diode formed of a semiconductor material having a gandgap energy smaller than a bandgap energy of the GaN-based compound semiconductor. A cathode electrode and an anode electrode of the diode are electrically connected to the source electrode and the gate electrode of the field effect transistor, respectively. | 2009-07-30 |
20090189192 | DEPOSITION OF GROUP III-NITRIDES ON Ge - The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer ( | 2009-07-30 |
20090189193 | SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE - A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class. | 2009-07-30 |
20090189194 | Electrostatic Discharge (ESD) Protection Circuit Placement in Semiconductor Devices - Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices. | 2009-07-30 |
20090189195 | Radio Frequency (RF) Circuit Placement in Semiconductor Devices - Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices. | 2009-07-30 |
20090189196 | PROGRAMMABLE NANOTUBE INTERCONNECT - Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. Neighboring interconnect layers separated by planar vias may include communication lines that are perpendicularly oriented with respect to each of the neighboring interconnect layers. The nanotube structure may be chosen from a group comprising a polymer, carbon, and a composite material. A carbon nanotube film may be patterned in a metal layer to form the plurality of nanotube structures. A sputtered planar process may be performed across a trench of electrodes to create the carbon nanotube structures. | 2009-07-30 |
20090189197 | SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS - A solid-state imaging device includes: an imaging region including a plurality of light-receiving parts; a first transfer section provided on the imaging region and transferring, in a first direction, signals generated by the light-receiving parts; a second transfer section provided at a first side of the imaging region and transferring, in a second direction intersecting the first direction, the signals transferred from the first transfer section; an output circuit for outputting the signals; and bonding pads provided at the first side of the imaging region with the second transfer section sandwiched between the imaging region and the bonding pads. The bonding pads are arranged in a plurality of rows each extending in the second direction. Each of the bonding pads in one of the rows at least partially overlaps one of the bonding pads in another one of the rows when viewed in the first direction. | 2009-07-30 |
20090189198 | STRUCTURES OF SRAM BIT CELLS - An SRAM bit cell structure that can be produced in small sizes while maintaining performance is presented. In one configuration, an SRAM bit cell includes driver field effect transistors that are p-type field effect transistors, load field effect transistors that are n-type field effect transistors and transfer gates that are p-type field effect transistors. Each field effect transistor may be arranged on a substrate that will enhance performance. In one arrangement, the p-type field effect transistors may be arranged on a silicon ( | 2009-07-30 |
20090189199 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having, on a surface thereof, a (110) surface of Si | 2009-07-30 |
20090189200 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode. Accordingly, the semiconductor element itself can have air-tightness, it is not necessary to cover the gate electrode surface with a damp-proof protective film, gate capacitance of the semiconductor element is reduced, and high frequency characteristics and gain of the semiconductor element improve. | 2009-07-30 |
20090189201 | INWARD DIELECTRIC SPACERS FOR REPLACEMENT GATE INTEGRATION SCHEME - Inward dielectric spacers for a replacement gate integration scheme are described. A semiconductor device is fabricated by first providing a substrate having thereon a placeholder gate electrode disposed in a dielectric layer. The placeholder gate electrode is removed to from a trench in the dielectric layer. A pair of dielectric spacers is then formed adjacent to the sidewalls of the trench. Finally, a gate electrode is formed in the trench and adjacent to the pair of dielectric layers. | 2009-07-30 |
20090189202 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES AND A PROCESS OF FORMING THE SAME - An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type. | 2009-07-30 |
20090189203 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a substrate, a gate insulation film formed on the substrate, a gate electrode formed on the gate insulation film, sidewall insulation films provided on side surfaces of the gate electrode, and stress application layers embedded in source and drain regions located, on a surface of the substrate, at a position which sandwiches the gate electrode, and applying stress to a channel region located under the gate insulation film in the substrate, a height of upper ends of interfaces between the substrate and the stress application layers being higher than a height of a lower end of an interface between the substrate and the gate insulation film. | 2009-07-30 |
20090189204 | SILICON THIN FILM TRANSISTORS, SYSTEMS, AND METHODS OF MAKING SAME - Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures such that the precision, resolution, and registration is achieved to produce a high performing transistor. Such TFTs can be used in applications such as displays, packaging, labeling, and the like. | 2009-07-30 |
20090189205 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a source electrode and a drain electrode formed over a semiconductor substrate, a gate electrode formed over the semiconductor substrate and disposed between the source electrode and the drain electrode, a protection film made of an insulating material and formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode, and a gate side opening formed at least in one of a portion of the protection film between the source electrode and the gate electrode and a portion of the protection film between the drain electrode and the gate electrode and disposed away from all of the gate electrode, the source electrode and the drain electrode. | 2009-07-30 |
20090189206 | CMOS image sensor and method of fabricating the same - A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area. | 2009-07-30 |
20090189207 | Multicolor photodiode array and method of manufacturing - Novel structures of the photodetector having broad spectral ranges detection capability are provided. The photodetector offers high quantum efficiency>95% over wide spectral ranges, high frequency response>10 GHz (@3 dB). The photodiode array of N×N (or M×N) elements is also provided. The array also offers wide spectral detection ranges ultraviolet to 2500 nm with high quantum efficiency>95% and high frequency response of >10 GHz, cross-talk of <0.1%. In the array, each photodiode is independently addressable and is made either as top-illuminated or as bottom illuminated type detector. The photodiode and its array provided in this invention, could be used in multiple purpose applications such as telecommunication, imaging, and sensing applications including surveillance, satellite tracking, advanced lidar systems, etc. The advantages of this photodetectors are that they are uncooled and performance will not be degraded under wide range of temperature variation. | 2009-07-30 |
20090189208 | Multicolor photodiode array and method of manufacturing - Novel structures of the photodetector having broad spectral ranges detection capability are provided. The photodetector offers high quantum efficiency>95% over wide spectral ranges, high frequency response>10 GHz (@3 dB). The photodiode array of N×N (or M×N) elements is also provided. The array also offers wide spectral detection ranges ultraviolet to 2500 nm with high quantum efficiency>95% and high frequency response of >10 GHz, cross-talk of <0.1%. In the array, each photodiode is independently addressable and is made either as top-illuminated or as bottom illuminated type detector. The photodiode and its array provided in this invention, could be used in multiple purpose applications such as telecommunication, imaging, and sensing applications including surveillance, satellite tracking, advanced lidar systems, etc. The advantages of this photodetectors are that they are uncooled and performance will not be degraded under wide range of temperature variation. | 2009-07-30 |
20090189209 | SEMICONDUCTOR MEMORY DEVICE - In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other. | 2009-07-30 |
20090189210 | Semiconductor Flash Memory Device and Method of Fabricating the Same - A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess. | 2009-07-30 |
20090189211 | Non-Volatile Memory Arrays Having Dual Control Gate Cell Structures And A Thick Control Gate Dielectric And Methods Of Forming - Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips. The resulting control gates are separated from the strips by the intermediate dielectric layer and from the substrate surface by the tunnel dielectric layer, the second layer of dielectric material and the intermediate dielectric layer. | 2009-07-30 |
20090189212 | ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM - An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom. | 2009-07-30 |
20090189213 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 Å. | 2009-07-30 |
20090189214 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films s formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity. | 2009-07-30 |
20090189215 | NONVOLATILE FLASH MEMORY DEVICE AND METHOD FOR PRODUCING THE SAME - A method of producing metallic nanocrystals ( | 2009-07-30 |
20090189216 | SEMICONDUCTOR COMPONENT INCLUDING A DRIFT ZONE AND A DRIFT CONTROL ZONE - Semiconductor component including a drift region and a drift control region. One embodiment provides a drift zone and a drift control zone. A drift control zone dielectric is arranged between the first drift zone and the drift control zone and has at least two sections arranged at a distance from one another in a current flow direction of the component. At least one separating structure is arranged between the drift zone and the drift control zone in the region of an interruption, defined by the at least two sections, of the drift control zone dielectric and has at least one PN junction. | 2009-07-30 |